JP2519889Y2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device forming a sense amplifier.

[Conventional technology]

Conventionally, a sense amplifier is used to amplify a potential difference between read lines of memory cells of a semiconductor memory device.
An example of this sense amplifier circuit is shown in FIG. As shown, the sense amplifier circuit is a P-channel MOS transistor PMO.
S1 and PMOS2 and N-channel MOS transistors NMOS1 and NMOS2 are connected complementarily and crosswise, and a minute potential difference between B and B input between both gates is used as a driving input signal A,
Is amplified by.

The layout of this sense amplifier circuit is as shown in FIG. In the figure, I is the first metal wiring layer,
II is a second metal wiring layer, and III is a wiring layer having a relatively high resistance such as polycrystalline silicon. This high resistance wiring layer III is
It is configured as the gate electrode of the transistor. In the figure, C ₀₁ is a contact between the semiconductor layer and the first metal wiring layer I, C ₀₂ is a contact between the semiconductor device and the second metal wiring layer II, and C ₂₃ is a second metal wiring layer II and the high resistance wiring layer. III
Shows contact with.

[Problems to be solved by the invention]

In the conventional sense amplifier circuit described above, the gate electrodes of NMOS2 and NMOS2 are connected by the low resistance second metal wiring layer II on one B side of the input of the paired transistor elements, but the other input is connected. The NMOS1 and the PMOS1 are connected by a high resistance wiring layer III forming a gate electrode. For this reason, the resistances and the capacitances of the respective elements are different from each other, and the abilities of the elements are also different from each other, and the operation state becomes unbalanced as compared with the case where the resistances and the capacitances are balanced. That is, when there is a difference in capability between the elements, the circuit operation tends to be stable toward the operating state of the element with the strong ability, and the element with the high ability is required to shift to the operating state of the weak element. This is because it is necessary to provide a higher input than the device.

It is an object of the present invention to provide a semiconductor integrated circuit device capable of correcting the imbalance of resistance and capacitance of wiring and achieving the balance of element operation.

[Means for solving problems]

According to the present invention, when arranging a first channel type first and second MOS transistors and a second channel type third and fourth MOS transistors constituting a sense amplifier circuit, the first and third MOS transistors are arranged. When the transistors and the second and fourth MOS transistors respectively form an inverter, the first, second, third and fourth MOS transistors are arranged in this order, and each MOS is arranged so as to form a sense amplifier circuit. Each MOS transistor is interconnected by a wiring having a resistance lower than that of the gate electrode without extending the gate electrode of the transistor.

〔Example〕

 The present invention will now be described with reference to the drawings.

FIG. 1 is a layout diagram of an embodiment of the present invention, and is a diagram in which the sense amplifier circuit shown in FIG. 2 is configured. In the figure, PMOS1 and PMOS2 are P-channel MOS transistors, NMOS1 and NMOS2 are N-channel MOS transistors, respectively. These are P-type semiconductor layers P1, P2, N-type semiconductor layers N1 and N2 and polycrystalline silicon as a gate electrode. High-resistance wiring layer II
Composed of I. The respective transistors are connected complementarily and crosswise by a low resistance first metal wiring layer I and a second metal wiring layer II to form a sense amplifier circuit.

Here, in this example, the arrangement of the NMOS1 and the NMOS2 is replaced with that of the conventional one, and the space between the PMOS1 and the NMOS1 and the distance between the PMOS2 and the N
The size of the interval with MOS2 is made equal. Also, the high resistance wiring layer III forming the gate electrode of each transistor is formed as short as possible so as to be only the semiconductor layer and the contact region outside this, and each gate electrode is formed in this high resistance wiring layer III.
Each high resistance wiring layer III
Is connected to the first metal wiring layer I and the second metal wiring layer II at the contact, and they are connected to each other by utilizing the first metal wiring layer I and the second metal wiring layer II.

In the figure, C ₀₁ is a contact between the semiconductor layer and the first metal wiring layer I, and C ₀₂ is a contact between the semiconductor layer and the second metal wiring layer II.
, C ₁₂ is a contact between the first metal wiring layer I and the second metal wiring layer II, C ₁₃ is a contact between the first metal wiring layer I and the high resistance wiring layer III, and C ₂₃ is a metal wiring layer II. And the high resistance wiring layer III.

According to this layout configuration, only the gate electrode of each transistor uses a high resistance material, and the other wirings are composed of the low resistance first and second metal wiring layers I and II. Become. Therefore, the resistance of the wiring can be reduced, and in this example, the complementary connection of the transistors is made equal to each other, so that the elements can be balanced. As a result, imbalance between the elements can be corrected and stable operation can be obtained.

Here, in the above-described embodiment, the description has been made focusing only on the resistance, but if attention is paid to the capacitance, a low-capacity circuit can be similarly configured by selecting a low-capacity material.

[Effect of device]

As described above, the present invention limits the gate electrodes formed of the high resistance wiring layers of the elements arranged at positions distant from each other and sandwiching the other elements only to the region in the vicinity of each element, Moreover, since these gate electrodes are connected to each other by a wiring layer having a low resistance or a low capacitance extending between the elements, it becomes possible to reduce the resistance and capacitance of the circuit and balance them, and There is an effect that a good element operation can be obtained.

[Brief description of drawings]

FIG. 1 is a layout configuration diagram of a sense amplifier of the present invention, FIG. 2 is a circuit diagram of the sense amplifier, and FIG. 3 is a layout configuration diagram of a conventional sense amplifier. P1, P2 ... P-type semiconductor layer, N1, N2 ... N-type semiconductor layer, PMOS1, PM
OS2 ... P-channel MOS transistor, NMOS1, NMOS2 ... N-channel MOS transistor, I ... First metal wiring layer, II ... Second metal wiring layer, III ... High resistance wiring layer (polycrystalline silicon layer), _C01 , _C02 , C ₁₂ , C ₁₃ , C ₂₃ … Contact.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/092

Claims (1)

(57) [Scope of utility model registration request] 1. A pair of bit lines, a pair of sense amplifier drive lines, first channel type first and second MOS transistors whose sources are connected to one sense amplifier drive line, and respective sources. Is connected to the other sense amplifier drive line, the third and third channels of the second channel type
4MOS transistors, the drains of the first and third MOS transistors and the gates of the second and fourth MOS transistors are connected to one bit line, and the drains of the second and fourth MOS transistors are connected. The first
And a gate of the third MOS transistor is connected to the other bit line. In the semiconductor integrated circuit device including a sense amplifier circuit, the first, second, third and fourth MO transistors are provided.
The S-transistors are arranged in a line in this order, and these MOS transistors are wirings having a resistance lower than that of the gate electrode without extending and forming the gate electrode of each MOS transistor so as to form the sense amplifier circuit. A semiconductor integrated circuit characterized in that the semiconductor integrated circuits are connected to each other by.