JP3214580B2 - Differential amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier, and more particularly to a differential amplifier which operates on a one-chip LSI, for example, using a bipolar transistor as an active element and used as a sense amplifier of a semiconductor memory.

[0002]

2. Description of the Related Art A differential amplifier amplifies a difference voltage between two input signals input to respective control electrodes of two transistors forming a differential pair. In the sense amplifier for amplifying a minute difference voltage between two digit lines of a memory cell. Differential amplifiers include active transistors used in MOS transistors and bipolar transistors. In each case, a differential transistor pair (amplifying unit) for amplifying a two-input differential voltage is used. And a constant current source for flowing a constant current to the amplification unit;
And a load section connected to the output end of the amplification section and acting as a load. Hereinafter, a conventional differential amplifier will be described focusing on a portion related to the present invention, that is, a positional relationship between an amplifier, a constant current source, and a load on an LSI chip.

FIG. 3 is a diagram showing an example of a layout on a chip when a differential amplifier using bipolar transistors is applied to a sense amplifier of a one-chip semiconductor memory. Referring to FIG. 3, the semiconductor memory includes a memory cell 1, a level shifter 2, an amplifier 3, a constant current source 4, and a load 7 arranged on the same chip 100. Storage information of the memory cell 1, after being level shifted is input to the level shifter 2 via each of the two digit lines D _A / D _B, is input to the amplifier 3.
The output signal from the amplifier 3 is transmitted to the wiring 5A / 5B connected to its output terminal, and further transmitted to the load 7 by the output wiring 6A / 6B. Amplifying portion 3, each pair of digit lines D _A / D _B, i.e. is more provided corresponding to each column of the memory cell, the load unit 7 is provided only one common to the plurality of amplifying section . Although FIG. 3 shows only one word cell connected to a common word line (not shown) as a memory cell, each digit line pair D _A / D _B is actually Are connected to a plurality of memory cells that share them.

[0004] Here, in the layout on the chip 100 shown in FIG. 3, the signal voltage (digit line D _A / D _B each voltage) of the memory cell 1 has, for example, 50mV and small, an amplifier 3 constant current source 4 is usually arranged in the immediate vicinity of the memory cell 1 in order to minimize the parasitic capacitance and resistance and to avoid the influence of layout imbalance. On the other hand, the load unit 7 is provided only on the chip 100 as described above, and is a part for transmitting and receiving signals to and from circuits and devices outside the chip. Is done. Therefore, the connection between each amplifying unit 3 and the load unit 7 is made by a long wiring of, for example, about 10 mm (the output wiring unit 6A /
6B), the output end of the amplifier 3 is drawn out by the wiring 5A / 5B, and connected to the output wiring 6A / 6B.

Next, FIG. 4 is a circuit diagram schematically showing the layout shown in FIG. 3 at the element level, and the operation of the differential amplifier and its use on a one-chip LSI will be described with reference to FIG. The operational characteristics at this time will be described. In FIG. 4,
Although details of the memory cell portion are not shown,
The digit lines D _A / D _B from the memory cell 1, the level shifter 2 of the two npn-type bipolar transistor Q ₂₁ /
It is connected to the base electrode of Q _22.

[0006] In FIG. 4, the n-channel MOS transistors Q ₄₁ and Q ₄₂ of the constant current source 4 is to have the same current capacity and the load unit 7, n-channel constant-current MOS transistor Q ₇₃ / Q The current capabilities of the ₇₄ are made identical. Input terminals 8 for controlling the gate potentials of these constant current MOS transistors are connected to transistors Q ₄₁ , Q ₄₂ , Q ₄₃ , Q ₇₃ , Q ₇₄ and Q
A voltage that causes ₇₅ to saturate is input. In this state, the two input terminals 21A / 21 of the level shifter 2 are
B, the power supply level V _CC is input to the input terminal 21A,
When (V _CC -ΔV) (where ΔV is a small positive voltage) is input to the input terminal 21B, the transistors Q ₂₁ / Q ₂₂ are turned on. In this case, the potential of the emitter electrode of the node N _1A i.e. transistor _{Q 21 (V CC -V f)} ( where,
_Vf is the forward voltage between the base and the emitter of the bipolar transistor), and the node N _1B, that is, the transistor Q ₂₂
The potential of the emitter electrode - Since the _{(V CC △ V-V f} ), towards the potential of the node N _1A becomes higher than the potential of the node N _1B.

On the other hand, in the amplifying section 3, the potential of the base electrode of the npn-type bipolar transistors Q ₃₁ / Q ₃₂ , that is, the potential of the nodes N _2A / N _2B , respectively, is changed from the potential of the nodes N _1A / N _1B to the parasitic of the wiring. becomes a voltage drop only down the potential at the resistor R _1A / R _1B, usually, the input portion of the amplifying portion 3 is designed electrically very careful to be symmetrical, the node N _2A / The magnitude relation of the potential of N _2B is the node N _1A
Reflecting the magnitude relation of the potential of / N _1B, the potential of the node N _2A is higher than the potential of the node N _2B . Therefore, the collector electrode of the transistor Q ₃₁ transistors Q
A current larger than the collector current of ₃₂ flows.

The node N ₅ in the load section 7, that is, n
the potential V ₅ of the common base electrode of the pn-type bipolar transistor Q ₇₁ / Q7 ₂ has a value determined by the constant current n-channel MOS transistor Q ₇₅ current capability. Therefore, node N4 _A i.e. the potential of the emitter electrode of the node N4 _B i.e. bipolar transistor Q ₇₁ of the potential and the output wiring portion 6B of the emitter electrode of the transistor Q ₇₂ of the output interconnection 6A is substantially (V ₅ -V _f), and the node The potential of N _3A, that is, the collector electrode of the transistor Q ₃₁ of the amplification unit 3, and the potential of the node N _3B, that is, the collector electrode of the transistor Q ₃₂ , are respectively the voltage of the current I _A flowing through the parasitic resistance (R _2A + R _3A ) at the potential of the node N _4A. Potential plus the drop and node N
It becomes a potential obtained by adding the voltage drop due to current I _B flowing through the parasitic resistance _4B potential _{(R 2 B + R 3B)} . However, the parasitic resistance R
_2A and R _2B are parasitic resistances associated with the wirings 5A and 5B, respectively. On the other hand, the parasitic resistance R
_{Reference numerals 3A} and _3B denote resistors which collectively represent all parasitic resistances associated with the output wiring portions 6A and 6B.

As described above, the n-channel MOS transistors Q ₇₃ / Q ₇₄ for constant current have the same current capability, and their gate electrodes are operated from the input terminal 8 so as to saturate these transistors. Since the voltage is applied, the current flowing through the transistors Q ₇₃ / Q ₇₄ becomes the same. Therefore, the parasitic resistance parasitic resistance between the current I _A flowing to the (R _2A + R _3A) current flows in the _{(R 2B + R 3B) I} B
Is the current difference flowing through the resistors R _4A / R _4B in the load section 7 as it is. Since the resistance values of the resistors R _4A / R _4B are the same, a potential difference corresponding to the current difference flowing through these resistors appears between the two output terminals 71A / 71B.

Next, when the input of the level shifter 2 is inverted, the input level of the input terminal 21A becomes (V _CC- △ V) and the input level of the input terminal 21B becomes V _CC , the potential of the node N _1A becomes (V _CC − △ V−V _f ) and the potential of the node N _1B becomes (V
_CC - _Vf ). Then, according to the change, the node N2 _A
Starts to change toward (V _CC- （V-V _f ), and the potential at the node N _2B changes to (V _CC -V _f ).
However, in this case, the nodes N _2A / N ₁ are affected by the parasitic resistances R _1A / R _1B and the parasitic capacitances C _1A / C _1B attached to the wiring.
There is a delay in the inversion change of the 2 _B potential. Similarly, node N
_4A / N _4B and although attempts reversed in accordance with change in the potential also input of the level shifter 2 output terminals 71A / 71B, the their potential change, and the parasitic resistance R2 _A and the parasitic capacitance C _2A wiring 5A has, A delay occurs due to the influence of the parasitic resistance R _3A and the parasitic capacitance C _3A associated with the output wiring section 6A.
Similarly, the parasitic resistance R _2B and the parasitic capacitance C of the wiring 5B
_2B , the parasitic resistance R _3B and the parasitic capacitance C of the output wiring portion 6B.
_3B causes a delay.

Here, the parasitic capacitance C _2A of the wiring 5A is:
In addition to simply showing the parasitic capacitance of one wiring 5A shown in the drawing, the parasitic capacitance of each of all other wirings 5A not shown collectively represents the capacitance connected in parallel. Similarly, the parasitic capacitance C _2B of the wiring 5B is
B represents the parallel capacitance of the parasitic capacitance of B.

As described above, the differential amplifier is a one-chip LSI.
In addition to the inherent delay required for the inversion operation of the transistor pair in the amplification unit 3, the operation speed due to the parasitic capacitance and the parasitic resistance attached to the wiring from the amplification unit 3 to the load unit 7 Delay.

[0013]

As described above, when the conventional differential amplifier is used on a one-chip LSI, the differential amplifier is placed in the immediate vicinity of an input signal source (memory cell 1 in this example).
The level shifter 2, the amplifier 3, and the constant current source 4 are arranged in a block. Then, the wires 5A / 5B are pulled out from the output terminals of the respective differential amplifiers and output wiring portions 6
By connecting to the A / 6B, the output signal of the amplification unit 3 is transmitted to the load unit 7 disposed at the periphery of the chip far away. As a result, the operation speed of the differential amplifier is affected by the parasitic resistance and the parasitic capacitance in the wiring 5A / 5B and the output wiring 6A / 6B.

The above arrangement follows the arrangement in a differential amplifier using MOS transistors. That is, since a MOS transistor is essentially driven by a voltage, it is difficult to drive an excessive capacitive load (including a parasitic capacitance and a load capacitance) at a high speed in a circuit using the MOS transistor as an active element. For this reason, in the MOS transistor circuit, the parasitic capacitance of the wiring is designed to be as small as possible even in the circuit arrangement, and consideration is given to avoid the influence on the operation speed. The arrangement shown in FIG.
The arrangement of the differential amplifier transistor structure is also applied to a differential amplifier of a bipolar transistor structure, but in which attempted to lower the wiring capacitance, still increasing as the
Resistance and capacitance that are parasitic on the wiring between the width section 3 and the load section 7 are inevitable.

In this case, since a large number of wirings 5A / 5B are connected in parallel to the output wiring parts 6A / 6B according to the memory capacity, from the viewpoint of the parasitic capacitance, the load from each amplifying part is loaded. The parasitic capacitance as a whole until reaching the part becomes very large.

On the other hand, from the viewpoint of the parasitic resistance, each wiring 5A / 5
This means that the series resistance of the parasitic resistance at B and the parasitic resistance at the output wiring portions 6A / 6B is interposed. Here, since the output wiring portions 6A / 6B are long wirings as described above, the output wiring portions 6A / 6B are designed so that the resistivity is as low as possible in terms of material and structure. That is, for example, in an LSI in which two upper and lower aluminum wirings are used as metal wirings on a chip, the output wiring portions 6A / 6B have an aluminum layer that is thicker and therefore has a lower resistivity and a thicker interlayer insulating film and a smaller parasitic capacitance. Aluminum wiring is allocated. As a result, the wiring 5A / 5B between the amplifier 3 and the output wiring 6A / 6B
In this case, a lower aluminum wiring having a relatively smaller thickness than the upper aluminum wiring, a higher resistivity, a thin interlayer insulating film, and a large parasitic capacitance has to be used.
The parasitic resistance of B increases. Moreover, since the amplifying unit 3, in other words, the wirings 5A / 5B are provided corresponding to the respective columns of the memory cells, if the memory capacity is increased and the pitch of the arrangement of the respective memory cells is reduced, the amplifying unit 3 responds accordingly. As a result, the line width of the wiring 5A / 5B is also compressed, and the wiring resistance increases.

That is, in the arrangement of the conventional amplifier shown in FIG. 3, it is inevitable that the operating speed is reduced due to the parasitic resistance and the parasitic capacitance of the wires 5A / 5B. Moreover, the adverse effects of the parasitic capacitance and the parasitic resistance become more remarkable as the scale of the LSI increases. In order to prevent a decrease in the operation speed of the differential amplifier and further increase the speed in response to the future increase in the scale of LSIs, the device for reducing the parasitic resistance and the parasitic capacitance of the wirings 5A / 5B is made smaller than before. is necessary.

Accordingly, it is an object of the present invention to provide a differential amplifier which is excellent in high-speed operation and has a small operation speed due to the parasitic resistance and parasitic capacitance of the wirings 5A / 5B when used in a one-chip LSI. is there.

[0019]

According to the present invention, there is provided a differential amplifier comprising:
On the same semiconductor substrate, an amplifier comprising a pair of bipolar transistors, a constant current source for supplying a constant current to the amplifier, and a load comprising a pair of load circuits disposed apart from the amplifier and the constant current source And an output wiring section for connecting the amplification section and the load section, wherein the amplification section is disposed immediately below the output wiring section, and the output signal of the amplification section is substantially directly output. It is configured to transmit to the wiring section.

[0020]

Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a part related to the present invention of a one-chip semiconductor memory according to a first embodiment of the present invention. Referring to FIG. 1, the present embodiment is different from the conventional semiconductor memory shown in FIG. 3 in that an amplifying section 3 and a constant current source 4 of a differential amplifier are divided into blocks and arranged immediately below output wiring sections 6A / 6B. That is the point.

The differential amplifier in the present embodiment performs the same logical operation as the conventional differential amplifier, but operates at a higher speed than the conventional one. That is, in this embodiment,
Amplifying section 3 and constant current source 4 are arranged immediately below output wiring sections 6A / 6B, and a signal from amplification section 3 is output from output wiring sections 6A / 6.
Since the signal is directly transmitted to B, the parasitic resistance parasitic on the wiring from the amplification section 3 to the load section 7 is only the parasitic resistance of the output wiring section 6A / 6B formed by the upper aluminum wiring. Also, the wiring parasitic capacitance is only the parasitic capacitance associated with the output wiring portions 6A / 6B. That is, in this embodiment, the parasitic resistance and the parasitic capacitance in the wirings 5A / 5B from the amplifying unit 3 to the output wiring units 6A / 6B are reduced as compared with the conventional semiconductor memory shown in FIG. The operation speed of the dynamic amplifier is improved as compared with the conventional differential amplifier.

The present embodiment can have the above arrangement because the differential amplifier uses a bipolar transistor as an active element. That is, M
In the differential amplifier having the OS transistor configuration, it is difficult to dispose the amplifying unit 3 immediately below the output wiring units 6A / 6B as in the present embodiment. In the case of a differential amplifier having a MOS transistor configuration, the output signal level of the amplifying section (in this case, including the differential transistor pair and the load circuit) is a MOS level and is typically as high as 5.0V. Accordingly, the amplifying unit is connected to the output wiring (corresponding to the output wiring unit 6A / 6B in FIG. 3), which is a wiring connecting the output buffer for transferring signals to and from an external circuit or device and the amplifying unit. In this case, crosstalk occurs due to the coupling capacitance between the amplifying unit and the output wiring, and the potential of the output wiring is likely to fluctuate. On the other hand, a bipolar transistor is essentially a current drive, and a signal level processed by a differential amplifier using the bipolar transistor is, for example, at most about 100 mV. Therefore, there is substantially no change in potential on the output wiring as in a differential amplifier having a MOS transistor configuration.

Next, referring to FIG. 2 showing a layout of a one-chip semiconductor memory according to a second embodiment of the present invention,
This embodiment is different from the first embodiment shown in FIG. 1 in that the level shifter 2 and the constant current source 4 are blocked. Also in this embodiment, the amplifying unit 3 includes the output wiring units 6A / 6B.
, The operating speed is increased as in the first embodiment. As described above, in the differential amplifier according to the present invention, it is possible to achieve an increase in operating speed without particularly disposing the constant current source immediately below the output wiring section.

In each of the above two embodiments, the signal from the memory cell 1 is input to the amplifier 3 of the differential amplifier via the level shifter 2, but the signal source (in the case of the embodiment) Needless to say, the level shifter 2 is not particularly required depending on the signal level from the memory cell 1).

[0025]

As described above, according to the present invention,
An amplifier that constitutes a differential amplifier is disposed immediately below an output wiring section that connects the amplifier and the load section, and a signal from the amplifier is directly transmitted to the output wiring section, so that an output from the amplifier section is output. It is possible to prevent a decrease in operation speed caused by a parasitic resistance and a parasitic capacitance attached to a lead-out line leading to a wiring portion, and to provide a differential amplifier excellent in high-speed operation.

[Brief description of the drawings]

FIG. 1 is a block diagram of a part related to the present invention of a one-chip semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a part related to the present invention of a one-chip semiconductor memory according to a second embodiment of the present invention;

FIG. 3 is a block diagram of a part related to the present invention in a conventional one-chip semiconductor memory.

4 is an element-level circuit diagram schematically showing a state in which the block diagram shown in FIG. 3 is realized by a differential amplifier using bipolar transistors.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell 2 Level shifter 3 Amplification part 4 Constant current source 5A, 5B Wiring part 6A, 6B Output wiring part 7 Load part 8 Input terminal 21A, 21B Input terminal 71A, 71B Output terminal 100 chip

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁷ identification code FI H03F 3/45 (58) Investigated field (Int.Cl. ⁷ , DB name) G11C 11/41 G11C 11/401 G11C 11/416 H01L 21/8242 H01L 27/108 H03F 3/45

Claims (1)

(57) [Claims] 1. An amplifying unit comprising a pair of bipolar transistors on a same semiconductor substrate, a constant current source for supplying a constant current to the amplifying unit, and a pair of remote units arranged apart from the amplifying unit and the constant current source. A differential amplifier comprising: a load section comprising a load circuit; and an output wiring section connecting the amplifying section and the load section, wherein the amplifying section is disposed immediately below the output wiring section, Wherein the output signal is transmitted substantially directly to the output wiring section.