JPS59129460A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable a layout of high density by alternately arranging sense amplifiers at different end sections of data lines and disposing the data lines of adjacent sense amplifiers so as to be mutually held. CONSTITUTION:A plurality of data lines D5, D5', D6, D6' are arranged in parallel, and sense amplifiers SA5, SA6 are set up at every one pair (D5, D5'), (D6, D6') of two data lines. In the memory device, the amplifiers SA5, SA6 are arranged alternately at different end sections of the data lines D5, D5' and D6, D6', and data lines of adjacent sense amplifiers are disposed so as to be mutually held. Since such arrangement results in half sense amplifiers disposed in the same direction, pitches in a layout to the sense amplifiers can be increased up to approximately twice, thus allowing the layout of high density, then realizing the sense amplifiers under the optimum state without a limitation on the layout.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a layout of two data lines that should be electrically balanced in a semiconductor memory device.

FIG. 1 shows an example of the layout of a conventional storage device. In Fig. 1, the two data line pairs (Dl, D'work) and (D2, D'2), which are the two-man power of the sense amplifier SA, are arranged in parallel, and the sense amplifier has the same end with respect to the data line. It is placed on the side of the department. In this case, the layout pitch of the sense amplifier is determined by the pitch of the memory cells MC connected to the data line, and is therefore subject to significant restrictions. Generally, the memory cell size is 64, 256
However, as the capacity gradually increases to 1M bits, there is a tendency for the size to decrease.

This naturally extends to the sense amplifiers connected to the memory cells, and it is extremely difficult to fit the sense amplifiers into the memory cell pitch.In fact, contrary to the miniaturization of cells, the sense amplifiers have become more sensitive and circuit technology has increased. This was completely contrary to the trend of increasing complexity.

In addition, the word line W1 of the transistor connected to the memory cell
．． The number of contacts for W2 is equal to one for each bitjb of the memory cell. This has become a major hindrance to higher density as the space for contacts becomes unignorable when the memory capacity becomes large. Therefore, it is conceivable to make the contact to the word line common for every 2 btt memory cells, which is shown in FIG. However, in such a layout, the directions of the transistors with respect to the data lines are opposite to each other, and the misalignment causes imbalance for the same sense amplifier, making it difficult to sense data with high precision.

An object of the present invention is to provide a semiconductor memory device with excellent characteristics.

In the present invention, data lines are arranged in parallel, and sense amplifiers are arranged alternately at ends in a direction different from the data lines, and adjacent sense amplifiers in opposite directions sandwich the data lines connected to the sense amplifiers. It is characterized by arranging data lines connected to the .

A semiconductor memory device according to the present invention is shown in FIG.

The present invention provides a plurality of data lines Ds + D's r D
6 + D'6 are arranged in parallel and sense amplifiers SA5 and SA6 are provided for each set of two data lines (D5°D'5) and (D6.D'6). The present invention is characterized in that the amplifiers SA5 and SA6 are arranged alternately at different ends of the data lines, and the data lines of adjacent sense amplifiers are arranged so as to be sandwiched between them.

According to the present invention, the sense amplifiers arranged in the same direction are
Since it is 1/2 that of the conventional one, the layout pitch for the sense amplifier can be approximately doubled, so a high-density layout can be achieved, and the sense amplifier can be realized in an optimal state without layout constraints. Further, the number of contacts with the word line can be halved by making the transistors connected to the memory cells common for every 2 bits. Further, the relative position direction of the memory cells with respect to the data lines can be made the same for data lines having the same sense amplifier.

Therefore, the channel directions of the transistors between the memory cell and the data line can also be made the same. This can be similarly achieved for dummy memory cells.

Therefore, it is possible to realize a semiconductor memory device in which the electrical characteristics of the two data lines are balanced even if there is misalignment of the masks.

FIG. 4 shows an example of the arrangement of the memory cell section implementing the present invention shown in FIG. 3.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional memory, FIG. 2 is a block diagram showing another conventional memory, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a layout of a memory cell section. FIG. W1~w,. -------- Word line, D I + D'
l + ”・D8+D'8 data line, SA1...
, SA8... sense amplifier. 5- Kaya 10 D/Dt' D2
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Claims (1)

[Claims] Data lines are arranged in parallel, and sense amplifiers are arranged alternately at ends in a direction different from the data lines, and data connected to adjacent sense up lines in the opposite direction across the data lines connected to the sense amplifiers. A semiconductor memory device characterized by arranging lines.