KR960005567B1 - Dram cell array - Google Patents

Abstract

In the array method of the DRAM cell for a semiconductor memory, sources are united into one common source by arraying four cells to a cross shape, two gate electrodes are connected to the vertical gate line, and the two remaining gate electrodes respectively have gate pairs with cell gates. The gate pairs are connected to an inclined gate line, and the common source is connected to bit line arrayed in parallel through a bit line contact. The cell array increases integration of a chip by reducing an area of the bit line contact and a field area.

Description

DRAM Cell Array Method and DRAM Cell Array

1 is a view for explaining a conventional DRAM cell and its arrangement method.

2 is a view for explaining the DRAM cell array and the arrangement method of the present invention.

The present invention relates to a DRAM cell array method and a DRAM cell array in which four DRAM cells share one source / drain area, and a bit line contact is connected to the one source / drain area to increase integration.

FIG. 1 illustrates a conventional DRAM cell layout. FIG. 1 (a) shows an active region 10, and FIG. 1 (b) shows an active region 10 and a gate line. The arrangement state of 12 is shown.

In this active region, DRAM cells are positioned one by one, and two cells on the left and right each have one source / drain region, and a bit line contact 14 is formed therein.

FIG. 1 (c) shows a layout for showing a continuous arrangement of DRAM cells, in which the bit lines 16 pass in the longitudinal direction of the active region 10, and the two cell end bit line contacts 14 are disposed. These are formed one by one, and the word lines (gate lines) 12 are arranged so as to pass perpendicularly to the bit lines.

Information storage capacitors 18 are formed on the left and right ends of the active area.

In the active region 10, two source / drain regions are formed on both sides of the gate line 12, and two source / drain regions are combined at the center of the active region to be twisted through the bit line contact 14. A contact for connecting the storage electrode of the capacitor is formed in the source / drain region of the wrong source / drain region to be connected to the capacitor 18.

Thus, two DRAM cells including two source / drain regions and one gate and one magnetic capacitor are connected to one bit line contact in one active region 10.

In this arrangement structure, there is not one DRAM cell where the bit line 16 and the word line 12 cross each other, but half the number of intersection points of the bit line and the word line, that is, four intersections and two cells exist. It was an array structure.

In the method of reading the information value '0' or '1' of the unit cell of the DRAM cell, a word line is first selected, and the bit line and the adjacent bit line to which the unit cell is connected are connected to the sense amplifier. The information value is read by comparing the voltage difference between two bit lines.

Until now, the main interest in technology development has been to reduce the planar area of the chip in order to achieve high integration of the DRAM. Among them, the cell array part called the core occupies the largest area. This is going on.

Considering the planar structure of the unit cell, which is a component of the core, the area ratio of the capacitor to the unit cell area has been reduced to a considerable part by the development of stack or trench technology, but the planar area of the part where the bitline contact is formed is Due to the design margin with the layers, it was difficult to reduce the required area.

Therefore, when the DRAM class is 16M, 64M or more, the proportion of the planar area occupied by the drain contact portion connected to the bit line is gradually increased.

In addition, dummy word lines pass below or above the capacitors in the next cell, which often interferes with the introduction of stack or trench structure technology.

In order to solve the above-mentioned difficulties of the prior art, the active region is formed into a “+” shape to form cells in each branch, thereby forming four cells in one active region, and reducing the number of bit line contacts in half, The area of the field area is also greatly reduced. Four cells are arranged in a "+" shape to combine the sources into one common source, two gate electrodes are connected to the vertical gate line, and the other two gates are The gate pair is formed separately from the gates of the upper and lower cells, and the gate pair is connected to the inclined gate line, and the common source is arranged to be connected to the horizontally arranged bit lines through one bit line contact. DRAM cell array method.

In addition, the present invention provides a DRAM cell array in which four DRAM cells form one DRAM cell unit and a plurality of DRAM cell units are arranged, wherein the DRAM cell unit is an active area having a “+” shape, the center of the active area. A common source formed at the top of the branch, four branch drains formed at the four branch ends of the active region, first, two, three and four gates formed between the common source and the branch drain, and the branch drains, respectively, Four unit cells consisting of a storage capacitor, the common source is connected to the bit line arranged horizontally through the bit line contact, the second gate, and the fourth gate is a vertical gate disposed perpendicular to the bit line The first gate is connected to the line, and the first gate is gated with the third gate of the DRAM cell unit located at the upper portion thereof to pass through the gate contact. An inclined gate line connected to an inclined gate line that is inclined with respect to the vertical gate line, and the third gate forms a gate pair with the first gate of the DRAM cell unit located below and is inclined with respect to the vertical gate line through the gate contact Is made to be connected to.

2 is for explaining the present invention.

The DRAM cells of the present invention are bundled four by one to form a unit, each cell including a drain, a transistor consisting of a gate and a common source, and a storage capacitor.

As shown in FIG. 2 (A), the active area of this unit is rotated by 90 degrees of one of the conventional active areas “10 of FIG. Form in a similar shape. In other words, the active region 30 is shaped like a '+'.

As shown in FIG. 2 (b ') showing the XY line cross-section in FIGS. 2 (b) and 2 (b), the active source / drain area 33 is located at the center 32 of the + character. Are formed, and the source / drain regions 35 to be connected to the capacitor are formed at the four branch ends 34, respectively.

The gate electrode 38 is formed with a source / drain region 33 at the center and a source / drain region 35 at each end thereof.

Hereinafter, four gates are referred to as a first gate 38-1, a second gate 38-2, a third gate 38-3, and a fourth gate 38-4 in the clockwise direction.

This active region is regularly arranged like a checkerboard as shown in Fig. 2 (c), and the second gate and the fourth gate 38-2 and 38-4 are arranged in a vertical direction with the gate line 8 ( The first gate 38-1 is connected to the third gate of the unit above the active region to form a gate pair 40, and the third gate 38-3 The gate pair 40 is connected to the first gate of the unit under the active region.

This gate pair 40 is connected to the inclined gate lines 9 which are inclined through the gate line contacts 42, as shown in FIG.

The common source 33 is connected to the bit line 7 which is arranged perpendicular to the gate line 8 through the bit line contact 44.

The branch drain formed on the branch is connected to the storage capacitor of each cell, respectively.

A plurality of memory cell units are arranged in all directions, and one bit line contact is formed in a common source and connected to the bit line, and the first and third gates are connected to the bit line through gate contacts formed at upper and lower gate pairs. It is connected to an inclined gate line disposed inclined with respect to the gate line, and the second and fourth gates are connected to a vertical gate line disposed perpendicular to the bit line.

The capacitor of each cell is arranged to be positioned above the drain of each cell, as shown in FIG. 2 (d), and through the capacitor contact (not shown, it connects the storage electrode and the drain of the capacitor). Connected.

As described above, by arranging cells, the area occupied by the bit line contact can be greatly reduced, and the field area for insulation required for each two cells is formed in units of four cells, thus reducing the field area much. The degree of integration of the chip can be greatly increased.

Claims (3)

In the DRAM cell array method of a semiconductor memory, four cells are arranged in a "+" shape, the sources are combined into one common source, two gate electrodes are connected to a vertical gate line, and the other two gates are arranged at the top. A gate pair is formed along each gate of a cell, and the gate pair is connected to the inclined gate line, and the common source is arranged so that the common source is connected to a horizontally arranged bit line through one bit line contact. Arrangement method. In a DRAM cell array in which four DRAM cells form one DRAM cell unit and a plurality of DRAM cell units are arranged, the DRAM cell unit is an active area formed in a “+” shape and a common source formed at the center of the active area. And four branch drains formed at the four branch ends of the active region, first, two, three and four gates formed between the common source and the branch drain, respectively, for storage connected to the branch drain and located above the branch drain. Four unit cells comprising a capacitor, wherein the common source is connected to a bit line arranged horizontally through a bit line contact, and the second gate and the fourth gate are vertical gates disposed perpendicular to the bit line. Each of the first gates is gated to a third gate of the DRAM cell unit The gate is connected to the inclined gate line inclined with respect to the vertical gate line through the gate contact, and the third gate is gated with the first gate of the DRAM device unit located at the lower side to the vertical gate line through the gate contact. A DRAM cell array characterized in that it is connected to the inclined gate line arranged inclined. The DRAM cell array of claim 3, wherein the inclined gate line is formed of a metal.