JP2949859B2 - Bipolar CMOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar CMOS semiconductor device, and more particularly to a bipolar CMOS gate array.

[0002]

Conventionally, this kind of bipolar CMOS semiconductor device, as shown in FIG. 2, has a P ⁺ buried layer 25 and N ⁺ buried layer 26 in P-type silicon substrate 27, the P ⁺
An N-type MOSFET 14 is formed on the buried layer 25, and an NPN-type bipolar transistor (Tr) is formed on the N ⁺ buried layer 26.
11, a resistor 12, and a P-type MOSFET 13 are formed.

An NPN type bipolar transistor 11 is
Base (P ⁻ ) 35, emitter (N ⁺ ) 34, collector (N) formed in low concentration N-type epitaxial layer 24.
⁺ ) 28, a base 35 is supplied with a potential by a base contact electrode 20 and a P ⁺ layer 36, an emitter 34 is passed through the emitter contact electrode 19, and a collector is an N well 23 and an NPN type bipolar transistor. The potential is applied through the common contact electrode 18 with the collector 28.

The resistor 12 is composed of a resistance layer (P ⁻ ) 37 and a P ⁺ layer 38 that are connected to the resistance contact electrode 21 in pairs with the base contact electrode 20 as one end.

The P-type MOSFET 13 is composed of a source / drain 32 and a gate electrode 33 provided in an N well 23. The N-type MOSFET 14 includes a source / drain 29 and a gate electrode 30 provided in the P well 22.

The P well 22 is connected to the P well contact electrode 17 and the N ⁺ layer 3 from the ground wiring 16 on the upper surface of the chip.
1 gives the lowest potential on the chip. The highest potential on the chip is applied to the N well 23 from the power supply wiring 15 on the upper surface of the chip through the common contact electrode 18 and from the collector 28.

[0007]

The above-mentioned conventional bipolar CMOS semiconductor device has a structure in which the power supply potential and the ground potential for each element are supplied from the upper surface of the chip. For this reason, for the electromigration under the worst use condition, the fixed power supply wiring 15 and the fixed wiring 15 having a sufficient width and thickness must be widely distributed in the internal cell region. Therefore, there is a problem that the area where the signal wiring can be laid is small, and the area occupied by the wide power supply wiring is large, so that the area of the internal cell region is increased.

[0008]

SUMMARY OF THE INVENTION Bipolar CM of the present invention
In the OS semiconductor device, a power electrode is provided on the back surface of a high-concentration N-type silicon substrate, and an N-type
A high-concentration N-type layer for electrically connecting a power supply line formed on the upper surface of the epitaxial layer and the silicon substrate is provided in the type epitaxial layer.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of one embodiment of the present invention.

Referring to FIG. 1, a bipolar CMOS semiconductor device comprises a high-concentration N-type silicon substrate 10 having a power supply electrode 15A on the back surface, and a low-concentration N-type epitaxial layer 24 formed on this N-type silicon substrate 10. And this N
Well 22 provided in the epitaxial layer 24 and N
A well 23 and a high-concentration N-type (N ⁺ ) layer 24A for electrically connecting the power supply wiring 15 formed on the epitaxial layer via an insulating film to the N-type silicon substrate 10; N-type MOS including source / drain 29 and gate electrode 30 formed of polysilicon layer
FET 14 and P-type MOSFE comprising source / drain 32 and gate electrode 33 formed on N well 23
It mainly comprises a T13 and an NPN-type bipolar transistor 11 formed on an N-type epitaxial layer 24 and including an emitter 34 and a base 35.

In FIG. 1, reference numeral 17 denotes a P-well contact electrode, reference numeral 18 denotes a common electrode which serves as an N-well contact electrode and a collector contact electrode and is connected to a polysilicon layer.
9 is an emitter contact electrode, 20 is a base contact electrode, 21 is a resistance contact electrode, 36 is a P ⁺ layer, 37
Is a P ^- resistance layer, and 38 is a P ⁺ layer.

According to the present embodiment configured as described above,
The power supply potential is supplied to the power supply wiring 15 through the power supply electrode 15A on the back surface of the substrate and the N ⁺ layer 24A. Therefore, signal wiring 2
Since it is not necessary to distribute the power supply wiring 15 having a width of up to three times in the internal cell area, the area in which the signal wiring can be wired increases and the cell area can be reduced.

[0013]

As described above, according to the present invention, a power electrode is provided on the back surface of a high-concentration N-type silicon substrate, and the high-concentration N-type epitaxial layer formed on the silicon substrate and the silicon substrate is provided from the power electrode. Since the power supply potential is supplied to the upper surface of the silicon substrate via the N-type layer,
It is not necessary to widely distribute the fixed power supply wiring having a large width in the internal cell region on the upper surface of the silicon substrate. Therefore, there is an effect that a routable area of the signal wiring of the bipolar CMOS semiconductor device is increased and a cell area can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of the present invention.

FIG. 2 is a sectional view of an example of a conventional bipolar CMOS semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 N-type silicon substrate 11 NPN-type bipolar transistor 13 P-type MOSFET 14 N-type MOSFET 15 Power supply wiring 15A Power supply electrode 16 Ground wiring 18 Common contact electrode 22 P well 23 N well 24 N-type epitaxial layer 24A N ⁺ layer

Claims (1)

(57) [Claims] 1. A high-concentration N having a power supply electrode on a back surface.
-Type silicon substrate, a low-concentration N-type epitaxial layer formed on the silicon substrate, a P-well and an N-well provided in the epitaxial layer, and a power supply line formed on the epitaxial layer. High-concentration N-type layer electrically connecting the P-type MOSFET, an N-type MOSFET formed on the P-well, a P-type MOSFET formed on the N-well, and an NPN-type bipolar transistor formed on the epitaxial layer. And a bipolar CMOS semiconductor device.