JPH04287965A - Bipolar cmos semiconductor device - Google Patents

Abstract

PURPOSE:To increase the region for a signal line, and to reduce the area of a cell by applying a supply voltage from a source electrode to a power line by way of an N<+> layer. CONSTITUTION:A source electrode 15A is formed on the rear surface of a high concentration N type silicon substrate 10. In order to establish an electrical connection between the N type silicon substrate 10 and a power line 15, an N<+> layer 24A is provided inside an N type epitaxial layer 24.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bipolar CMOS semiconductor devices, and more particularly to bipolar CMOS gate arrays.

0002

2. Description of the Related Art Conventionally, this type of bipolar CMOS semiconductor device has a P+ buried layer 25 and an N+ buried layer 26 in a P type silicon substrate 27, as shown in FIG. An N-type MOSFET 14 is formed on top,
The structure is such that an NPN type bipolar transistor (Tr) 11, a resistor 12, and a P type MOSFET 13 are formed on the N+ buried layer 26.

[0003] The NPN type bipolar transistor 11 is
It is composed of a base (P-) 35, an emitter (N+) 34, and a collector (N+) 28 formed in a low concentration N-type epitaxial layer 24, and the base 35 has a base contact electrode 20 and a P+ layer 36. A potential is applied to the emitter 34, and an emitter contact electrode 1 is applied to the emitter 34.
A potential is applied to the collector through the common contact electrode 18 between the N well 23 and the collector 28 of the NPN type bipolar transistor.

The resistor 12 is composed of a resistive layer (P-) 37 and a P+ layer 38, which have the base contact electrode 20 as one end and are connected to the resistive contact electrode 21 in a pair.

The P-type MOSFET 13 is composed of a source/drain 32 provided in an N well 23 and a gate electrode 33. The N-type MOSFET 14 is composed of a source/drain 29 and a gate electrode 30 provided in a P well 22.

The lowest potential on the chip is applied to the P-well 22 from the ground wiring 16 on the top surface of the chip through the P-well contact electrode 17 and the N+ layer 31. The highest potential on the chip is applied to the N-well 23 from the collector 28 through the common contact electrode 18 from the power supply wiring 15 on the top surface of the chip.

[0007]

The conventional bipolar CMOS semiconductor device described above has a structure in which power supply potential and ground potential are supplied to each element from the top surface of the chip. Therefore, fixed power supply wiring 15 and ground wiring 16 having sufficient width and thickness must be widely distributed within the internal cell region to prevent electromigration under the worst use conditions. Therefore, the area where the signal wiring can be wired becomes smaller and the area occupied by the wide power supply wiring becomes larger, resulting in a problem that the area of the internal cell region increases.

[0008]

[Means for solving the problems] Bipolar CM of the present invention
An OS semiconductor device has a power supply electrode provided on the back surface of a highly doped N-type silicon substrate, and an N-type silicon substrate formed on the silicon substrate.
A highly doped N-type layer is provided in the epitaxial layer to electrically connect the silicon substrate to the power supply wiring formed on the upper surface of the epitaxial layer.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a sectional view of one embodiment of the present invention.

In FIG. 1, the bipolar CMOS semiconductor device includes a highly doped N-type silicon substrate 10 with a power supply electrode 15A provided on the back surface, and a lightly doped N-type epitaxial layer 24 formed on the N-type silicon substrate 10. And this N
P well 22 and N well provided in type epitaxial layer 24
A well 23, a highly doped N-type (N+) layer 24A that electrically connects the N-type silicon substrate 10 and the power supply wiring 15 formed on the epitaxial layer via an insulating film, and P
An N-type MO consisting of a source/drain 29 formed on a well 22, a gate electrode 30 made of a polysilicon layer, etc.
The SFET 14 and the source formed on the N well 23
P-type MOSF consisting of drain 32, gate electrode 33, etc.
It mainly consists of an ET 13 and an NPN bipolar transistor 11 formed of an emitter 34 and a base 35 formed on an N-type epitaxial layer 24 .

In FIG. 1, 17 is a P-well contact electrode, 18 is a common electrode that serves both as an N-well contact electrode and a collector contact electrode, and is connected to the polysilicon layer.
9 is an emitter contact electrode, 20 is a base contact electrode, 21 is a resistor contact electrode, 36 is a P+ layer, 3
7 is a P- resistance layer, and 38 is a P+ layer.

According to this embodiment configured as described above,
The power supply potential is between the power supply electrode 15A on the back side of the substrate and the N+ layer 24A.
The power is supplied to the power supply wiring 15 through the power supply line 15. Therefore, it is no longer necessary to distribute the power supply wiring 15, which has a width two to three times that of the signal wiring, within the internal cell region, so that the area where the signal wiring can be wired increases and the cell area can be reduced.

[0013]

As explained above, the present invention provides a power supply electrode on the back surface of a highly doped N-type silicon substrate, and connects the power supply electrode to the silicon substrate and the N-type epitaxial layer formed on the silicon substrate. Since it is configured so that a power supply potential can be supplied to the upper surface of the silicon substrate via the N-type layer,
There is no need to widely distribute wide fixed power supply wiring within the internal cell region on the upper surface of the silicon substrate. Therefore, the wiring area of the bipolar CMOS semiconductor device can be increased, and the cell area can also be reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of one embodiment of the present invention.

FIG. 2 is a cross-sectional view of an example of a conventional bipolar CMOS semiconductor device.

[Explanation of symbols]

10 N-type silicon substrate 11 NPN-type bipolar transistor 13
P-type MOSFET 14 N-type MOSFET 15 Power supply wiring 15A Power supply electrode 16 Ground wiring 18 Common contact electrode 22 P-well 23 N-well 24 N-type epitaxial layer 24A N+ layer

Claims (1)

[Claims] Claim 1: A highly doped N-type silicon substrate with a power supply electrode provided on the back surface, a lightly doped N-type epitaxial layer formed on this silicon substrate, and a P well provided on this epitaxial layer. a highly doped N-type layer that electrically connects the silicon substrate to a power supply wiring formed on the N-well and the epitaxial layer; an N-type MOSFET formed on the P-well; A bipolar CMOS semiconductor device comprising: a P-type MOSFET; and an NPN-type bipolar transistor formed in the epitaxial layer.