JP2000260891A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove an inversion preventing layer with high concentration which prevents reduction of element size, and to suppress adverse influence of a parasitic MOS transistor. SOLUTION: In this semiconductor device, one part of a polysilicon layer 41 or a collector electrode 16 connected with an emitter electrode 15 are arranged on insulating films 6 and 121, on parts equivalent to the channel regions of a parasitic MOS transistor for suppressing the operation of the parasitic MOS transistor, in an element region generated due to imparting of different potentials to the electrode wirings of each of regions 9, 10, and 8 of the base, emitter, and collector in a PNP bipolar element surrounded by P-type regions 4 and 5. Thus, at operation of the bi-polar transistor, potential control for suppressing the channel formation of the parasitic MOS transistor is achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a bipolar process having a high breakdown voltage or a Bi-CMOS (bipolar transistor / CMOS transistor mixed mounting) process.

[0002]

FIG. 6 is a cross-sectional view of a conventional NPN transistor. A high-concentration N ⁺ -type buried layer 2 is formed on a P-type semiconductor substrate 1. An N-type epitaxial layer 3 is formed on the substrate 1 including the buried layer 2. A high concentration P ⁺ type buried layer 4 is formed on the substrate 1. On this buried layer 4, a P-type region 5 separating the epitaxial layer 3 is formed. The epitaxial layer 3 surrounded by the P-type region 5 becomes an island region and becomes one element region.

A field insulating film 6 is formed on an epitaxial layer 3 serving as an element region. On the surface of the epitaxial layer 3 surrounded by the field insulating film 6, a low-concentration P ⁻ type region 7 as an internal base region and an N ⁺ region 8 as a collector region are formed. A P ⁺ region 9 as a base region and an N ⁺ region 10 as an emitter region are formed on the surface of the P ⁻ region 7. A deep N ⁺ region 11 reaching the N ⁺ type buried layer 2 is formed below the N ⁺ region 8 of the collector region.

[0006] An interlayer insulating film 12 is formed on the field insulating film 6 and the element region. Base electrode 14 connected to P ⁺ region 9, emitter electrode 15 connected to N ⁺ type region 10, and collector electrode 1 connected to N ⁺ region 8 on interlayer insulating film 12 through contact holes 13 respectively.
6 are formed. The base electrode 14, the emitter electrode 15, and the collector electrode 16 are led out onto the interlayer insulating film 12 as electrode wirings.

The electrode wiring (for example, aluminum) of the base electrode 14 is formed on the interlayer insulating film 12 so as to straddle between the P-type regions 7 (or 9) and 5. Therefore, the P-type regions 7 (or 9) and 5 are sourced,
There is a parasitic P-channel MOS transistor in which the drain region and the electrode wiring (14) on the interlayer insulating film 12 are used as a gate, and the island region of the N-type epitaxial layer 3 serving as a collector potential is used as a back gate. This parasitic P channel M
In order to prevent the OS transistor from turning on, a high-concentration N ⁺ -type layer 17 for preventing inversion is formed below the field insulating film 6 between the P-type regions 7 and 5.

The electrode wiring (for example, aluminum) of the collector electrode 16 is formed on the interlayer insulating film 12 by an N-type region 3 as an island region and a P-type region 5 for isolation.
Is formed so as to straddle between the other island regions 31 that have passed through. Therefore, there is a parasitic N-channel MOS transistor in which the N-type regions 3 and 31 are the source and drain regions, the electrode wiring (16) on the interlayer insulating film 12 is the gate, and the P-type region 5 is the back gate. This parasitic N channel M
In order to prevent the OS transistor from being turned on, a high-concentration P ⁺ -type layer 18 for inversion prevention is formed by increasing the concentration on the surface of the P-type region 5 under the field insulating film 6.

FIG. 7 is a sectional view of a conventional lateral PNP transistor. The same parts as those in FIG. 6 are denoted by the same reference numerals. A high-concentration N ⁺ -type buried layer 2 is formed on a P-type semiconductor substrate 1. An N-type epitaxial layer 3 is formed on the substrate 1 including the buried layer 2. A high concentration P ⁺ type buried layer 4 is formed on the substrate 1. On this buried layer 4, a P-type region 5 separating the epitaxial layer 3 is formed. P-type region 5
The epitaxial layer 3 surrounded by is an island region, and becomes one element region.

A field insulating film 6 is formed on the epitaxial layer 3 serving as an element region. On the surface of the epitaxial layer 3 surrounded by the field insulating film 6, a high-concentration P ⁺ -type region 21 as a collector region, a high-concentration P ⁺ region 22 as an emitter region, and N as a base region
⁺ Region 23 is formed. Under the N ⁺ region 23 of the base region, a deep N region reaching the N ⁺ type buried layer 2 is formed.
⁺ Region 11 is formed.

An interlayer insulating film 12 is formed on the field insulating film 6 and on the element region. A base electrode 24 connected to the N ⁺ -type region 23, an emitter electrode 25 connected to the P ^{+ -type} region 22, and a collector electrode connected to the P ⁺ -type region 21 via the contact holes 13 on the interlayer insulating film 12. 26 are formed. The base electrode 24, the emitter electrode 25, and the collector electrode 26 are led out onto the interlayer insulating film 12 as electrode wirings.

The electrode wiring (for example, aluminum) of the base electrode 24 is provided between the N-type region 3 as an island region and another island region 31 having passed through the P-type region 5 for isolation on the interlayer insulating film 12. Is formed so as to straddle. Therefore, N
N-type channel regions 3 and 31 are source and drain regions, an electrode wiring (base electrode 24) on interlayer insulating film 12 is a gate, and P-type region 5 is a back gate.
There is an OS transistor. This parasitic N-channel MO
In order to prevent the S transistor from turning on, a high concentration P ⁺ -type layer 27 for preventing inversion, in which the concentration on the surface of the P-type region 5 under the field insulating film 6 is increased.

The electrode wiring (for example, aluminum) of the collector electrode 26 is formed on the interlayer insulating film 12 so as to straddle between the P-type regions 21 and 5. Therefore, the P-type regions 21 and 5 are connected to the source and drain regions and the electrode wiring on the interlayer insulating film 12 (collector electrode 26).
There is a parasitic P-channel MOS transistor having a gate as a gate and an island region of the N-type epitaxial layer 3 serving as a base potential as a back gate. This parasitic P channel M
In order to prevent the OS transistor from turning on, a high-concentration N ⁺ -type layer 28 for preventing inversion is formed under the field insulating film 6 between the P-type regions 21 and 5.

According to the configuration shown in FIG. 6 or FIG.
In order to prevent the OS transistor from being turned on, it is necessary to provide the N ⁺ -type layer 17, the P ⁺ -type layer 18, or the N ⁺ -type layer 28 and the P ⁺ -type layer 27, which are the field inversion prevention layers, and occupy them. The area hinders the size reduction of the bipolar transistor element.

That is, as the required withstand voltage of the bipolar transistor increases, the concentration of the field inversion prevention layer also needs to be increased accordingly. Therefore, it is necessary to keep a sufficient distance between the field inversion prevention layer itself and the diffusion layer to ensure the withstand voltage between the other diffusion regions, which causes a problem that the element size is increased. In many cases, additional steps are required.

[0014]

Conventionally, it has been necessary to provide a high-concentration diffusion layer serving as a field inversion prevention layer for the purpose of suppressing the operation of a parasitic MOS transistor which adversely affects the operation of a bipolar transistor element. However, there is a problem that as the higher withstand voltage is required, the distance between the diffusion layer itself and the other diffusion region must be increased in order to secure the withstand voltage between the diffusion layer itself and the other diffusion region, which leads to an increase in element size.

The present invention has been made in consideration of the above circumstances, and has as its object to eliminate the above-described high-concentration diffusion layer that hinders the reduction of the element size and to reduce the adverse effect of the parasitic MOS transistor. It is to provide a semiconductor device which suppresses the problem.

[0016]

SUMMARY OF THE INVENTION A semiconductor device according to the present invention is a bipolar transistor having a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type on the substrate, and a region of the second conductivity type thereon. A first conductivity type buried layer formed on the substrate so as to surround the bipolar transistor element region to electrically separate the element region from the other bipolar transistor element region, A conductive type region, an insulating film on the bipolar transistor element region, an electrode wiring of the bipolar transistor element formed with the insulating film interposed therebetween, and the bipolar transistor element generated by applying different potentials to the electrode wiring, respectively. The channel region of the parasitic MOS transistor to suppress the operation of the parasitic MOS transistor in the region Provided on said insulating film on a portion corresponding to characterized by including a conductive layer that is controlled by the potential applied of said electrode wire.

In the present invention, the conductive layer is controlled by the potential applied to the electrode wiring of the bipolar transistor element,
In order to suppress the activation of the parasitic MOS transistor inside the element region, it is formed between the insulating films on the channel region of the parasitic MOS transistor.

Therefore, for example, the conductive layer is a part of the second electrode wiring located under the first electrode wiring among the electrode wirings of the bipolar transistor element. Further, the conductive layer is electrically connected to a first electrode wiring among the electrode wirings of the bipolar transistor element, and is located below the second electrode wiring.

By providing such a conductive layer, it is not necessary to provide a high concentration layer for preventing inversion below the field insulating film.

[0020]

FIG. 1 is a sectional view showing a configuration of an NPN bipolar transistor according to a first embodiment of the semiconductor device of the present invention. P-type silicon semiconductor substrate 1
A high concentration N ⁺ type buried layer 2 is formed thereon. An N-type epitaxial layer 3 is formed on the substrate 1 including the buried layer 2. In addition, a high-concentration P ⁺
A mold buried layer 4 is formed. On this buried layer 4, a P-type region 5 for separating the epitaxial layer 3 is formed (P-type guard ring layer). The epitaxial layer 3 surrounded by the P-type region 5 becomes an island region and becomes one element region.

A field insulating film 6 is formed on the epitaxial layer 3 serving as an element region. On the surface of the epitaxial layer 3 surrounded by the field insulating film 6, a low-concentration P ⁻ type region 7 as an internal base region and an N ⁺ region 8 as a collector region are formed. On the surface of the P ⁻ type region 7, a P ⁺ region 9 as an external base region and an N ⁺ type region 10 as an emitter region are formed. A deep N ⁺ region 11 reaching the N ⁺ type buried layer 2 is formed below the N ⁺ region 8 of the collector region.

A conductive polysilicon layer 41 is selectively formed on field insulating film 6. The polysilicon layer 41 is provided so as to entirely or partially overlap the P-type region 5 for isolation.

A first interlayer insulating film 121 is formed on the field insulating film 6 and on the element region. Interlayer insulating film 1
The base electrode 14 connected to the P ⁺ region 9, the emitter electrode 15 connected to the N ⁺ type region 10, the collector electrode 16 connected to the N ⁺ region 8, and A contact wiring 42 connected to the polysilicon layer 41 is formed.

On the interlayer insulating film 121, a second interlayer insulating film 122 is formed. The electrode wiring 151 of the emitter electrode 15 is drawn out through the contact hole 132. The electrode wiring 151 is also connected to the polysilicon layer 41 via another contact hole 132. Therefore, the polysilicon layer 41 is set to the same potential as the emitter electrode 15.

The base electrode 14 is drawn out onto the interlayer insulating film 122 through a contact hole (not shown).
The electrode wiring of the collector electrode 16 is
1 is formed.

In the above configuration, the electrode wiring of the polysilicon layer 41 and the collector electrode 16 is important. First,
In addition, the polysilicon layer 41 is provided on the field insulating film 6 on the P-type region 5, and has an emitter potential which is the lowest potential for the operation of the NPN bipolar transistor element. As a result, the N-type region 3 which is an island region, another island region 31 having passed through the P-type region 5 for isolation is used as a source / drain region, and an electrode wiring (collector electrode 16) on the interlayer insulating film 121 is used as a gate. Then, the activation of the parasitic N-channel MOS transistor using the P-type region 5 serving as a guard ring as a back gate is suppressed.

Second, the electrode wiring of the collector electrode 16 is as follows:
A portion 16a is provided on the first interlayer insulating film 121 and located between the P-type regions 7 (or 9) and 5. The collector electrode 16 is at the highest potential for operation of the NPN bipolar transistor device. As a result, the P-type regions 7 (or 9) and 5 are connected to the source and drain regions and the emitter electrode 15 (or the base electrode 1) on the interlayer insulating film 122.
4) The operation activation of the parasitic P-channel MOS transistor having the gate and the island region of the N-type epitaxial layer 3 serving as the collector potential as the back gate is suppressed.

FIG. 2 is a plan view showing a main part of FIG.
The same parts as those in FIG. 1 are denoted by the same reference numerals. The electrode wiring 141 of the base electrode 14 not shown in FIG. 1 is shown. Each electrode and wiring is, for example, aluminum. The polysilicon layer 41 (hatched) is the N-channel parasitic M
In order to cut off the channel of the OS transistor, it may be formed on the field insulating film 6 so as to partially overlap the P-type region 5 which is a guard ring layer. Also,
The polysilicon layer 41 may be provided on the channel region where an N-channel parasitic MOS transistor is formed, so that the potential of the emitter electrode is applied, and does not surround the element region as in the case of the guard ring. A configuration is also conceivable.

The wiring pattern (thick line) of the collector electrode 16 is wider on the first interlayer insulating film 121 than other electrode wiring patterns. The reason is that a high potential is applied in operation, so that the resistance is reduced. Part of this wiring pattern is the parasitic M of the P channel.
In order to cut off the channel of the OS transistor, a P-type region 7 is formed below the emitter electrode 15 and the base electrode 14.
It suffices if it exists on the interlayer insulating film 121 immediately above the N-type region located between (or 9) and 5.

FIGS. 3 and 4 are plan views showing the modification of FIG. 2 (the same reference numerals are used). The wiring pattern (thick line) of the collector electrode 16 extends on the insulating layer immediately below the emitter electrode 15 and the base electrode 14 and between the P-type regions 7 (or 9) and immediately above the N-type region. ing.
If this configuration is satisfied, the operation of the P-channel parasitic MOS transistor can be suppressed. Therefore, the base region (P ⁺
Instead of a pattern (FIG. 3) surrounding the periphery of the region 9) and the emitter region (N ⁺ type region 10), the wiring pattern of the emitter electrode may be extended from one side (FIG. 4). . The polysilicon layer 41 may be located on the channel region where an N-channel parasitic MOS transistor is formed, so that the potential of the emitter electrode is applied. Therefore, it may be formed so as to partially overlap the insulating film immediately above the P-type region 5 which is the guard ring layer below the wiring pattern (thick line) of the collector electrode 16. If this configuration is satisfied, a configuration in which the element region is not surrounded like the guard ring as shown in FIG. 4 may be used.

According to the above configuration, the potential relation between the gate and the source of the parasitic MOS transistor inherent in the NPN bipolar transistor element structure is determined by using the potential relation of the electrode wiring of the NPN bipolar transistor element.
The OS transistor operation cannot be activated.

Therefore, the N-channel and P-channel parasitic MOS transistors which adversely affect the operation of the NPN bipolar transistor element without providing a field inversion prevention layer for increasing the concentration according to the breakdown voltage as in the prior art are provided. Operation can be suppressed. As a result, the size of the bipolar transistor element is reduced.

FIG. 5 is a sectional view showing the structure of a lateral PNP bipolar transistor according to a second embodiment of the semiconductor device of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals. A high-concentration N ⁺ -type buried layer 2 is formed on a P-type silicon semiconductor substrate 1. An N-type epitaxial layer 3 is formed on the substrate 1 including the buried layer 2.
Are formed. A high concentration P ⁺ type buried layer 4 is formed on the substrate 1. On this buried layer 4, a P-type region 5 for separating the epitaxial layer 3 is formed (P-type guard ring layer). The epitaxial layer 3 surrounded by the P-type region 5 becomes an island region and becomes one element region.

A field insulating film 6 is formed on the epitaxial layer 3 serving as an element region. On the surface of the epitaxial layer 3 surrounded by the field insulating film 6, a high-concentration P ⁺ -type region 21 as a collector region, a high-concentration P ⁺ region 22 as an emitter region, and N as a base region
⁺ Region 23 is formed. Under the N ⁺ region 23 of the base region, a deep N region reaching the N ⁺ type buried layer 2 is formed.
⁺ Region 11 is formed.

A polysilicon layer 41 is selectively formed on the field insulating film 6. This polysilicon layer 41
Is provided so as to entirely or partially overlap the P-type region 5 for isolation.

A first interlayer insulating film 121 is formed on the field insulating film 6 and on the element region. Interlayer insulating film 1
21 via respective contact holes 131,
Base electrode 24, P ⁺ emitter electrode 25 connected to the region 22, a collector electrode 26 connected to the P ⁺ -type region 21 connected to the N ⁺ -type region 23, contact wires are further connected to the polysilicon layer 41 42 are formed.

On the interlayer insulating film 121, a second interlayer insulating film 122 is formed. The electrode wiring 261 of the collector electrode 26 is drawn out through the contact hole 132. The electrode wiring 261 is also connected to the polysilicon layer 41 via another contact hole 132. Therefore, the polysilicon layer 41 is set to the same potential as the collector electrode 26.

The base electrode 24 is connected to the contact hole 13
2 is drawn out onto the interlayer insulating film 122 (electrode wiring 241). The electrode wiring of the emitter electrode 25 is formed on the interlayer insulating film 121.

In the above structure, the electrode wiring of the polysilicon layer 41 and the emitter electrode 25 is important.

First, the polysilicon layer 41 is provided on the field insulating film 6 on the P-type region 5.
That is, the collector potential is the lowest potential in operation of the NP bipolar transistor element. As a result, the N-type region 3 as an island region and the P-type region 5 for isolation are formed.
Of the parasitic N-channel MOS transistor having the source and drain regions as the source / drain regions, the gate as the electrode wiring (emitter electrode 25) on the interlayer insulating film 121, and the back gate as the P-type region 5 as a guard ring. Suppress operation activation.

Second, the electrode wiring of the emitter electrode 25 is
That is, a portion 25a located between the P-type regions 21 and 5 is provided on the first interlayer insulating film 121. The emitter electrode 25 has the highest potential for the operation of the PNP bipolar transistor element. As a result, the P-type regions 21 and 5 are formed in the source and drain regions and the interlayer insulating film 121.
The activation of the parasitic P-channel MOS transistor with the upper emitter electrode 25 as the gate and the island region of the N-type epitaxial layer 3 serving as the base potential as the back gate is suppressed.

According to the above configuration, the potential relation between the gate and the source of the parasitic MOS transistor inherent in the PNP bipolar transistor element structure is determined by utilizing the potential relation between the electrode wiring of the PNP bipolar transistor element and the parasitic M transistor.
The OS transistor operation cannot be activated.

Therefore, the N-channel and P-channel parasitic MOS transistors which adversely affect the operation of the PNP bipolar transistor element are not provided without providing the field inversion prevention layer for increasing the concentration according to the breakdown voltage as in the prior art. Operation can be suppressed. As a result, the size of the bipolar transistor element is reduced.

The configuration of each of the above embodiments is useful for a high-breakdown-voltage element composed of a bipolar transistor or Bi-CMOS. Even if the demand for a higher breakdown voltage increases, the activation of the operation of the parasitic MOS transistor is suppressed in accordance with the potential applied to the electrode of the bipolar transistor which actually operates. There is an advantage that there is no need to change the process such that the impurity concentration of the field inversion prevention layer must be increased in response to a request for a breakdown voltage.

[0045]

As explained above, according to the present invention,
A conductive layer controlled by the potential given by the electrode wiring of the bipolar transistor element is provided between the insulating layers on the channel region of the parasitic MOS transistor so that the activation of the parasitic MOS transistor in the element region can be suppressed. This eliminates the need to provide a high-concentration layer for preventing field inversion corresponding to the breakdown voltage below the field insulating film, and contributes to a reduction in element size.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of an NPN bipolar transistor according to a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a plan view showing a main part of FIG. 1;

FIG. 3 is a plan view showing a first modification of FIG. 2;

FIG. 4 is a plan view showing a first modification of FIG. 2;

FIG. 5 is a sectional view showing a configuration of a lateral PNP bipolar transistor according to a second embodiment of the semiconductor device of the present invention.

FIG. 6 is a cross-sectional view of a conventional NPN transistor.

FIG. 7 is a cross-sectional view of a conventional lateral PNP transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P type silicon semiconductor substrate 2 ... N ⁺ type buried layer 3 ... N type epitaxial layer 4 ... P ⁺ type buried layer 5 ... P type region (P type guard ring layer) 6 ... Field insulating film 7 ... P ^- type region (internal base region) 8 ... N ⁺ region (collector region) 9 ... P ⁺ region (external base region) 10 ... N ⁺ type region (emitter region) 11 ... deep N ⁺ region 121, 122 ... interlayer insulation Films 131, 132 Contact holes 14, 24 Base electrodes 15, 25 Emitter electrodes 151, 141, 241 and 261, Electrode wiring 16, 26 Collector electrodes 21 P ⁺ type region (collector region) 22 P ⁺ region (Emitter region) 23 ... N ⁺ region (Base region) 41 ... Polysilicon layer 42 ... Contact wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/331 H01L 29/78 618A 29/73 29/786 21/336 F-term (Reference) 5F003 AP04 BA11 BA24 BA25 BA93 BB08 BC08 BE08 BH01 BH06 BH10 BH18 BJ15 BN01 BP01 BP31 5F032 AB01 CA17 DA12 DA42 DA53 5F033 HH04 HH08 JJ01 JJ08 KK01 VV03 XX03 XX26 5F048 AA01 AC05 BA07 BA12 EB05 CA03 DD03 CA03 FF12 GG02 GG12 GG22 GG23 GG32 GG42 HJ04 HL03 HM02 HM04 HM12 HM13

Claims (3)

[Claims] A bipolar transistor element region having a first conductivity type semiconductor substrate, a second conductivity type buried layer on the substrate, and a second conductivity type region thereon; A buried layer of a first conductivity type formed on the substrate so as to surround the bipolar transistor element region to electrically separate the device region from the first transistor region and a first conductivity type region thereon; And an electrode wiring of the bipolar transistor element formed with the insulating film interposed therebetween; and an operation of a parasitic MOS transistor in the bipolar transistor element region caused by applying different potentials to the electrode wiring. Parasitic MO for
A conductive layer provided on the insulating film on a portion corresponding to a channel region of an S transistor, the conductive layer being controlled by a potential given by the electrode wiring. 2. An NPN transistor element region including an N-type buried layer formed on a P-type silicon substrate and an N-type epitaxial layer formed thereon, and formed so as to surround the surface of the element region. A field insulating film, a P-type buried layer formed so as to surround the device region for electrically isolating the device region from a region of another epitaxial layer, and a P-type diffusion layer thereon, A low-concentration P-type internal base region formed on the surface of the element region, a high-concentration N-type emitter region formed on the surface of the region, a high-concentration P-type external base region, and the internal base region A high-concentration N-type collector region separated from the semiconductor device; an insulating film formed on the element region and the field insulating film; and at least a part of the isolation P-type diffusion layer. A conductive layer formed on the field insulating film and electrically connected to the emitter region, a P-type region of the internal base region and the external base region, and a region between the P-type diffusion layer for isolation. A first-layer electrode wiring formed on the insulating film so as to cover at least a part of the first layer and electrically connected to the collector region; and the insulating layer so as to cross over a part of the first-layer electrode wiring. A second layer electrode wiring formed on the film and electrically connected to the emitter region. 3. An element region of a PNP transistor comprising an N-type buried layer formed on a P-type silicon substrate and an N-type epitaxial layer formed thereon, and formed so as to surround the surface of the element region. A field insulating film, a P-type buried layer formed so as to surround the device region for electrically isolating the device region from a region of another epitaxial layer, and a P-type diffusion layer thereon, A high-concentration N-type base region, a high-concentration P-type emitter region, and a high-concentration P-type collector region formed on the surface of the element region, respectively; and an insulation layer formed on the element region and the field insulating film. A conductive layer formed on the field insulating film so as to cover at least a part of the isolation P-type diffusion layer and electrically connected to the collector region; A first layer formed on the insulating film so as to cover at least a part of the region between the P-type region of the region and the P-type diffusion layer for isolation, and electrically connected to the emitter region. An electrode wiring; and a second-layer electrode wiring formed on the insulating film so as to cross over a part of the first-layer electrode wiring and electrically connected to the collector region. Semiconductor device.