KR100709478B1 - Semiconductor device capable of decreasing leakage current by parasitic field transistor and method of manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor device capable of reducing leakage current caused by a parasitic field transistor, and a method of manufacturing the same. By blocking the generation of the parasitic field transistor by connecting to the metal wiring, it is possible to suppress the occurrence of leakage current and improve the electrical characteristics of the device.

Parasitic Field Transistors, Leakage Current, Device Separators

Description

Semiconductor device capable of reducing leakage current by parasitic field transistor and method of manufacturing the same             

1 is a circuit diagram illustrating a string structure of a NAND flash memory device.

2 is a cross-sectional view of a device for explaining a cause of leakage current during an erase operation.

3A and 3B are characteristic graphs showing the amount of leakage current generation.

4 is a cross-sectional view of a device for describing a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101, 401: semiconductor substrate 102, 402: N well

103, 403: Triple P well 104, 104a, 404, 404a: device isolation membrane

105, 405 tunnel oxide film 106, 406 floating gate

107, 407: dielectric film 108, 408: word line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same that can reduce leakage current caused by parasitic field transistors.

In general, leakage current exists in all semiconductor devices. A case of the NAND flash memory device will be described as an example.

1 is a circuit diagram illustrating a string structure of a NAND flash memory device.

Referring to FIG. 1, a cell array of a NAND flash memory has a string-based structure, and the string is a source select transistor SST connected to a source line SL and a drain select transistor DST connected to a bit line BL. ) And flash memory cells C1 to Cn connected in series between the source select transistor SST and the drain select transistor DST. Here, 16 or 32 flash memory cells C1 to Cn are connected in series between the source select transistor SST and the drain select transistor DST.

The erase operation of the NAND flash memory device is performed in the following manner.                         

For a 512M NAND flash memory device, the memory array is divided into two planes, and the plane is divided into 2048 blocks. One block includes a plurality of strings in which 16 cells are connected (for example, 528 × 2 × 8).

In general, an erase operation of a NAND flash memory device is performed in blocks. In more detail, the source select line SSL, the drain select line DSL, the source line SL, and the bit line BL are floated, and the flash memory cells C1 to Cn included in the selected block are plotted. A voltage of 0 V is applied only to the word lines WL1 to WLn. In this state, when a high voltage (for example, 16V to 20V) is applied as an erase voltage to the triple P well in which the flash memory cells C1 to Cn are formed, electrons are emitted from the floating gate to perform an erase operation.

When the erase characteristic of the flash memory device is tested, the test is performed under the above conditions. When the erase characteristic is tested on a block-by-block basis, since all 4096 blocks must be tested, the total test time is greatly increased by the erase test. Therefore, in the test, the erase operation is performed by a chip erase method in which the entire chip is erased without performing the erase operation in units of blocks.

However, when the erase operation is performed by the block erase method, the defect rate is low, whereas when the erase operation is performed by the chip erase method, the defect rate rapidly increases (at least 3 times, and as much as 10 times).

The result of analyzing the cause of this phenomenon is as follows.

2 is a cross-sectional view of a device for explaining a cause of leakage current during an erase operation.

Referring to FIG. 2, the N well 102 and the triple P well 103 are formed in the P-type semiconductor substrate 101, and the trench type isolation layers 104 and 104a are formed in the device isolation region. The tunnel oxide film 105 and the floating gate 106 are formed in a stacked structure on the active region, and the dielectric film 107 and the word line 108 serving as the control gate are formed in a direction perpendicular to the device isolation film 104.

The word line 108 is connected to an X-decoder (not shown) formed in the peripheral circuit region, and a parasitic field transistor (PFT) is formed in a portion extending for the connection. Specifically, the triple P well 103 serves as a source, the N well 102 under the device isolation layer 104a serves as a channel region, and the P type semiconductor substrate 101 serves as a drain. An extended word line 108a serves as a gate.

In this state, when a high voltage is applied to the triple P well 103 for the erase operation, a channel is formed in the N well 102 under the device isolation film 104a, and the triple P well 103 is changed into the P-type substrate 101. Current (leakage current) flows.

3A and 3B are characteristic graphs showing the amount of leakage current generation.

Referring to FIG. 3A, it can be seen that the amount of leakage current changes according to a voltage applied to a word line serving as a gate of a parasitic field transistor.

Referring to FIG. 3B, it can be seen that the amount of leakage current increases as the voltage applied to the triple P well serving as the source of the parasitic field transistor increases.

Here, since the high voltage is applied to only 16 word lines when the erase operation is performed in units of blocks, only 16 parasitic field transistors are formed. However, when the erase operation is performed by the chip erase method, since the high voltage is applied to all word lines, the number of parasitic field transistors is incomparably increased (thousands of times). Therefore, the amount of leakage current also increases rapidly, and thus the erase operation is not normally performed, thereby increasing the defective rate generated during the test operation.

In contrast, the semiconductor device and the method of manufacturing the same capable of reducing the leakage current caused by the parasitic field transistor according to the present invention etch the conductive layer formed on the device isolation layer on the upper portion of the N well surrounding the triple P well, and By connecting the conductive layer with a contact plug and a metal wire to block generation of the parasitic field transistor, it is possible to suppress the occurrence of leakage current and to improve the electrical characteristics of the device.

In a semiconductor device according to an embodiment of the present invention, in a semiconductor device including an N well, a triple P well, an isolation layer, and a conductive layer formed on the semiconductor substrate, the triple P well serves as a source, and the N well serves as a channel region. The semiconductor device may further include a device isolation layer formed deeper than the target depth on the N well region of the region where the semiconductor substrate serves as a drain and the conductive layer serves as a gate to form the parasitic field transistor.

A semiconductor device according to another embodiment of the present invention includes an N well formed in an active region of a semiconductor substrate, a triple P well formed in a partial region of the N well, a first device isolation layer formed in an element isolation region of the semiconductor substrate, and a triple P. A second device isolation layer is formed deeper than the first device isolation layer on the N well that vertically surrounds the well.

A semiconductor device according to another embodiment of the present invention includes N wells and triple P wells formed in an active region of a semiconductor substrate divided into a low voltage device region and a high voltage device region, a first device isolation layer formed in the low voltage device region, and a low voltage device. A second device isolation layer is formed deeper than the first device isolation layer in the N well upper portion of the region edge and the high voltage device region.

According to another aspect of the present invention, a method of manufacturing a semiconductor device includes sequentially forming N-we and triple P wells on a semiconductor substrate, and forming a conductive layer on the semiconductor substrate in a predetermined pattern, thereby forming triple P wells. Forming a conductive layer in a disconnected pattern on the upper part of the N well vertically enclosed, forming an interlayer insulating film on the entire structure including the conductive layer, and forming a contact plug and metal wiring to electrically connect the disconnected conductive layer. The step of connecting to.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various other forms, and the scope of the present invention is not limited to the following embodiments. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

4 is a cross-sectional view of a device for describing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4, an N well 402 and a triple P well 403 are formed in a P-type semiconductor substrate 401. Here, the N well 402 is formed first and the triple P well 403 is formed later, where the triple P well 403 is formed inside the N well 402. Thus, the N well 402 wraps around the triple P well 403.

Next, trench type device isolation layers 404 and 404a are formed in the device isolation region, and various elements for forming a semiconductor device are formed on the active region. In this case, a conductive material layer may be formed on the device isolation layers 404 and 404a to electrically connect the devices.

Specifically, for example, in the case of a flash memory device, a tunnel oxide film 405, a floating gate 406, a dielectric film 407, and a word line 408 are formed on an active region. Here, the word line 402 is formed not only on the floating gate 406 but also on the device isolation layer 404a for electrical connection with peripheral cells.

In the semiconductor device having the above structure, the triple P well 403, the N well 402, and the P-type substrate 401 are arranged in parallel under the device isolation layer 404a. The word line 408 is formed on the isolation layer 404a. As a result, the word line 408 serves as a gate, the triple P well 403 serves as a source, the N well 402 serves as a channel region, and the P type substrate 401 serves as a drain. Field transistors are formed. Parasitic field transistors are often formed at the boundary between the low voltage device region and the high voltage device region.

In order to prevent leakage current caused by the parasitic field transistor, the word line 408 formed on the device isolation layer 404 on the N well 402 that vertically surrounds the triple P well 403 is removed. do. As a result, the word line 408 is disconnected and not connected to a peripheral circuit (eg, an X-decoder).

In order to connect them, an interlayer insulating film 409 is formed on the entire structure, and a contact plug 410 is formed at the end of the etched word line 408. Subsequently, when the contact plug 410 is connected to the metal wire 411, the broken word line 408 is normally connected again.

In this case, even if a high voltage is applied to the word line 408 or the triple P well 403, the parasitic field transistor is formed not only on the device isolation film 404a but also on the interlayer insulating film 409 on the N well 402. Not formed.

As described above, the present invention by etching the conductive layer formed on the device isolation layer on the top of the N well surrounding the triple P well, by connecting the disconnected conductive layer with a contact plug and a metal wiring to block the generation of parasitic field transistor Therefore, leakage current can be suppressed and the electrical characteristics of the device can be improved.

In addition, the reliability of the test can be improved by preventing leakage current from increasing during test time of NAND flash memory devices.

Claims (4)

A semiconductor device comprising an N well, a triple P well, an isolation layer, and a conductive layer formed on a semiconductor substrate, The conductive layer in the region where the triple P well serves as a source, the N well serves as a channel region, the semiconductor substrate serves as a drain, and the conductive layer serves as a gate to form a parasitic field transistor is etched. And the disconnected conductive layer is connected to the contact plug through the metal wire. An N well formed in an active region of the semiconductor substrate; A triple P well formed in a portion of the N well; A conductive layer formed on the semiconductor substrate and disconnected from the N well to vertically surround the triple P well; And A semiconductor device comprising a contact plug and a metal wiring for electrically connecting the disconnected conductive layer. N well and triple P wells formed in an active region of a semiconductor substrate divided into a low voltage device region and a high voltage device region; A conductive layer disconnected over the N well at the edge of the low voltage device region; A semiconductor device comprising a contact plug and a metal wiring for electrically connecting the disconnected conductive layer. Sequentially forming N-we and triple P wells on the semiconductor substrate; Forming a conductive layer on the semiconductor substrate in a predetermined pattern, and forming the conductive layer in a disconnected pattern on the N well that vertically surrounds the triple P well; Forming an interlayer insulating film on the entire structure including the conductive layer; And Forming a contact plug and a metal wiring to electrically connect the disconnected conductive layer.

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