KR20090070534A - Flash device and manufacturing method thereof - Google Patents

Abstract

A flash device and a method for manufacturing the same are provided to prevent the resistance in a boundary surface between the metal wiring and the contact plug by forming a plurality of contact plugs directly contacted with a common source line. A semiconductor substrate(400) including a drain select transistor, a plurality of memory cells, a source select transistor, and a common source line is provided. A first interlayer insulating layer is formed on the semiconductor substrate. A contact hole with an upper part wider than a lower part is formed by etching the first interlayer insulating layer formed on the source select transistor. A first contact plug(428) is formed by forming a conductive material in a contact hole. The upper width of the contact plug is wider than the interval between the transistors and is narrower than the width of the outside of the transistors.

Description

Flash device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash device and a method of manufacturing the same, and more particularly, to a flash device and a method of manufacturing the same, which reduce resistance of a common source line to suppress under program generation.

Among the semiconductor devices, flash devices, which have recently been in the spotlight due to the superiority of data storage, portability, and large capacity, are described in detail as follows.

The flash device includes a memory cell array for storing data and an operator for driving the flash device. Among these, the memory cell array will be described below.

1 is a circuit diagram illustrating a memory cell block of a flash device, and FIG. 2 is a graph illustrating a threshold voltage distribution when a conventional under program occurs.

Referring to FIG. 1, a memory cell array of a flash device includes a plurality of memory cell blocks 100, and one of the memory cell blocks 100 is described in detail as follows. The memory cell block 100 includes a plurality of strings strings S1 to Sk. Each of the strings S1 to Sk includes memory cells F0 to Fn arranged in series and a drain select transistor T1 and a source select transistor T0 arranged at both ends of the memory cells F0 to Fn. do. The gate terminal of the drain select transistors T1 included in each of the strings S1 to Sk share the drain select line DSL, and the gate terminal of the source select transistors T0 share the source select line SSL. . In addition, the gate terminals of the memory cells F0 to Fn share the word lines WLL0 to WLn in units of pages. The drain junctions of the drain select transistors T1 are connected to the bit lines BL1 to BLk, respectively, and the source junctions of the source select transistors T0 are common source lines. Commonly connected with (CSL).

Next, the program operation of the flash device will be described. The program operation is performed by repeatedly performing a program and a verify operation. That is, after the program operation is performed, the verifier operation is performed to check whether the program operation is properly performed. In the case of memory cells having a threshold voltage lower than the verifi voltage, the program operation is repeated. The selected cell 110 in which the program operation is performed will be described in more detail as follows.

After performing the program operation on the selected cell 110, the Verify operation is performed. The verify operation is determined as the amount of decrease in the voltage of the bit line BL2 charged with respect to the selected cell 110. Specifically, if electrons are sufficiently applied to the selected cell 110 so that the threshold voltage of the selected cell 110 is included in the program threshold voltage distribution, the threshold voltage is higher than the verifi voltage and thus precharged during the verifi operation. The bit line BL2 voltage is not discharged. On the contrary, if the threshold voltage of the selected cell 110 is not low and the program operation is not completed, the voltage of the bit line BL2 passes through the selected cell 110 and is discharged through the common source line CSL. As described above, the Verify operation detects the threshold voltage level of the memory cell by sensing the voltage level of the bit line.

In this case, since the voltage of the bit line BL2 is discharged through the common source line CSL, the resistance of the common source line CSL should be low. However, as the degree of integration of semiconductor devices has recently increased, the line width of the common source line CSL has decreased. Accordingly, the resistance of the common source line CSL may increase. When the resistance of the common source line CSL increases, it is difficult for the voltage to escape through the common source line CSL, and the program operation is sufficiently performed. Although not (A in FIG. 2), an under program may be determined to determine the selected cell 110 as a cell in which a program is completed.

In addition, noise of a voltage level may be generated due to an increase in resistance of the common source line CSL, thereby making it difficult to control the threshold voltage distribution.

An object of the present invention is to increase the area of the common source line to reduce the resistance of the common source line.

Alternatively, resistance of the interface between the metallization and the contact plug can be prevented by removing a part of the metallization electrically contacting the common source line and forming a plurality of contact plugs that are in direct contact with the common source line.

A flash device according to an embodiment of the present invention includes a semiconductor substrate including transistors. An interlayer insulating film formed on the semiconductor substrate. A contact hole is formed between the transistors, the upper width of which is wider than the lower width. It is made of a flash element including a contact plug formed inside the contact hole.

The contact plug is in contact with the junction region between the transistors, and the upper width of the contact plug is formed to be wider than the gap between the transistors, narrower than the outer width of the transistors, and the lower width of the contact plug is narrower than the gap between the transistors.

A flash device according to another embodiment of the present invention includes a semiconductor substrate including a junction region. A drain select line, a plurality of memory cells and a source select line formed on the semiconductor substrate are included. It is formed between the source select lines and includes a common source line whose upper width is wider than the lower width. It consists of a flash element comprising contact plugs formed on a common source line.

The upper width of the common source line is wider than the spacing of the source select lines and narrower than the outer width of the source select lines.

In the method of forming a flash device according to an embodiment of the present invention, a semiconductor substrate including a drain select transistor, a plurality of memory cells, and a source select transistor is provided. A first interlayer insulating film is formed on the semiconductor substrate. The first interlayer insulating layer formed between the source select transistors is etched to form a contact hole having an upper portion wider than a lower portion. And forming a first contact plug by forming a conductive material in the contact hole.

The forming of the contact hole may include forming a first hard mask pattern having an open first region on the first interlayer insulating layer. An etching process is performed according to the first hard mask pattern to form a trench in the first interlayer insulating layer. The first hard mask pattern is removed. A second hard mask pattern having a second width narrower than the first area is formed on the first interlayer insulating layer having the trench formed therein. An etching process is performed according to the second hard mask pattern to form a contact hole in the first interlayer insulating layer. A method of manufacturing a flash device comprising removing the second hard mask pattern.

The trench is wider than the gap between the transistors, and is formed to be narrower than the width between the outer sides of the transistors, and the contact holes are formed to be narrower than the gap between the source select transistors.

After forming the first contact plug, the method may further include forming a second contact plug on the first contact plug that is not in contact with the first metal wire, which is an intermediate layer.

According to the present invention, since the resistance of the common source line can be reduced by increasing the area of the common source line, it is possible to suppress noise generation and underprogram in the metal wiring during the program operation, thereby improving the reliability of the program operation. have.

In addition, by removing a part of the metal wiring that is in direct contact with the common source line and forming a plurality of contact plugs that are in direct contact with the common source line, it is possible to prevent the occurrence of resistance at the interface between the metal wiring and the contact plug. Since it can be suppressed, the reliability of the program operation of the flash element can be improved.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

3 is a layout diagram illustrating a flash device of the present invention, in particular, a layout diagram showing a part of a memory cell block. This will be described in detail as follows.

In the case of a flash device, word lines WL, drain select line DSL, source select line SSL, and drain contact plug DC are formed on a semiconductor substrate on which an active region 300 and an isolation region 302 are formed. And a common source line CSL. The common source line CSL is formed between the source select line SSL. A manufacturing method that can reduce the resistance of the common source line CSL will be described in detail with reference to the B-B 'direction.

4A to 4F are cross-sectional views illustrating a method of manufacturing a flash device according to the present invention.

Referring to FIG. 4A, a semiconductor substrate 400 including transistors is provided. Referring to the flash device in detail, the source select lines SSL are formed on the semiconductor substrate 400 including the junction region 400a. The source select line SSL may be formed by stacking the gate insulating layer 402, the first conductive layer 404, the dielectric layer 406, the second conductive layer 408, and the metal layer 410. Alternatively, a hard mask pattern (not shown) for the gate patterning process may be further stacked on the metal layer 410. The gate insulating film 402 may be formed of an oxide film, and the first conductive film 404 may be formed of a polysilicon film. The dielectric film 406 may be formed in a stacked structure of an oxide film, a nitride film, and an oxide film, or may be formed of a high dielectric film. In this case, a hole is formed in a portion of the dielectric film 406 so that the first conductive film 404 and the second conductive film 408 may be in contact with each other and electrically connected to each other. The second conductive layer 408 may be formed of a polysilicon layer, and the metal layer may be formed of a tungsten silicide (WSix) layer.

After forming the source select line SSL, a spacer 412 for protecting the source select line SSL is formed on sidewalls of the source select line SSL, and the spacer 412 and the source select line SSL are formed. And a first insulating layer 414 for self-aligned contact in a subsequent contact hole forming process along the surface of the junction region 400a. In this case, the first insulating layer 414 may also be referred to as a self-aligned contact (SAC) insulating layer. Preferably, the spacer 412 and the first insulating layer 414 are formed of materials having different etching selectivity. For example, since the interlayer insulating film is mainly formed of an oxide film, the first insulating film 414 may be formed of a nitride film, and the spacer 412 may be formed of an oxide film. Next, a second insulating film 416 for interlayer insulating film is formed on the first insulating film 414. The second insulating film 416 may be formed of an oxide film.

Referring to FIG. 4B, a first hard mask pattern 418 having a pattern for forming the trench 419 for reducing the resistance of the source select line is formed on the second insulating layer 416. The width W2 of the open area of the first hard mask pattern 418 may be wider than the width W1 of the common source line to be subsequently formed. For example, the width W2 of the open area of the first hard mask pattern 418 may be wider than the gap W1 between the common source lines and narrower than the outer width of the neighboring source select lines SSL. An etching process is performed according to the first hard mask pattern 418 to form the trench 419 in the first insulating layer 416. In this case, the trench 419 may be formed to a depth such that the first insulating film 414 formed on the source select line SSL is not exposed. For example, the trench 419 can be formed to a depth of 200 kPa to 20000 kPa.

Referring to FIG. 4C, a second hard mask pattern in which the first hard mask pattern 418 of FIG. 4B is removed and a region in which a common source line is to be formed is defined on the second insulating layer 416 on which the trench 419 is formed. 420 is formed. Accordingly, the width W1 of the open area of the second hard mask pattern 420 becomes the width of the common source line to be subsequently formed. An etching process is performed according to the second hard mask pattern 420 to form a contact hole 421 in the trench 419 of the second insulating layer 416. The contact hole 421 is preferably formed so that the junction region 400a is exposed, and a part of the upper portion of the junction region 400a may be removed.

Referring to FIG. 4D, after removing the second hard mask pattern 420 of FIG. 4C, a common source line 422 is formed by filling a conductive material in the contact hole (421 of FIG. 4C) and the open area (419 of FIG. 4C). Form. Specifically, the common source line 422 may be formed by filling a conductive material in the contact hole (421 of FIG. 4C) and the open area (419 of FIG. 4C) and performing a chemical mechanical polishing (CMP). have.

As such, while the upper portion 422a of the common source line 422 is electrically isolated from the source select line SSL, an increase in resistance can be suppressed by forming a width overlapping the source select line SSL on the layout. That is, since an increase in the area (or volume) of the common source line 422 can be suppressed to increase the resistance of the common source line 422, noise of voltage can be reduced, and electrical characteristics of the flash memory device can be reduced. Can improve.

In addition, by forming a contact plug electrically connected to the common source line CSL according to a manufacturing method described below, an increase in resistance of the common source line CSL may be further reduced.

Referring to FIG. 4E, a third insulating layer 424 for interlayer insulating layers is formed on the common source line CSL and the second insulating layer 416. The third insulating film 424 may be formed of an oxide film. After the third insulating layer 424 is formed, it is preferable to form the first metal wiring M1, which is an intermediate layer, but not to contact the first contact plug 428 to be subsequently formed. A fourth insulating film 426 for interlayer insulating film is formed on the third insulating film 424. The fourth insulating film 426 may be formed of an oxide film. Subsequently, the fourth insulating layer 426 is formed to form a hard mask pattern (not shown) in which the contact hole 427 region is opened, and to perform an etching process according to the hard mask pattern (not shown) to expose the common source line 422. ) And part of the third insulating film 424 are removed. Subsequently, the first contact plug 428 is formed by filling a conductive material in the contact hole 427 and performing a planarization process (CMP) to expose the fourth insulating film 426. Although not shown in the drawing, instead of forming the first metal wire M1, it is preferable to form a plurality of first contact plugs 428 to replace the role of the first metal wire M1. For example, the first contact plug 428 may be formed per string, but this may increase the size of the flash device, and therefore preferably the first contact plug 428 per two or three screws. To form.

If the first metal wire M1 and the first contact plug 428 contact each other, the resistance may increase due to the interface F between the contact plugs. However, as described above, since the number of interfaces can be reduced by preventing the first metal wiring M1 and the first contact plug 428 from contacting each other, the overall resistance of the common source line 422 can be reduced. All.

Referring to FIG. 4F, a second metal wiring M2 is formed on the first contact plug 428 and the fourth insulating film 426, and the fifth insulating film 430 and the upper portion of the second metal wiring M2 are formed. The second contact plug 432 is formed. In addition, a third metal wiring M3 is formed on the fifth insulating layer 430 and the second contact plug 432.

As described above, by reducing the resistance of the common source line CSL and the region electrically connected thereto, the discharge through the common source line CSL may be improved during the program verify operation. .

Referring to FIG. 5, FIG. 5 is a graph illustrating a change in the threshold voltage according to the present invention. By suppressing an increase in resistance of the common source line CSL, an under program may be suppressed. This can be applied to both a single level ship (SLC) having a single program threshold voltage distribution section and a multi level chip (MLC) having a plurality of program threshold voltage distribution sections. In particular, since the margin between neighboring program threshold voltage distributions is very narrow in a multi-level chip (MLC), electrical reliability can be improved by preventing under program generation.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a circuit diagram illustrating a memory cell block of a flash device.

2 is a graph illustrating a threshold voltage distribution when a conventional under program occurs.

3 is a layout for explaining a flash device of the present invention.

4A to 4F are cross-sectional views illustrating a method of manufacturing a flash device according to the present invention.

5 is a graph for explaining a change in threshold voltage according to the present invention.

<Explanation of symbols for the main parts of the drawings>

400: semiconductor substrate 402: tunnel insulating film

404: First conductive film 406: Dielectric film

408: second conductive film 410: metal film

412 spacer 414 first insulating film

416: Second insulating film 418: First hard mask pattern

420: second hard mask pattern 422: common source line

424: third insulating film 426: fourth insulating film

428: first contact plug 430: fifth insulating film

432: second contact plug M1: first metal wiring

M2: Second Metal Wiring M3: Third Metal Wiring

Claims (11)

A semiconductor substrate including transistors; An interlayer insulating film formed on the semiconductor substrate; A contact hole having an upper width greater than a lower width between the transistors; And And a contact plug formed in the contact hole. The method of claim 1, And the contact plug is in contact with a junction region between the transistors. The method of claim 1, And the upper width of the contact plug is wider than a gap between the transistors and narrower than an outer width of the transistors. The method of claim 1, And a lower width of the contact plug is smaller than a gap between the transistors. A semiconductor substrate including a junction region; A drain select line, a plurality of memory cells, and a source select line formed on the semiconductor substrate; A common source line formed between the source select lines and having an upper width wider than a lower width; And And a contact plug formed on the common source line. The method of claim 5, wherein And the upper width of the common source line is wider than an interval of the source select lines and narrower than an outer width of the source select lines. Providing a semiconductor substrate including a drain select transistor, a plurality of memory cells and a source select transistor; Forming a first interlayer insulating film on the semiconductor substrate; Etching the first interlayer insulating layer formed between the source select transistors to form a contact hole having an upper portion wider than a lower portion thereof; And And forming a first contact plug by forming a conductive material in the contact hole. The method of claim 7, wherein forming the contact hole, Forming a first hard mask pattern having a first region open on the first interlayer insulating layer; Forming a trench in the first interlayer insulating layer by performing an etching process according to the first hard mask pattern; Removing the first hard mask pattern; Forming a second hard mask pattern on the first interlayer insulating layer having the trench formed therein, the second region having a narrower width than the first region being opened; Forming a contact hole in the first interlayer insulating layer by performing an etching process according to the second hard mask pattern; And And removing the second hard mask pattern. The method of claim 8, And forming the trench in a width wider than a gap between the transistors and narrower than a width between the outer sides of the transistors. The method of claim 8, And forming the contact hole in a width narrower than an interval between the source select transistors. The method of claim 7, wherein And after forming the first contact plug, forming a second contact plug on the first contact plug that is not in contact with the first metal wiring, which is an intermediate layer.

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