JPH01114076A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01114076A JPH01114076A JP27222287A JP27222287A JPH01114076A JP H01114076 A JPH01114076 A JP H01114076A JP 27222287 A JP27222287 A JP 27222287A JP 27222287 A JP27222287 A JP 27222287A JP H01114076 A JPH01114076 A JP H01114076A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- base
- region
- resistor
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 238000000206 photolithography Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000008188 pellet Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に外部受動素子を内蔵し
た接合トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a junction transistor incorporating an external passive element.
一般にトランジスタを用いてインバータ回路あるいはド
ライバー回路を形成する場合、電流制御用としてベース
、エミッタ端子間に並列に抵抗が挿入される。通常、抵
抗はトランジスタとは独立した外付は抵抗として回路基
板上で構成されている。最近では、第７図に示すように
１チツプ内にトランジスタとポリシリコン高抵抗等を同
時に形成し、電極配線により構成されているものがある
。Generally, when forming an inverter circuit or a driver circuit using transistors, a resistor is inserted in parallel between the base and emitter terminals for current control. Usually, a resistor is configured on a circuit board as an external resistor independent of a transistor. Recently, as shown in FIG. 7, there is a device in which a transistor, a polysilicon high resistance, etc. are simultaneously formed in one chip, and the chip is constructed with electrode wiring.
上述した従来技術では第７図に示すように配線された金
属電極層６がトランジスタ素子領域外の薄膜抵抗５と結
線されるので、半導体基板表面に露出しているコレクタ
、ベース接合の一部およびコレクタ領域の一部を絶縁膜
を介して電極が横断する構造となる。このため、コレク
タ、ベース間道バイアス時のＰＮ接合の信頼性が等電位
電極環を有するトランジスタに比べて劣る問題があった
。In the prior art described above, the wired metal electrode layer 6 is connected to the thin film resistor 5 outside the transistor element area as shown in FIG. The structure is such that an electrode crosses a part of the collector region with an insulating film interposed therebetween. For this reason, there is a problem in that the reliability of the PN junction when biasing between the collector and the base is inferior to that of a transistor having an equipotential electrode ring.
本発明の半導体装置は半導体基板内にエミッタ、づ−ス
、コレクタ領域が形成されている接合トランジスタにお
いて、エミッタ領域はベース領域内に形成され、エミッ
タとベースとの間に接続される抵抗はベース領域上に絶
縁膜を介して設けられている。The semiconductor device of the present invention is a junction transistor in which an emitter, a source, and a collector region are formed in a semiconductor substrate, and the emitter region is formed in a base region, and the resistor connected between the emitter and the base is It is provided on the region with an insulating film interposed therebetween.
本発明はエミッタ、ベース間抵抗を絶縁膜をはさんで素
子内部に形成しているため、エミッタ、ベース接合の信
頼性が向上する効果があり、さらにペレット小型化によ
る低コスト化に有利となる。In the present invention, the resistance between the emitter and the base is formed inside the element with an insulating film in between, which has the effect of improving the reliability of the emitter-base junction, and is also advantageous in reducing costs by downsizing the pellet. .
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図、第２図はその平
面図、第３図はその等価回路図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is an equivalent circuit diagram thereof.
Ｐ型半導体基板１上にフォトリソグラフィ技術およびブ
レーナ技術を用いてＮ型ベース領域２． Ｐ型エミッタ
領域３を選択的に形成し、ＰＮＰ型接合トランジスタを
形成する。次に、抵抗形成時に拡散領域へ影響を与えな
いためにフォトリソグラフィ技術により選択的に前記ト
ランジスタ上に絶縁膜４，４′を形成、さらにイオン注
入法等によりポリシリコン高抵抗領域５を選択的にエミ
ッタ領域３とベース領域２にまたがるように形成し、こ
の領域５の両端のうち一方はエミッタ電極、他方はベー
ス電極に接するように選択的に金属電極６を形成する。An N-type base region 2. is formed on a P-type semiconductor substrate 1 using photolithography technology and Brainer technology. A P-type emitter region 3 is selectively formed to form a PNP-type junction transistor. Next, insulating films 4 and 4' are selectively formed on the transistors using photolithography technology in order not to affect the diffusion region during resistor formation, and the polysilicon high resistance region 5 is selectively formed using ion implantation or the like. A metal electrode 6 is selectively formed so as to span the emitter region 3 and the base region 2, and the metal electrode 6 is selectively formed so that one of both ends of the region 5 is in contact with the emitter electrode and the other end is in contact with the base electrode.
第４図は本発明の他の実施例の縦断面図である。FIG. 4 is a longitudinal sectional view of another embodiment of the invention.
第５図は本実施例のペレット平面図、第６図は本実施例
の等価回路である。この実施例では、一実施例に更に、
ベース領域２と外部への取出し電極の間に一実施例と同
様の方法によりポリシリコン抵抗５を素子上に選択的に
形成したものである。FIG. 5 is a plan view of the pellet of this embodiment, and FIG. 6 is an equivalent circuit of this embodiment. In this embodiment, one embodiment further includes:
A polysilicon resistor 5 is selectively formed on the element between the base region 2 and the electrode taken out to the outside by the same method as in the first embodiment.
本発明はトランジスタの素子上に抵抗パターンを形成し
ているため電極がエミッタ、ベース間のＰＮ接合の横断
を無くすことができるので、エミッタ、ベース接合の信
頼性が向上する効果がある。Since the present invention forms a resistance pattern on the transistor element, it is possible to eliminate the need for the electrode to cross the PN junction between the emitter and the base, which has the effect of improving the reliability of the emitter and base junction.
更に素子上に抵抗形成しているため、素子内部を有効に
活用できペレット小型化等による低コスト化に有利とな
る。Furthermore, since a resistor is formed on the element, the inside of the element can be effectively utilized, which is advantageous in reducing costs by making the pellet smaller.
第１図は本発明の一実施例の抵抗内蔵型トランジスタの
縦断面図、第２図は本発明の一実施例のトランジスタの
平面図、第３図は本発明の一実施例の等価回路図、第４
図は本発明の他の実施例の半導体装置の縦断面図、第５
図は本発明の他の実施例の半導体装置の平面図、第６図
は本発明の他の実施例の等価回路図、第７図は従来の抵
抗内蔵型トランジスタの平面図である。
１・・・・・・Ｐ型半導体基板、２・・・・・・Ｎ型ベ
ース領域、３・・・・・・Ｐ型エミッタ領域、４，４′
・・・・・・絶縁膜、５・・・・・・ポリシリ高抵抗、
６・・・・・・金属電極。
代理人 弁理士 内 原 音
第 ２ 図
Ｅ
、箔 ３ フ
／／ダグへ−ス種りに
第７靭
に）
窟５図FIG. 1 is a longitudinal cross-sectional view of a transistor with a built-in resistor according to an embodiment of the present invention, FIG. 2 is a plan view of a transistor according to an embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of an embodiment of the present invention. , 4th
FIG. 5 is a vertical cross-sectional view of a semiconductor device according to another embodiment of the present invention.
6 is a plan view of a semiconductor device according to another embodiment of the present invention, FIG. 6 is an equivalent circuit diagram of another embodiment of the present invention, and FIG. 7 is a plan view of a conventional transistor with a built-in resistor. 1... P-type semiconductor substrate, 2... N-type base region, 3... P-type emitter region, 4, 4'
...Insulating film, 5...Polysilicon high resistance,
6...Metal electrode. Agent Patent Attorney Uchihara Sound No. 2 E, Haku 3 F//Dagges Seinori No. 7) Cave No. 5
Claims (1)
成されている接合トランジスタにおいて、前記エミッタ
領域は前記ベース領域内に形成され、前記エミッタと前
記ベースとの間に接続される抵抗は前記ベース領域上に
絶縁膜を介して設けられていることを特徴とする半導体
装置。In a junction transistor in which an emitter, a base, and a collector region are formed in a semiconductor substrate, the emitter region is formed in the base region, and a resistor connected between the emitter and the base is formed on the base region. A semiconductor device characterized in that it is provided with an insulating film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27222287A JPH01114076A (en) | 1987-10-27 | 1987-10-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27222287A JPH01114076A (en) | 1987-10-27 | 1987-10-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01114076A true JPH01114076A (en) | 1989-05-02 |
Family
ID=17510816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27222287A Pending JPH01114076A (en) | 1987-10-27 | 1987-10-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01114076A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56144580A (en) * | 1980-04-10 | 1981-11-10 | Mitsubishi Electric Corp | Semiconductor device |
-
1987
- 1987-10-27 JP JP27222287A patent/JPH01114076A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56144580A (en) * | 1980-04-10 | 1981-11-10 | Mitsubishi Electric Corp | Semiconductor device |
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