JPH0499369A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize with a processing margin higher integration and speed and to further shorten a delivery term by composing a memory cell of a Schottky diode formed on a polycrystalline silicon and a contact formed on the diode. CONSTITUTION:In a cell section formed in a matrix state if a conductor layer 103 is merely connected to a wiring layer 110 in an opening 109, cells are short- circuited therebetween. In order to avoid it, a polycrystalline silicon layer is provided under the opening, a Schottky diode 107 made of high melting point metal silicide is formed on the surface to form a junction, and it is avoided by the rectification thereof. In this case, an insulating film 104 is formed between the layer 103 and a polycrystalline silicon layer 106 to improve workability. The film 104 is interposed thereby to stop etching, the layers 106, 107 and 103 can be separately etched, and the layers 103 and 110 can be brought into direct contact with one another.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvement of the structure of a semiconductor device 6. [Prior Art] A semiconductor device, particularly a read-only memory, has been conventionally used as shown in FIG. 2(a). Each cell is composed of one transistor, and ROM data is written by changing the threshold voltage of this transistor by ion implantation.

FIG. 2(b) is a cross-sectional view of this, in which 201 is a semiconductor substrate, 202 is a gate film, 203 is a gate electrode, 204 is a high concentration diffusion layer, 205 is a low concentration diffusion layer of an LDD structure, and 206 is an LDD structure. Structure sidewall insulation film, 207
2 is an interlayer insulating film, and 208 is an AL wiring. ROM here
Data writing has been performed by forming an impurity layer 209 by ion implantation before or after forming the interlayer insulating film 207 and changing the threshold voltage. Also, Figure 2 (C
) is a plan view, where a is a unit portion of a cell, and 210 is an element isolation region.

[Problems to be Solved by the Invention] As miniaturization and high integration progress, one contact part (in Fig. 2(b), the gate electrode 3, Al2O2, and diffusion layer 204) was required, and the problem that it was not possible to reduce the size much, and the problem that the on-resistance of the transistor itself could not be lowered, making it impossible to increase the speed became apparent.

The object of the present invention is to solve this problem and provide a structure that can realize downsizing and speeding up.

[Means for Solving the Problems] A semiconductor device of the present invention includes: a first insulating film formed on a semiconductor substrate; a first insulating film containing impurities of a first conductivity type formed on the first insulating film; a conductive layer, a second insulating film formed on the first conductive layer, a first opening formed in a predetermined portion of the second insulating film on the first conductive layer, and a second insulating film formed on the first conductive layer; a second conductor layer made of polycrystalline silicon containing impurities of a first conductivity type, which is in direct contact with the first conductor layer through the first opening; and a third insulator formed on the second conductor layer. a second opening formed in a predetermined portion of the third insulating film other than above the opening; a high melting point formed on the second conductor layer within the second opening; A semiconductor device comprising a Schottky diode made of metal silicide and a third conductor layer mainly composed of AL formed over the second opening.

Embodiment 1 FIGS. 1(a), 1(b), and 1(c) are a plan view and a sectional view showing the circuit system and structure of a semiconductor device according to an embodiment of the present invention.

In FIGS. 1(b) and 1(c), 101 is a semiconductor substrate;
102 is an element isolation insulating film; 103 is a conductor layer made of the same material as the gate electrode and containing impurities of the first conductivity type; polycide, 104 a first interlayer insulating film, 105 a first opening,
106 is a polycrystalline Zinocon layer containing a first conductivity type, that is, an N-type impurity, 108 is a second interlayer insulating film, 109 is a second opening formed on the first opening 105, and 107 is the second A Schottky diode made of refractory pentavalent metal silicide is formed on the polycrystalline silicon layer 106 in the opening 109. 110 is a wiring layer such as AL. Also the first
In Figure (b), 1 and 2 are one cell unit portion.

As shown in FIGS. 1(b) and 1(c), one cell unit is based on one contact opening 109, and whether or not to open a contact is determined using data on the mask during the processing process. That is, this is a method of making a read-only memory by determining data by electrically sensing whether or not the wiring 110 and the conductor layer 103 are electrically connected.

At this time, the conductor layer 103 and the wiring layer 110 are simply connected to the opening 1.
If the cells are connected only by 09, short circuits will occur between the cells in the cell part formed in a matrix.To avoid this, a polycrystalline silicon layer is provided under the opening, and the surface thereof is coated with high melting point metal silicide. A junction is formed by forming a Schottky diode 107 consisting of a Schottky diode 107 to avoid this rectifying effect. A circuit diagram of this structure is shown in FIG. 1(a). Also, at this time, the conductor layer 103
By forming an insulating film 104 between the polycrystalline silicon layer 106 and the polycrystalline silicon layer 106, processing efficiency was also improved. That is, when the conductor layer 103 and the polycrystalline silicon layer 106 are in contact with each other over the entire surface, they do not need to be etched continuously, and
When it is desired to directly connect the wiring layer 110 such as L and the conductor layer 103, the polycrystalline silicon layer 106 must be interposed, resulting in problems such as contact resistance. - By interposing the periphery film 104, this can stop the etching, and the polycrystalline silicon layer 106, 107 and the conductor layer 103 can be etched separately, and the conductor layer 103 and the wiring layer +10 can be directly contacted. was completed.

Further, the first opening 105 is not provided above the second opening,
In other words, by providing the conductor layer 103 in separate parts, even if the N-type impurity in the conductor layer 103 diffuses into the polycrystalline silicon layer 106 above during heat treatment in a post-process, it will not directly collide with the Schottky diode region @107. Stable properties can also be obtained.

By this method, a memory cell as shown in FIG. 1(b) could be realized and downsizing could be achieved.

Furthermore, although there is a P-N junction, the device functions through electrical continuity between the conductor layer 103 and the wiring layer 110 without using a transistor, so the resistance is lower than the ON resistance of a transistor, and high speed can be achieved. Furthermore, since data is written with or without the contact, that is, the opening 107, the time from data writing to completion, that is, the manufacturing delivery time, can be shortened.

[Effects of the Invention 1] As described above, according to the present invention, memory cells of read-only memory, which conventionally consisted of memory cells made of transistors, can be replaced by a Schottky diode formed on polycrystalline silicon and this diode formed on the Schottky diode. Memory cells were constructed using contacts, and this could be achieved with sufficient processing margins, resulting in high integration, high speed, and short delivery times.

[Brief explanation of drawings]

FIGS. 1(a) to (c) are explanatory diagrams of the present invention, and FIG. 1(a)
1 is a circuit diagram, FIG. 1(b) is a plan view, and FIG. 1(c) is a sectional view. Figures 2(a) to (c) are explanatory diagrams of the conventional structure.
2(a) is a circuit diagram, FIG. 2(b) is a plan view, and FIG. 2(c) is a sectional view. 101.201 Semiconductor substrate 102.210...Element isolation insulating film 103.203...Glue electrode containing N-type impurity and its wiring layer 104...・First interlayer insulating film 105...
. . . First opening 106 . . . Polycrystalline silicon layer 107 containing N-type impurities . . . High melting, φ metal silicide 202
・ ・ 206 ・ ・ ・ 209 ・ 211 ・ Schottky diode second interlayer insulating film, second opening AL, etc. wiring layer gate insulating film, high concentration impurity layer, low concentration impurity layer, side Wall, interlayer insulating film, impurity layer for data writing, contact and above

Claims (1)

[Claims] a first insulating film formed on a semiconductor substrate; a first conductive layer containing impurities of a first conductivity type formed on the first insulating film; and a first conductive layer formed on the first conductive layer. a second insulating film, a first opening formed in a predetermined portion of the second insulating film on the first conductor layer, the first opening being in direct contact with the first conductor layer; a second conductive layer made of polycrystalline silicon containing impurities of a first conductivity type; a third insulating film formed on the second conductive layer; a first opening in a predetermined portion of the third insulating film; a second opening formed in a portion other than above the section, a Schottky diode made of high melting point metal silicide formed on a second conductor layer in the second gate, and above the second opening. 1. A semiconductor device comprising a third conductor layer formed as a main component of Al.