JPH02163962A - Mos-type memory integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a gate insulating film from being destroyed by a charge-up at an ion implantation operation and to enhance a yield by a method wherein an impurity concentration of a source region and a drain region of a MOSFET constituting a memory cell is made lower than that of other MOSFET's. CONSTITUTION:In a MOS-type memory integrated circuit device which contains a MOSFET constituting a memory cell and the other MOSFET, an impurity concentration of a source region and a drain region 5, 7 of the MOSFET constituting the memory cell is made lower than that of a source region and a drain region 10, 12 of the other FET. For example, a source region and a drain region 5, 7 of a MOSFET in a memory cell part of a MOS-type DRAM are formed by an ion implantation operation at a dose of 2 to 5X10<13>/cm<2> by using phosphorus is impurities; a source region and a drain region 10, 12 of a MOSFET constituting a peripheral circuit are formed by the ion implantation operation at a dose of 10<15> to 10<16>/cm<2> by using arsenic as impurities; impurity concentrations are set at 4 to 10X10<18>/cm<2> and 10<20>/cm<2> or higher, respectively.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a MOS type memory integrated circuit device, and in particular, to a MOS type field effect transistor (hereinafter referred to as MOSFET) constituting a memory cell. The present invention relates to a MOS type memory integrated circuit in which the impurity concentration is different from that of the source/drain regions of other MOSFETs.

[Prior Art] The structure of a conventional MOSFET of this type is shown in FIGS. 8(a) and 8(b), taking the case of a DRAM as an example.
) shows the transistor structure of the memory cell portion, and FIG. 8(b) shows the transistor structure of the peripheral circuit portion. In these transistors, source and drain regions 50.70 are provided in the p-silicon semiconductor substrate 1 on both sides of the gate electrode 6.11.
and 10.11 are formed, and an interlayer insulation 1!116 is deposited on the semiconductor substrate 1, and a contact hole 8 formed in the insulation film is formed on the insulation film. source region 50 or source, drain region 1
An aluminum wiring 9 is formed in contact with 0.12. In addition, in the memory cell part, a capacitor diffusion layer 2,
A capacitor composed of a capacitor insulating film 3 and a capacitor electrode 4 is formed, and the capacitor diffusion layer 2 is connected to a MOSFET train 70 in the memory cell section.
is connected to. The gate electrode 6 of the memory cell transistor extends perpendicularly to the plane of the paper and functions as a word line, and the aluminum wiring 9 led out from the source region 5 of this transistor functions as a digit line. Although not shown here, the source/drain regions are usually formed to have a so-called LDD structure. In conventional memory integrated circuit devices,
The source and drain regions of the MOSFET of the memory cell are
It was formed in the same process and with the same impurity concentration as the source and drain regions of the MOSFET in the peripheral circuit portion.

[Problems to be Solved by the Invention] In highly integrated memory integrated circuit devices, source/drain regions are generally formed by ion implantation. 100 keV, 1015~1.016/co! This is formed by ion implantation at a dose of . At this time, since the gate electrode is in a floating state, charge-up occurs in the portion of the gate electrode into which ions are implanted, and as a result, there is a possibility that the gate insulating film may be destroyed. especially,
Breakdown of the gate insulating film in gate electrodes with large areas, such as word electrodes of memory cells, is noticeable, and the yield of memory integrated circuit devices has been significantly reduced due to the occurrence of defects in these areas.

[Means for Solving the Problems] The MOS type memory integrated circuit device of the present invention comprises a MOS type memory integrated circuit device forming a memory cell formed on a p-silicon semiconductor substrate.
The impurity concentration in the source/drain regions of the FET is lower than the impurity concentration in the source/drain regions of the MOSFET, which is another integrated circuit component.

[Example] Next, an example of the present invention will be described with reference to the drawings.

1A and 1B are cross-sectional views showing a first embodiment of the present invention, in which FIG. The memory cell part of a MOS type DRAM with one transistor memory cell layout is shown in Figure 1 (
b) shows a portion of an n-type MOSFET that constitutes a peripheral circuit.

In these figures, the same parts as those in the conventional example shown in FIGS. 8(a) and 8(b) are given the same reference numerals, so redundant explanation will be omitted. The source and drain regions 5.7 in (a) are different in impurity concentration from the source and drain regions 10.12 in FIG. The latter is formed by ion implantation with a dose of Q''/crA, and the latter is formed by ion implantation with a dose of 1015 to 101'/crd using arsenic as an impurity, and the impurity concentration is 4~l OX 10”/aA, 10”/c
It has been done more than nf.

Therefore, the layer resistance of the n-type diffusion layer is higher in the former and lower in the latter, but in the case of memory cell transistors, the current handled is small, and in addition, the cells are miniaturized. Therefore, the distance between the end of the source/drain region and the contact with the aluminum wiring 9 or the distance between the capacitor diffusion layer 2 and the end of the source/drain region is short, so even if the parasitic resistance of the source/drain region becomes large, special problems will not occur. On the other hand, transistors in peripheral circuits often handle large currents, such as when charging large-capacity digit lines, and the resistance value of their source and drain regions must be high enough to supply large currents at high speed. has been made low. Since this transistor is doped with a large amount of impurities, there is an undeniable risk that the gate insulating film will be destroyed, but the number of elements formed in the peripheral circuit section is originally smaller than that in the memory cell section. Because there are very few
The effect on yield due to breakdown of the gate insulating film in this portion is negligible.

Next, a second embodiment of the present invention will be described with reference to FIG. 2(d) and FIG. 3(d).

FIG. 2(d) shows the memory cell portion and FIG. 3(d)
) is a sectional view showing the transistor structure of the peripheral circuit portion. In the peripheral circuit portion, the transistors have an LDD structure as shown in FIG. 3(d). The source/drain regions 5.7 of the transistor in the memory cell portion are formed to have the same impurity concentration as the n- diffusion layer in the LDD structure.

Next, FIGS. 2(a) to (C) and 3(a) to (C)
), the method for manufacturing the integrated circuit device of the second embodiment will be described.

Figures 2 (a) to (c) show the manufacturing process of the part shown in Figure 2 ((f)), and Figures 3 (a) to (C) show the manufacturing process of the part shown in Figure 3 (d). It is a diagram showing the order.

First, as shown in FIG. 2(a), n"
A diffusion layer is formed to serve as a capacitor diffusion layer 2, and further,
forming a capacitor insulating film 3 and a capacitor electrode 4;
Next, as shown in FIGS. 2(a) and 3(a), the gate electrode 6 of the memory cell transistor and the gate electrode 11 of the peripheral circuit transistor are formed.
b) and as shown in Figure 3(b), 2 to 5× phosphorus
Ion implantation was performed at a dose of IQ+3/aIl to simultaneously form the source and drain regions 5.7 and the n- diffusion layer 13. Subsequently, as shown in FIG. 2(c) and FIG. 3(c), an oxide film sidewall 14 is formed on the side surface of the gate ring i6.11, and then an n-type film as shown in FIG. 3(c) is formed. Accelerating arsenic only in the MOSFET section with energy of 100
At keV, 5 x 1015 ~ I x 10 I6/ad
Ions are implanted at a dose of
A drain region 10.12 was formed. At this time, the memory cell portion shown in FIG. 2(C) is covered with a mask material to prohibit doping.

Finally, after depositing the glabella insulating film 16 and forming the contact hole 8 therein, an aluminum wiring 9 is formed and the second
Obtain the apparatus of the second embodiment shown in FIG. 3(d) and FIG. 3(d).

In this embodiment, it is structurally unnecessary to form a highly doped 01 diffusion layer in the memory cell transistor shown in FIG. Breakdown of the insulating film can be avoided. Furthermore, by designing the impurity concentration of the source/drain regions of the memory cell portion to be low, the effective parasitic channel length of the element isolation region can be increased, which is advantageous for miniaturization of the element isolation region. Furthermore, concentration of electric field in the drain region of the gate electrode edge can be prevented.
The characteristics of the transistor can be maintained in good condition for a long period of time.

FIG. 4 is a sectional view showing a third embodiment of the present invention. This embodiment relates to a DRAM using a trench type capacitor, in which a p-silicon semiconductor substrate l has a conductive layer 18 formed thereon, a capacitor diffusion layer 2 which is an n+ diffusion layer, and a capacitor insulating layer 18. 83, a capacitor consisting of the capacitor electrode 4 is formed. The source region 5 and drain region 7 of the MOSFET used here are formed by ion-implanting phosphorus at a dose of 1Q13 to 1014/-, and are
The impurity concentration is 2 compared to the source/drain region of SFET.
The drain region 7, which is one length and is three orders of magnitude lower, has a structure in which it overlaps with the n+ diffusion layer which is the capacitor diffusion layer.

FIG. 5 is a sectional view showing a fourth embodiment of the present invention,
In this embodiment, the capacitor diffusion layer 2, which was an n+ diffusion layer in the embodiment of FIG. 4, is formed in the same process as the source/drain region 5.7 to have the same impurity concentration.

These impurity regions are formed by ion-implanting arsenic at a dose of 1 (approximately +14 to 10<15>/cut) immediately after forming the groove 18.

FIG. 6 is a sectional view showing a fifth embodiment of the present invention,
In this embodiment, the source region 5 of the memory cell transistor is formed by doping the contact pole 8 with n-type impurities. The impurity concentration was approximately 1019/-, and the layer was doped with phosphorus. On the other hand, the drain region 7 is formed at the same time as the capacitor diffusion layer 2, and has a physical structure, as in the example shown in FIG.

FIG. 7 is a sectional view showing a sixth embodiment of the present invention,
In this embodiment, the gate ring f of the memory cell transistor is
i6 is formed in a structure overlapping with the capacitor electrode 4 forming the cell capacitance. Therefore, the drain region is formed in common with the capacitor diffusion layer 2. In addition, the source region 5 contains phosphorus at a dose of 1013 to 1014/7.
It is formed by ion implantation. Furthermore, in this embodiment, silicide wiring 9a is used instead of aluminum wiring 9. According to this embodiment, even if the junction depth of the source region is formed to be shallow,
Aluminum alloy spikes do not cause short circuits.

In the embodiments shown in FIGS. 4 to 7, the MOSFET of the peripheral circuit was not shown, but the source and drain regions of this transistor are shown in FIG. 1(b).
It is assumed that they are normally formed as shown in FIGS. 3(d) to 3(d).

Furthermore, it is assumed that the source region 5 with a low impurity concentration is additionally doped with an impurity by an appropriate means in order to improve ohmic properties in the contact portion.

As an example, the present invention has been applied to a dynamic RAM, but the present invention is not limited thereto. It is similarly applicable to any device that includes a memory cell region as part of an integrated circuit device.

C. Effects of the Invention] As explained above, one aspect of the present invention is to improve the MOS of the memory cell part.
Since the impurity concentration of the source/drain region of the FET is lower than that of the source/drain region of the MOSFET constituting the peripheral circuit, according to the present invention, the source/drain region of the MOSFET in the memory cell section There is no need to ion-implant a large amount of impurities to form. Therefore, breakdown of the gate insulating film due to charge-up during ion implantation can be prevented, and the yield of the memory integrated circuit device can be improved.

Furthermore, the depth of the junction of the source/drain diffusion layer of the MOSFET in the memory cell can be designed to be shallow, and the width of the element isolation region can be made narrower. Therefore, according to the present invention, further miniaturization of the memory integrated circuit device is possible.

Further, by lowering the impurity concentration in the source/drain regions, electric field concentration at the gate edge portion can be alleviated, and the long-term reliability of the MOSFET constituting the memory cell can be improved.

Source region, in region, RAM wiring, large region, 1 in region, wall, 6... gate electrode, 7... drain 8... contact hole, 9... aluminum 10... peripheral circuit Transistor points...gate electrode, 12...drain 13...n-diffusion layer, 14...side 16...
...Interlayer insulating film, 18...groove.

Claims (1)

[Claims] In a MOS type memory integrated circuit device including a MOS type field effect transistor constituting a memory cell and another MOS type field effect transistor, the impurity concentration of the source/drain region of the transistor constituting the memory cell is equal to that of the source of the other transistor. - A MOS type memory integrated circuit device characterized in that the drain region is lower than that of the drain region.