JPS6294975A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent soft errors in D/RAM, and obtain a semiconductor memory device of high reliability, by constituting the source.drain of a memory cell transistor with a first conduction type layer whose impurity density is less than or equal to the first conduction type impurity layer, and providing a second conduction type layer under a capacitor electrode. CONSTITUTION:A gate oxide film is formed in the forming region of memory cell transister and peripheral circuit transister, and a polysilicon layer 2 is deposited. After patterning, a gate electrode is formed. A source.drain 5 of the peripheral circuit transistor and a source.drain 6a of the memory cell transistor are simultaneously formed by self-alignment and ion implantation. The density of N<-> layer 6a being said source.drain is about 10<18>cm<-3> which is less than or equal to an N<-> layer 7. Then the depth of source.drain 6a is restrained in the same range as the N<-> layer 7, and a P<-> layer 8 to prevent soft errors is not erased. When the conduction region of cell transistor is formed in a shallows depth of the N<-> layer, the exudation to a part of the P<-> layer 8 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and is particularly used in a dynamic random access memory (referred to as D/RAM).

[Technical background of the invention and its problems]

The conventional technology for this food is shown in Figure 3. Here, the memory cell is a 1-transistor/1-capacitor type memory, where 1 is a P-type substrate, 2 is a polysilicon layer, 3 is a conductive wiring path, 4 is an insulating film, and 5 is a peripheral circuit transistor. A conductive region (source, drain), 6 is a conductive region (source, drain) of a transistor of a memory cell, 7 is a capacitor part conductive region, 8 is a lower conductive region of the capacitor part, and 9 is a polysilicon layer for the capacitor.

FIG. 4 is a partially enlarged view of FIG. 3, and FIG. 5 is an electrical equivalent circuit thereof, in which IZ is a transistor, 12 is a capacitor for storing information, 13 is a word line, and 14 is a bit line.

By the way, in the conventional I)/RAM, the conductive region 5 of the peripheral circuit transistor and the conductive region 6 of the transistor of the memory cell have a high concentration of conductivity type opposite to that of the substrate 1, that is, 10 c.
An impurity layer of m or more is used. Further, the capacitor has a layer 7 of a conductivity type opposite to that of the substrate I as a conductive region, and has an impurity layer 8 of the same conductivity type as the substrate 1 below. Further, in the prior art, as shown in layers 5 and 6, a high concentration impurity layer (referred to as N+) is used for both the memory cell and the peripheral circuit. Therefore, as shown in Fig. 4, the seepage part (part 10 in Fig. 4) where the N+ layer seeps out in the capacitor part causes a layer of the same conductivity type as the substrate (
(referred to as P-) 8 is erased, and the entire capacitor part is P-.
8 can no longer be covered. As a result, P8, whose purpose is to prevent soft errors caused by alpha rays, does not partially lose its potential barrier effect against electrons.
This results in the induction of soft errors.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and the present invention has been made in view of the above circumstances.
The present invention aims to prevent soft errors in AM and provide a highly reliable semiconductor memory device.

[Summary of the invention]

In the present invention, the source and drain (first conductivity type) of a transistor of a memory cell are formed of a first conductivity type layer having a lower concentration or equivalent to the first conductivity type impurity layer which is the capacitor electrode, and the capacitor electrode A second conductivity type layer is provided below to prevent soft errors. A peripheral circuit of a memory uses a transistor formed of a first conductivity type layer (source, drain) having the same concentration as the memory cell.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
3 and 2 are cross-sectional views of the same embodiment, but since these are examples in correspondence with FIGS. 3 and 4, the same reference numerals are used for corresponding parts. First, an active region is formed on a P-type substrate I, and then an insulating film for a capacitor portion is formed. Mask with photoresist, and apply N only to the capacitor part and part of the peripheral circuit.
Ion implantation is performed for the first layer 7 and the first P layer 8. After that, a polysilicon layer 9, which is the electric component of the capacitor, is deposited.
Patterning through. An oxide insulating film is formed on polysilicon layer 9 to electrically insulate it from the transistor of the memory cell.

Next, a gate oxide film is formed in the memory cell transistor and peripheral circuit transistor forming regions, and then a polysilicon layer 2 is deposited and patterned to form a gate electrode. Next, by self-alignment, the source and drain 5 of the peripheral circuit transistor and the source and drain 6a of the memory cell transistor are simultaneously formed by ion implantation. The concentration of the N''' layer 6a, which is the source and drain, is on the order of 1018z-3, which is thinner than or equivalent to the N layer 7.Then, the depth of the source and drain 6a is suppressed to be equal to that of the N layer 7.
The P layer 8 for soft error prevention will not be erased.

In the above peripheral circuit transistor, the problem that the N layer 5 has a high resistance can be solved by lowering the resistance using means such as selective deposition of tungsten or the like.
(ad drain), and junction breakdown in the contact portion can be prevented by diffusing impurities from the contact portion.

The advantages of the above embodiment are as follows. When a transistor with a concentration of 10 cm or more is used in a memory cell, the N+ layer 6 protrudes below the polysilicon layer 9 as shown in FIG. Despite the formation, the area of P layer 8 is reduced. If the conductive regions (source, drain) of the cell transistor are shallowly formed with a single layer of N (1018 cm-3) as shown in FIG. It has the effect of forming a higher potential for electrons that cause soft errors. Furthermore, when a transistor is constructed using a single layer of low concentration N, it is also possible to prevent the generation of hot electrons that cause reliability deterioration due to the relaxation of the electric field near the drain.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a semiconductor memory device that prevents soft errors and has high reliability.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an embodiment of the present invention, FIG. 2 is a partially enlarged view thereof, FIG. 3 is a cross-sectional view of a conventional bright RAM, FIG. 4 is a partially enlarged view thereof, and FIG. is an electrical equivalent circuit diagram of the memory cell. 1... P-type substrate, 2... polysilicon layer, 3...
Conductive wiring path, 5... Peripheral circuit conductive region, 6... Memory cell conductive region, 7... Capacitor portion conductive region, 8
. . . Lower conductive region of capacitor portion, 9. ...Polysilicon layer for capacitors. -1 concave Fig. 2

Claims (3)

[Claims] (1) A semiconductor memory device comprising a transistor and a capacitor formed on one main surface of a semiconductor substrate, wherein the capacitor includes a conductive layer and a conductivity type opposite to that of the substrate (a conductivity type disposed under the conductive layer). 1 conductivity type) and an insulating film between the conductive layer and the first impurity layer; The second conductivity type
By using the impurity layer of
1. A semiconductor memory device having a depth that does not erase an impurity layer. (2) The semiconductor memory device according to claim 1, wherein the impurity layer formed simultaneously with the second impurity layer is used for a source and a drain of a peripheral transistor. (3) The concentration of the second impurity layer is 10^1^8 cm^
-^3 The semiconductor memory device according to claim 1, wherein the number of semiconductor memory devices is three.