JP2000077538A - Cmos semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the concentration of an embedded channel for adjusting to an arbitrary turning-on voltage and suppress the off-leak current by using a non-doped polysilicon as a gate electrode for a p-channel transistor. SOLUTION: A gate electrode 4 is formed on an active region 2 with a gate insulation film 3 in between, forming an n-channel transistor nch-Tr and a p-channel transistor pch-Tr. A polysilicon, comprising a gate electrode 4a on the n-channel transistor nch-Tr, is an N+-type polysilicon added with an n-type impurity and is conductive. A polysilicon, comprising a gate electrode 4b on the p-channel transistor pch-Tr, is a non-doped polysilicon to which no impurity is doped. Thus, while the off-leak current is suppressed, the turning-on voltage can be reduced. Furthermore, the channel can be made small in width, and the element be made fine in size.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor (Field Effect transistor) having a gate electrode made of silicon.
Transistor (hereinafter FET), more specifically,
P-channel MOS (Metal Oxide Semi
conductor) a so-called C having an FET and an n-channel MOSFET
The present invention relates to reduction and miniaturization of an off-leak current below a gate electrode of a MOS semiconductor device.

[0002]

2. Description of the Related Art FIG. 10 shows a conventional typical CMOS semiconductor device. Such a CMOS semiconductor device is used for various logic circuits, SRAMs, and the like. An n-well is formed on a part (the right half in the figure) of the semiconductor substrate 51, and a p-well is formed on the other part (the left half thereof). An active region 52 is formed on a part of each of the n-well and the p-well.
A gate electrode 54 is formed on the active region 52 with a gate insulating film 53 therebetween, forming an n-channel transistor nch-Tr and a p-channel transistor pch-Tr. The gate electrode 54 is doped with an n-type impurity of about 1E20 cm ^-3 to be conductive. Gate electrode 5 of active region 52
4 is formed in a region where conductivity is opposite to that of the well, that is, a p-type impurity such as boron,
Source and drain regions 55 to which n-type impurities such as phosphorus are added are formed in the wells.

When the gate electrode 54 is grounded, the channel region 56 below the gate electrode is completely depleted and non-conductive, so that no current flows even when a voltage is applied between the source and drain regions 55. When a voltage is applied to the gate electrode 54, the channel region 56 becomes conductive.
At this time, when a voltage is applied between the source and the drain, a channel current flows through the channel region 56. For a p-channel transistor and an n-channel transistor, the gate electrode 5
The difference between the positive and negative voltages applied to the transistor 4 makes the transistor 4 conductive, and CMOS is a semiconductor device that utilizes this fact. The threshold value of the gate voltage at which the channel region below the gate electrode becomes conductive is called an on-voltage.

[0004] When polysilicon doped with n-type impurities (hereinafter referred to as N ⁺ poly) and a substrate doped with p-type impurities are brought into contact via a gate insulating film, a difference in work function causes Electrons try to move to N ⁺ poly. For this reason,
A p-channel transistor using N ⁺ poly as a gate electrode
Even if the gate voltage is 0 V, the state is as if a weak positive voltage was applied.To turn on the transistor, a voltage must be applied after canceling the voltage, and a further voltage must be applied. Was rising. Also,
Problems such as a difference in the absolute value of the ON voltage between the p-channel transistor and the n-channel transistor have occurred.

In order to reduce the ON voltage of the p-channel transistor, a region called a buried channel 57 may be formed in the channel region 56 in some cases. The buried channel is a region to which impurities of the same conductivity type as the source and drain regions are added, and the on-voltage can be reduced by increasing the amount of impurities added thereto. FIG. 3 shows the dependency of the on-voltage on the amount of buried channels by a solid line. According to this, for example, 5.0 × 10 ¹² cm
^It can be seen that the ON voltage can be reduced to 0.3 V if the doping amount is ^-2 .

On the other hand, as shown in FIG. 11, it has been proposed to make the impurity added to the gate electrode 54 different for the n-channel transistor and the p-channel transistor. That is, N ⁺ poly is used for the gate electrode 54a located above the n-channel transistor as before, and the gate electrode 54b located above the p-channel transistor is doped with polysilicon (P ⁺ Poly)
Is used. With this configuration, since the conductivity type of the gate electrode 54 and the channel region 56 immediately below the gate electrode 54 are the same, there is no difference in work function between the gate electrode and the channel region, and the ON voltage is set to a predetermined value. Can be.

[0007]

When the gate voltage is 0 V, the channel current is ideally 0 A.
In ET, a minute current flows even if the gate voltage is 0V. Such a current is called an off-leak current.

The buried channel 57 has a channel region 5
8 is doped with impurities of the same conductivity type as the source and drain regions 55, so that an increase in the amount of implantation increases an off-leak current. The off-leakage current is on the order of pA (picoamps), but with the recent reduction in on-voltage and miniaturization of elements, it causes malfunctions in logic circuits and errors in reading of storage elements, and cannot be ignored. I have. In addition, off-leak current is caused by unnecessary current,
The battery of a portable device incorporating such an element is wasted, the operating time is shortened, and this is a problem.

When boron is implanted into a polysilicon film to form P ⁺ poly of the gate electrode 54b of a CMOS p-channel transistor, the boron penetrates through the gate electrode 54 because of its large diffusion coefficient in silicon. And reaches the semiconductor substrate 51. Boron is the semiconductor substrate 5
When implanted into 1, the concentration of the buried channel 57 increases, the breakdown voltage between the source and drain regions 55 decreases, and there arises a problem that the off-leak current increases. Further, since the concentration of boron remaining in the gate electrode 54b also varies,
The on-voltage of the p-channel transistor varies. In addition, boron diffuses laterally,
When the diffusion reaches the gate electrode 54a of the n-channel transistor, the on-voltage of the n-channel transistor also varies.

In order to reduce the leakage current, it is necessary to reduce the concentration of the buried channel.
The on-voltage of the channel transistor cannot be sufficiently reduced, the on-voltage of the p-channel transistor has a small difference from the voltage applied to the gate electrode, and the channel current of the p-channel transistor is smaller than that of the n-channel transistor. Become smaller. Therefore, as shown in FIG.
the gate width GW _p of the p-channel transistor by taking larger than the gate width GW _n of the n-channel transistors so as to ensure the current value of the same level as the n-channel transistor. This has led to an increase in the area of the device.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has been made to reduce the concentration of a buried channel for adjusting to a desired on-voltage by using non-doped polysilicon as a gate electrode of a p-channel transistor. This is a CMOS semiconductor device in which the off-leak current is reduced by reducing the depth of the buried channel.

The MOSFET generally uses the gate electrode 54 as a wiring. For this reason, the electric resistance of the gate electrode 54 greatly affects the operation of the device, and many efforts have been made to reduce the resistance of the gate electrode 54. In the conventional gate electrode 54, polysilicon is doped with an impurity to reduce the electric resistance. The gate electrode 54 employs a polycide structure using tungsten silicide or the like, and succeeds in further reducing the electric resistance of the gate electrode 54. Here, the present applicant has concluded that the factor determining the electrical resistance of the gate electrode 54 employing the polycide structure is mainly tungsten silicide, and does not depend much on the amount of impurities doped into polysilicon. I found it. That is, if the gate electrode 54 having the polycide structure is employed, it can be said that it is not always necessary to dope the polysilicon of the gate electrode with an impurity.

[0013]

Embodiments of the present invention will be described below. FIG. 1 shows a CMOS according to the present invention. An n-well is formed on a part (the right half in the figure) of the semiconductor substrate 1 and a p-well is formed on the other part (the left half of the figure). Active region 2 is formed on a part of each of the n-well and the p-well. A gate electrode 4 is formed on active region 2 with a gate insulating film 3 interposed therebetween, and n-channel transistors nch-Tr and p-channel transistors
A channel transistor pch-Tr is formed. The gate electrode 4 has a polycide structure which is a multilayer structure of polysilicon and tungsten silicide. The polysilicon of the gate electrode 4a on the upper part of the n-channel transistor nch-Tr is N ⁺ poly doped with an n-type impurity of about 1E20 cm ⁻³ and is conductive. The polysilicon of the gate electrode 4b above the p-channel transistor pch-Tr is non-doped polysilicon to which no impurity is added.
In the region of the active region 2 where the gate electrode 4 is not formed, an impurity of a conductivity type opposite to that of the well, that is, a p-type impurity such as boron is added to the n-well, and an n-type impurity such as phosphorus is added to the p-well. Source and drain regions 5 are formed. A buried channel region 7 is formed in the channel region 6 below the gate electrode 4.

The p-channel transistor will be described below.

FIG. 2 shows a MOSFET of this embodiment and a conventional MOSF.
4 shows the gate length GL dependence of off-leak current of ET. The gate length GL is the distance between the source and drain regions 6 below the gate electrode 4, in other words, the length of the channel region 6 in the direction of the source and drain regions. In this embodiment and in the conventional case, the thickness of the polysilicon film is 1010 °. ○ indicates conventional MOSFET, △
And ▲ are MOSFETs of the present invention. The ON voltages are 0.61 V for ○, 0.67 V for △, and 0.49 V for ▲. The on-voltage can be adjusted by changing the concentration of the buried channel. The phenomenon in which the off-leak current increases as the gate length becomes shorter is a phenomenon generally called a short channel effect. First, compare ○ and ▲
The MOSFET of the present invention has substantially the same off-leakage current value even though the on-voltage is about 0.1 V lower. Next, comparing O and Δ, the MOSFET according to the present invention has an off-leak current value that is nearly two orders of magnitude smaller only by an ON voltage of about 0.06 V higher. As described above, in the MOSFET of the present invention, the off-leak current can be suppressed to be smaller than that of the conventional MOSFET at the same ON voltage. Next, FIG. 3 shows the ON-voltage dependency of the off-leak current. In both the present invention and the related art, when the on-state voltage is set low, the off-leak current increases. However, the MOSFET of the present invention has an off-leak current value which is one digit smaller than that of the conventional MOSFET.

Next, FIG. 4 shows the dependency of the on-voltage on the concentration of the buried channel 8. The decrease in the on-voltage with the increase in the concentration of the buried channel 8 is the same in both the conventional MOSFET and the MOSFET of the present invention. However, for example,
The concentration of the buried channel 8 at 0.35V is 3.0 × 10
¹² cm ^-2 , which is 60% of the concentration required for a conventional MOSFET.
%. The MOSFET of the present invention can be set to the same ON voltage as that of the conventional MOSFET with less impurity implantation than the conventional MOSFET.

It is considered that the reason why the off-leak current of the MOSFET of the present invention is smaller than the conventional one is that the concentration of the buried channel is low and the depth at which the buried channel is formed is small. Since the buried channel and the source and drain regions are regions to which impurities of the same conductivity type are added, they are basically conductive,
Due to the low concentration of the buried channel, the electrical resistance is only relatively high. Therefore, as the concentration of the buried channel increases, the off-leak current increases. Also, as the concentration increases, the depth at which the buried channel is formed also increases, thereby lowering the electric resistance of the buried channel region. Therefore, as the concentration of the buried channel increases, the off-leak current increases. MOSFET of the present invention
Can achieve the same on-voltage with a buried channel concentration lower than that of the conventional MOSFET. Therefore, if the on-voltage is the same as that of the conventional MOSFET, the off-leakage current can be suppressed to 1/10 or less.

Next, the thickness of the non-doped polysilicon film 3 will be described. In this embodiment, the thickness of the non-doped polysilicon film 3 is 1010 °, 285 °, and 247 °. Hereinafter, the sample having a thickness of 1010 ° of the polysilicon film 3 is referred to as Sample 1, the sample having a thickness of 285 ° is referred to as Sample 2, and the sample having a thickness of 247 ° is referred to as Sample 3.

FIG. 5 shows that the thickness of the doped polysilicon film 53 is 10 10 Å
Is the gate voltage dependence of the channel current of a conventional MOSFET (hereinafter referred to as a conventional sample). The channel current of the present embodiment is
Samples 1 to 3 are slightly smaller, but not to a practically problematic degree. Samples 2 and 3 have larger channel current values than Sample 1, and it can be said that Sample 2 and Sample 3 are better from the channel current value.

FIG. 6 shows the characteristics of the MOSFET according to the prior art and the present embodiment when the ON voltage is set to about 0.65 V. The first stage is sample 1, the second stage is sample 2, the third stage is sample 3, and FIG.
The fourth row shows the characteristics of the conventional sample. The off-leakage current is 6.40 pA for the conventional MOSFET, which is 0.05 pA to 0.09 pA under each condition, which is about two orders of magnitude smaller, indicating that the off-leakage current is sufficiently suppressed. β is the slope of the channel current value with respect to the gate voltage, and is a value indicating the driving capability of the FET. β is sample 2,
3 shows almost the same value as the conventional one, but sample 1 is slightly lower. This is because the inside of the non-doped silicon film is depleted, and the thicker the film thickness, the thicker the depletion region.

FIG. 7 shows the dependence of the ON voltage on the gate length. The horizontal axis represents the effective channel length, and the vertical axis represents the on-state voltage standardized by the gate length of 2 μm. The effective channel length is a channel length resulting from diffusion of impurities in the source and drain regions. ● and ○ are conventional MOSFETs, ▲ and △ are
MOSFET. The MOSFET of the present invention is 0.05μ
by about m. The phenomenon that the ON voltage decreases as the gate length decreases is the short channel effect.
In the SFET, it can be said that the occurrence of the short channel effect is improved by 0.05 μm. In other words, miniaturization is possible compared to the conventional MOSFET.

FIG. 8 is a comparison of the reduction in the on-state voltage with respect to the gate lengths of the samples 1, 2, and 3. Samples 2 and 3 having a smaller film thickness have a smaller decrease in on-state voltage than Sample 1. This is because, when the polysilicon layer 3 is formed, the thicker layer requires more time for deposition and is kept at a high temperature during that time, so that impurities in the buried channel diffuse and the buried channel becomes deeper. It is.

FIG. 9 shows the gate breakdown voltage. This is a leakage current from the gate electrode when a voltage is applied to the gate electrode. Samples 1, 2, and 3 show almost the same values. At Vg <8 V, the leakage current is larger than that of the conventional sample, but this does not pose a practical problem as a current value. In addition, the measurement results when the film thickness of non-doped polysilicon is 193 ° are also shown. Looking at this, a leakage current of about 1 nA flows at Vg = 1 V, which is not usable. Further, CV characteristics cannot be obtained at this film thickness. Therefore, the thickness of the non-doped polysilicon film 3 needs to be at least 193 ° or more.

From the above data, it is found that the thickness of the non-doped polysilicon is 1010 ° or less, and the thinner the better, from the viewpoint of the driving ability and the suppression of the short channel effect. Does not fulfill
It can be said that the suitable film thickness of non-doped polysilicon is 193 ° to 1010 °.

As described above, when the gate electrode of the p-channel transistor is made of non-doped polysilicon having an appropriate thickness, the leak current can be reduced and the on-voltage can be reduced.

When the on-state voltage is reduced, the difference between the voltage applied to the gate electrode and the on-state voltage increases, so that a sufficient amount of current for the p-channel transistor can be secured. In conventional CMOS, only the p-channel transistor has a gate width GW to secure the current amount of the p-channel transistor.
_{Although p} was increased, this became unnecessary and the gate width GW
Can be reduced to have the same width as the n-channel transistor. In addition, since the current amount of the p-channel transistor is secured, the voltage applied to the gate electrode can be reduced, so that the power supply voltage can be reduced.

Next, an n-channel transistor will be described. The use of non-doped polysilicon for the gate electrode can of course be carried out with an n-channel transistor. However, in the case of an n-channel transistor, when it is made non-doped, the difference in work function from the substrate is reduced, and the short-channel effect is remarkably exhibited, so that it is not effective. Therefore, the non-doping of the gate electrode is applied only to the p-channel transistor, and the gate electrode of the n-channel transistor is N ⁺ poly.

By the way, in CMOS, in order to make only the gate electrode of a p-channel transistor non-doped,
It is necessary to separate a non-doped region and an N ⁺ region between a channel transistor and an n-channel transistor. However, phosphorus or arsenic implanted into the N ⁺ region may diffuse into the non-doped region due to a heat treatment step in the manufacturing process of the device. Therefore, it is preferable that the boundary between the non-doped region and the N ⁺ region is not at the center of the p-channel transistor and the n-channel transistor but is shifted toward the n-channel transistor.

The term "non-doped" in the present specification means that active impurities are not added. For example, a small amount of impurities diffuse from other diffusion layers and the like, resulting in a small amount of impurities. Even if an impurity is added to the polysilicon film or an unexpected impurity is mixed during the formation, it is assumed to be in the category of “non-doping”.

Since amorphous silicon generally has a smaller impurity diffusion than polysilicon, the non-doped polysilicon film may be a non-doped amorphous silicon film. Therefore, the silicon film described in the claims includes a polysilicon film, an amorphous silicon film, and the like.

Although tungsten silicide has been described as an example of the polycide structure, the polycide structure may be made of various metals such as molybdenum and titanium. In addition to the polycide structure, it is sufficient if the electrical resistance of the gate electrode can be sufficiently reduced after the silicon layer of the gate electrode is non-doped.

In addition, the present invention can be variously applied without departing from the spirit described in the claims.

[0033]

As described above, in the CMOS semiconductor device of the present invention, since the gate electrode of the p-channel transistor is a non-doped silicon film, the on-state voltage can be reduced while suppressing the off-leak current.

Further, since the ON voltage is reduced, the channel current when a predetermined power supply voltage is applied increases, and the channel width, which was conventionally increased to secure the channel current, can be reduced. Can be

Further, since the ON voltage is reduced, the power supply voltage can also be reduced. Therefore, the operating time of the portable device incorporating the power supply can be extended, and the power supply voltage can be reduced. The number of batteries can be reduced, and the size of a portable device can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing gate length dependence of off-leak current.

FIG. 3 is a diagram showing the dependency of the ON voltage on the impurity concentration of a buried channel.

FIG. 4 is a diagram showing gate voltage dependence of a channel current.

FIG. 5 is a diagram showing the on-voltage dependence of off-leakage current.

FIG. 6 is a table showing characteristics of the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a diagram showing the effective channel length dependence of the ON voltage.

FIG. 8 is a diagram showing the gate length dependency of the ON voltage.

FIG. 9 is a diagram showing gate voltage dependence of a gate leak current.

FIG. 10 is a diagram of a conventional semiconductor device.

FIG. 11 is a diagram of a conventional semiconductor device.

Claims (5)

[Claims] 1. A p-channel MOS transistor having a gate electrode having at least a silicon film and an n-channel MOS transistor
A CMOS semiconductor device comprising: a transistor; and at least the silicon film forming the gate electrode of the p-channel MOS transistor is non-doped silicon. 2. A p-channel MOS transistor and an n-channel MOS having a gate electrode having at least a silicon film.
In the CMOS semiconductor device having a transistor, the silicon film forming the gate electrode of the p-channel MOS transistor is non-doped silicon, and the silicon film forming the gate electrode of the n-channel MOS transistor is doped with n-type impurities. A CMOS semiconductor device, characterized in that it is made of silicon. 3. The CMOS semiconductor device according to claim 1, wherein said gate electrode has a polycide structure of a silicon film and a refractory metal. 4. The method according to claim 1, wherein the thickness of the silicon film is 193 ° or more.
CMOS semiconductor device. 5. The method according to claim 1, wherein the thickness of the silicon film is 1010 ° or less.
CMOS semiconductor device.