JPH1154630A - Semiconductor and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure breakdown strength of an oxide by injecting gate impurities to a MOS transistor depositing a gate electrode material at a low voltage element part to form a source.drain electrode and injecting the gate impurities at a high voltage element part only after formation of the source.drain electrode. SOLUTION: A region for forming the gate electrode 7 of an insulated gate field-effect transistor being driven at a constant voltage is implanted with impurities having a high diffusion coefficient after depositing a gate electrode material and gate impurities of MOSFET having a low diffusion coefficient after forming source.drain regions 12, 13. A region for forming the gate electrode 6 of a MOSFET being driven at a high voltage is implanted only with gate impurities having a low diffusion coefficient or a low solid solubility after forming the source.drain regions 12, 13. Since a depletion layer is formed easily on the gate insulation film 3 side when a bias is applied to a gate electrode on the high voltage driving circuit side, the field being applied to the gate insulation film 3 can be relaxed by the voltage drop in the depletion layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MO in which an internal circuit has a low power supply voltage in order to reduce power consumption, while a high power supply voltage is mixed as an input / output circuit or the like.
S (Metal-Oxide-Semiconductor)
or) a semiconductor device having a structure and a method of manufacturing the same.
In particular, the present invention relates to a method of separately forming circuits for easily improving a device without reducing the reliability and yield of a gate oxide film due to different power supply voltages.

[0002]

2. Description of the Related Art Integrated circuits using complementary semiconductor devices such as CMOS have been miniaturized even today even when the minimum processing line width of 0.25 μm has been achieved. With a reduction in the gate length of a MOS transistor, reduction in power supply voltage based on a scaling law has been attempted in response to requests for element breakdown voltage, element deterioration, and reduction in power consumption. In general, the power consumption of a MOS transistor is approximately proportional to the square of the power supply voltage. Therefore, it is very effective to lower the power supply voltage in order to reduce the power consumption and prevent an increase in the heat generation per unit area due to miniaturization. It is.

However, in reality, it has not been possible to reduce the power supply voltage of all LSIs.
It is rare that the entire LSI is composed only of OS transistors. Usually, it is necessary to take measures such as increasing the power supply voltage only for the input / output section or using high voltage specifications for some circuits for high-speed operation. There are many.

Here, a conventional method for manufacturing a MOS LSI will be described in detail with reference to a CMOS integrated circuit as an example.

First, the steps up to FIG. 9 will be described.
Hereinafter, for convenience, only the NMOS region will be described, but the creation of the PMOS region is performed in the same manner.

First, a silicon substrate that has been cleaned is prepared. As the silicon substrate, either an n-type or a p-type can be used. Here, an n-type silicon substrate is used as an example. Next, a region (p-well) in which p-type impurities are diffused, which is a region necessary for forming an n-channel MOSFET, is formed on the substrate. Then
An oxide film made of silicon oxide is formed thereon, and for example, L
Element isolation is performed by the OCOS method. Then, after a gate oxide film made of silicon oxide is formed on the entire surface of the element formation region by, for example, thermal oxidation, a layer made of, for example, polysilicon is formed on the entire surface. In addition, as a gate electrode material, it is also preferable to have a double structure of a polysilicon film and a silicide film of a high melting point metal.

Next, as shown in FIG. 10, after a resist film is formed on the entire surface, an ion implantation region is opened, and phosphorus ions are implanted as impurities. Then, after ion implantation,
Heat treatment by lamp annealing is performed, and as shown in FIG. 11, the polysilicon and the oxide film are removed by photoetching to form a gate electrode. Thereafter, as shown in FIG. 12, arsenic ions are implanted and annealed to form source / drain electrode (n +) layers on both sides of the gate electrode, and at the same time, lower the resistance of the gate electrode layer.

Next, as shown in FIG. 13, after removing the resist, a sidewall made of, for example, silicon oxide is formed by anisotropic etching. Again, FIG.
As shown in (1), a resist film is formed on the entire surface, an ion implantation region is opened, and arsenic ions are implanted as impurities. Then, heat treatment is performed by lamp annealing or the like to form a silicide, a contact, and a wiring.

[0009]

According to the above-mentioned conventional method, electrodes having the same thickness are formed in all the element portions in the same chip, but a high voltage circuit and a low voltage circuit are mixed. If the high power supply voltage shared with the input / output circuit is directly connected to the low power supply voltage specification MOS transistor, the reliability of the low power supply voltage specification MOS transistor is seriously affected due to the thin gate oxide film. May be exerted.

As a measure for this, conventionally, a method of making the thickness of the gate insulating film of the entire LSI thicker than that of the low voltage portion in accordance with an input / output circuit of a high power supply voltage specification and the like has been attempted. As a method of increasing the thickness of the oxide film only in the high voltage portion, a method of implanting nitrogen only in a region where a thin oxide film is formed before oxidation of the silicon substrate to reduce the oxidation rate, or a method of thinning after once performing oxidation. There is known a method of removing the oxide film only in a region where the oxide film is to be formed and then performing the second oxidation.

However, of the methods for increasing the thickness of the oxide film only in the high voltage portion, the method using nitrogen implantation has a problem such as a decrease in current driving capability due to the influence of nitrogen. There are problems such as deterioration of oxide film quality and reduction of yield due to particles.

On the other hand, Japanese Patent Laid-Open No. 9-74141 discloses that
A semiconductor device, wherein when the gate electrodes of the high-voltage drive circuit and the low-voltage drive circuit are made conductive, the concentration of the introduced impurities is set lower on the high-voltage drive circuit side than on the low-voltage drive circuit; and The manufacturing method is described. As a method of setting the introduced impurity concentration lower on the high voltage drive circuit side than on the low voltage drive circuit, for example,
After arsenic is implanted into the NMOS gate electrode of the low-voltage drive circuit, boron, which is the opposite conductivity type, is then introduced.

However, a substantial amount of boron is required to make the N ⁺ conductive state N ⁻ conductive state by boron ion implantation. In addition, arsenic has a low activation rate and a low diffusion constant. Therefore, when a small amount of boron having a large diffusion constant is implanted, depletion becomes very unstable and the variation in threshold voltage becomes very large.

In order to solve these problems, the present invention relates to a semiconductor device having a field effect transistor driven at a low voltage and a high voltage, and an electric field driven at a low voltage into which a plurality of impurities having different diffusion constants are implanted. A semiconductor having a MOSFET region 1 of an effect transistor and a MOSFET region 2 of a field effect transistor driven at a high voltage into which an impurity having a small diffusion constant or a low solid solubility among impurities implanted in the MOSFET region 1 is implanted. It is an object to provide an apparatus and a method for manufacturing the same.

[0015]

According to a method of manufacturing a semiconductor device of the present invention, a gate impurity of a MOS transistor is injected into a low voltage element portion after depositing a gate electrode material and, for example, after forming source / drain electrodes. The high-voltage operating element is implanted only after the formation of the source / drain electrodes, for example.

More specifically, the present invention provides 1) an insulated gate field effect transistor (MOSFE) driven at a low voltage.
In the region to be a gate electrode of T), an impurity having a large diffusion coefficient is implanted after depositing a gate electrode material and a gate impurity of a MOSFET having a small diffusion coefficient is formed, for example, after forming a source / drain region. In a region to be a gate electrode of a MOSFET to be formed, only a gate impurity having a low diffusion coefficient or a low solid solubility is implanted, for example, after forming source / drain electrodes.

According to the present invention, when a bias is applied to the gate electrode on the high voltage drive circuit side,
A depletion layer is easily formed on the side of the gate insulating film, and an electric field applied to the gate insulating film is reduced due to a voltage drop in the depletion layer. For this reason, the effective gate electric field applied to the electrode on the high voltage drive circuit side is lower on the gate insulating film side than before, and the thickness of the gate oxide film on the high voltage drive circuit side is reduced. Even if the thickness is almost the same as the film thickness, the withstand voltage of the oxide film can be ensured.

Further, since a high-voltage operation transistor can be formed on the same chip only by selecting a gate impurity implantation region, an integrated circuit corresponding to a multi-voltage can be manufactured without increasing the cost and the yield due to an increase in the number of steps. Can be formed.

Hereinafter, the present invention will be described in detail.

In the semiconductor device of the present invention, the internal circuit is set at a low power supply voltage in order to reduce power consumption, while, for example, an MO having a high power supply voltage mixed as an input / output circuit is used.
It has an S structure.

According to the semiconductor device of the present invention, the high-voltage driving circuit and the low-voltage driving circuit are arranged separately on the circuit pattern, and the gap between the high-voltage driving circuit side gate electrode and the low-voltage side gate electrode is increased. Are preferably connected by a metal wiring material such as aluminum which does not move impurities. This is because it is possible to prevent impurities introduced into the gate electrode from diffusing from the low voltage circuit side to the high voltage side due to thermal history and the like in the subsequent steps. Further, each gate electrode may be formed of a layer made of polysilicon,
It is also possible to adopt a two-layer structure in which a lower polysilicon film and an upper refractory metal silicide film are used.

The semiconductor device of the present invention has a field-effect transistor driven at a low voltage and a field-effect transistor driven at a high voltage, and is driven at a low voltage into which a plurality of impurities having different diffusion constants are implanted. (A three-terminal element having a gate, a source, and a drain, and a gate part as a central element has a MOS structure of metal / oxide film / semiconductor), and the MOSFET area. 1 has a MOSFET region of a field effect transistor driven at a high voltage into which an impurity having a small diffusion constant or a low solid solubility is implanted.

The impurities include nitrogen as a donor,
Group V elements such as phosphorus, arsenic, and antimony, and examples of acceptors include group III elements such as boron, aluminum, gallium, arsenic, and indium.

When considering the diffusion of impurities into a substrate, it is generally necessary to consider physical parameters such as the mechanism of diffusion, the solid solubility of impurity atoms in the substrate, and the diffusion coefficient of impurity atoms in the substrate. It is. Here, the solid solubility is a function representing the solubility of impurities in a certain solid, and depends on the temperature. The impurity concentration on the surface of a certain solid is determined by the solid solubility limit of the impurity element in the substrate material (the upper limit of the solubility in the solid at a certain temperature) if the impurity source is sufficient. Boron and the like have a relatively low solid solubility compared to arsenic and phosphorus. When the diffusion constant is D, D is J = −D · dN /, where J is the flow of the impurity when the thermal diffusion phenomenon of the impurity introduced into a certain substance is represented by a mathematical formula.
dx (where N represents the impurity concentration and x represents the depth of the diffused impurity from the surface). Generally, boron and phosphorus have a larger diffusion constant than arsenic and indium.

Further, the semiconductor device according to the present invention has one I
A structure in which an NMOS and a PMOS are combined in a C chip (CMOS: Complementary MOS) can be used. For example, it has an input / output circuit that is a high-voltage drive circuit and an internal circuit that is a low-voltage circuit, each of which has an n-channel MOSFET and a p-channel MOSFET.
T.

The present invention also relates to a method of manufacturing a semiconductor device having a first insulated gate field effect transistor driven at a low voltage and a second insulated gate field effect transistor driven at a high voltage. Forming a layer made of amorphous or polycrystalline silicon on the active region via a gate insulating film; and forming a layer of the amorphous or polycrystalline silicon on the first insulated gate field effect transistor. A first impurity introducing step of introducing an impurity of the same conductivity type as the channel and having a large diffusion constant into a region to be a gate electrode; and a step of introducing a plurality of the plurality of impurities into the gate electrodes of the first and second insulated gate field effect transistors. And a second impurity introduction step of introducing an impurity having a small diffusion constant or a low solid solubility among the impurities.

More preferably, after the first impurity introduction step, the layer made of amorphous or polycrystalline silicon is patterned to drive the first field effect transistor driven at a low voltage and the first field effect transistor driven at a high voltage. Forming a gate electrode of the second insulated gate field effect transistor, and simultaneously forming source and drain regions of the first and second insulated field effect transistors in the second impurity introducing step It is a manufacturing method of.

Specifically, the impurity in the first impurity introducing step is phosphorus, the impurity in the second impurity introducing step is arsenic, the impurity in the first impurity introducing step is boron, and the second impurity is boron. The impurity in the impurity introducing step is preferably indium. further,
The impurity in the first and second impurity introducing steps may be boron. In this case, the impurity concentration in the second impurity introducing step is set to be lower than the impurity concentration in the first impurity introducing step.

The first impurity is an ion of an element having a relatively large diffusion constant and / or solid solubility and activation rate. Phosphorus, which is an n-type impurity in the NMOS transistor region, and ions in the PMOS transistor region. Boron, which is a p-type impurity, is preferably implanted.

The second impurity has a diffusion constant and.
Alternatively, arsenic, which is an n-type impurity, is implanted into the NMOS transistor region, and indium, which is a p-type impurity, is preferably implanted into the NMOS transistor region. In this case, when impurities are introduced into the high-voltage driving circuit side and the low-voltage driving circuit side, the impurities are introduced into the semiconductor substrate at the same time, so that the source region and the drain region can be formed in a self-aligned manner. The process can be simplified.

The manufacturing method of the present invention is suitable for manufacturing a complementary semiconductor device such as a so-called CMOS.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a manufacturing method according to the present invention will be described below in detail with reference to the drawings.

The present embodiment is an example of manufacturing a semiconductor device including an internal circuit including a memory array (not shown), such as a DRAM, and a peripheral circuit including an input / output circuit. The internal circuit of this semiconductor device has, for example, a 3V specification in order to reduce power consumption, while the peripheral circuit has another LS systemized together with this DRAM.
In connection with I, a 5-V power supply specification is used and a 2-power supply configuration is adopted. And each circuit is a p-channel MOSFET
(PMOS) and an n-channel MOSFET.

In the following description, for the sake of convenience, only the PMOS regions of the high voltage driving element section and the low voltage driving element section are shown, but an n-channel MOSFET (NMOS)
In the case of (1), it is necessary to reverse all conductivity types including the active region.

First, as shown in FIG. 1, an element isolation 2 is formed on a silicon substrate by an ordinary method. That is, p
Transistor region and PMO of silicon substrate 1
A deep groove (trench) is provided between the transistor and the S transistor region, and element isolation is formed by the groove. Thereafter, a silicon oxide film 3 is formed by thermal oxidation. The conditions of the thermal oxidation are as follows, for example.

Temperature: 850 ° C. Time: 40 minutes Film thickness: 8 nm Gas: O ₂ Next, after forming a resist film on the entire surface, the resist is opened only in the PMOS region by photolithography, and ion implantation is performed to form a well. Implants phosphorus into the silicon substrate 1. The implantation conditions at this time are, for example, P, 100 Kev, 3E12 cm ⁻² ,
P, 30 Kev, 1E12 cm ^-2 .

Next, after removing the resist and forming a resist film again, the resist is opened only in the NMOS region by photolithography, and boron is implanted into the silicon substrate 1 by ion implantation to form a well. The implantation conditions at this time are, for example, B, 50 KeV,
3E12 cm ^-2 . Further, boron is implanted into the silicon substrate 1 by ion implantation in order to adjust the threshold value of the transistor and suppress the short channel effect. The injection conditions at this time are, for example, B, 50 Kev,
3E12 cm- ² , B, 15 KeV, 1E12 cm- ² .

Next, after removing the resist, the silicon oxide film is removed with a diluted hydrofluoric acid solution, and subsequently, a silicon oxide film is formed to a thickness of, for example, 4 nm by thermal oxidation.

Next, as shown in FIG. 2, polycrystalline silicon 4 is deposited, for example, to a thickness of 200 nm by the CVD method.

Next, as shown in FIG. 3, after a resist film 5 is formed on the entire surface, the resist is opened only in the low-voltage operating element region in the NMOS region by photolithography, and phosphorus is applied, for example, P, 10 Kev, 3E15 cm. Inject ^-2 .

Further, as shown in FIG. 4, the polycrystalline silicon 4 is etched by anisotropic etching to form a gate pattern. The gate length at this time is, for example,
The low voltage operating element section 7 is 0.18 μm, and the high voltage operating element section 6 is 0.23 μm.

Next, as shown in FIG. 5, after a resist film 8 is formed on the entire surface, NMO is performed by photolithography.
A resist is opened only in the S region, and LDD (Lightly
Arsenic is implanted into the silicon substrate 1 by ion implantation to form a doped drain. The implantation conditions at this time are, for example, As, 15 Ke
V, 1E14 cm ^-2 .

Next, as shown in FIG. 6, after removing the resist, a silicon oxide film is deposited to a thickness of, for example, 150 nm by a conventional CVD method, and then the silicon oxide film is deposited to a thickness of 150 nm by anisotropic etching. Etching is performed to form side walls 9 of a silicon oxide film.

Further, as shown in FIG.
1 is formed on the entire surface, and then N is formed by photolithography.
A resist is opened only in the MOS region, and arsenic is implanted into the polycrystalline silicon and the silicon substrate 1 by ion implantation. The injection conditions at this time are, for example,
As, 20 KeV, 3E15 cm ^-2 .

Thereafter, although not particularly shown, for example, at 950.degree.
After performing activation annealing for performing heat treatment for 2 seconds, an interlayer insulating film is formed, and F
Each electrode of the ET is pulled out or connected, and finally, an overcoat film is formed, thereby completing the manufacture of the semiconductor device. FIG. 8 is a schematic cross-sectional view of one whole semiconductor device manufactured in this manner.

In the above description of the manufacturing method, there are no limitations other than those specifically mentioned, and various modifications can be made within the scope of the present invention. For example, the structure of the gate electrode is not limited to LDD, and the film structure may be polycide.

Through the above steps, phosphorus and arsenic are introduced as impurities into the gate of the transistor in the low voltage operation section, and only arsenic is implanted into the gate of the transistor in the high voltage operation section. These impurities are diffused to the interface between the gate oxide film and the polycrystalline silicon and activated by heat treatment such as lamp annealing.

However, when an impurity amount of almost the same concentration is implanted, the diffusion amount of arsenic is smaller than that of phosphorus,
Since the activation rate is low, the activation amount of the gate impurity near the interface between the gate oxide film and the polycrystalline silicon is lower in the gate implanted with arsenic alone. For this reason, when a gate voltage is applied, the extent of the depletion layer near the interface of the gate oxide film increases when only arsenic is implanted.

The depletion layer in polycrystalline silicon 5 lowers the gate voltage applied to silicon substrate 1 and gate oxide film 4 due to the voltage drop in the depletion layer.

Therefore, the effective gate electric field applied to the transistor in the high-voltage operation section is reduced, and the withstand voltage of the oxide film can be ensured even with the same gate oxide film thickness as the transistor in the low-voltage operation section.

[0051]

As described above, according to the present invention,
When a bias is applied to the gate electrode on the high voltage drive circuit side, a depletion layer is easily formed on the gate insulating film side, and an electric field applied to the gate insulating film can be reduced due to a voltage drop in the depletion layer. . For this reason, the effective gate electric field applied to the electrode on the high voltage drive circuit side is reduced, and the thickness of the gate oxide film on the high voltage drive circuit side is almost the same as the thickness of the gate oxide film on the low voltage drive circuit side. Even with this, it is possible to ensure the withstand voltage of the oxide film.

Further, since a high-voltage operation transistor can be formed on the same chip only by selecting an implantation region of a gate impurity, an integrated circuit corresponding to a multi-voltage can be manufactured without increasing the cost and the yield due to an increase in the number of steps. Can be formed.

[Brief description of the drawings]

FIG. 1 is a diagram in which after a device isolation region is formed on a silicon substrate 1, a silicon oxide film 3 is formed by thermal oxidation.

FIG. 2 is a diagram in which a polycrystalline silicon layer 4 is formed after a silicon oxide film 3 is formed.

FIG. 3 is a diagram in which after forming a polycrystalline silicon layer 4 and a resist 5, only a high voltage driving element portion is opened by photoetching and phosphorus ions are implanted.

FIG. 4 is a diagram in which gate electrodes 6 and 7 are formed.

FIG. 5 is a diagram illustrating arsenic ion implantation for forming an LDD.

FIG. 6 is a view in which a sidewall 9 is formed.

FIG. 7 is a diagram illustrating ion implantation of arsenic on a polycrystalline silicon layer and a silicon substrate.

FIG. 8 is a cross-sectional view illustrating one embodiment of a semiconductor device of the present invention.

FIG. 9 is a view in which a polysilicon layer 4 is formed after forming an element isolation region and a silicon oxide film 3 in a conventional method.

FIG. 10 shows a conventional method in which a resist film is formed and then NM
FIG. 4 is a diagram in which only an OS region is opened and phosphorus is ion-implanted.

FIG. 11 is a diagram in which gate electrodes 16 and 17 are formed in a conventional method.

FIG. 12 is a diagram showing arsenic ion implantation for forming an LDD in a conventional method.

FIG. 13 is a view in which a sidewall 20 is formed in a conventional method.

FIG. 14 is a diagram illustrating ion implantation of arsenic on a polycrystalline silicon layer and a silicon substrate in a conventional method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation film, 3 ... Oxide insulating film (gate insulating film), 4 ... Polycrystalline silicon layer, 5, 8, 1
1, 18, 23: a resist film; 6, 16, a gate electrode of an electric field transistor driven at a high voltage; 7, 17, a gate electrode of an electric field transistor driven at a low voltage;
Side wall, 12, 21, ... drain region, 13, 2
2 ... source region, 10, 19 ... LDD, 14 ... n well, 15 ... p well

Claims (11)

[Claims] 1. A semiconductor device having a first insulated gate field effect transistor driven at a low voltage and a second insulated gate field effect transistor driven at a high voltage. A plurality of impurities having the same conductivity type as the channel and having different diffusion constants are introduced into the gate electrode, and the diffusion constant or the solid solubility of the plurality of impurities among the plurality of impurities is introduced into the gate electrode of the second insulated gate field effect transistor. A semiconductor device into which small impurities are introduced. 2. The semiconductor device according to claim 1, wherein phosphorus and arsenic are introduced into a gate electrode of said first insulated gate field effect transistor. 3. The semiconductor device according to claim 1, wherein boron and indium are introduced into a gate electrode of said first insulated gate field effect transistor. 4. The semiconductor device according to claim 1, wherein arsenic is introduced into a gate electrode of said second insulated gate field effect transistor. 5. The gate electrode of the second insulated gate field effect transistor is doped with indium or boron having a concentration lower than that of boron introduced into the gate electrode of the first insulated gate field effect transistor. The semiconductor device according to claim 1, wherein: 6. The semiconductor device according to claim 1, wherein the semiconductor device has a p-channel type and an n-channel type as the first and second insulated gate field effect transistors, respectively. 7. A method of manufacturing a semiconductor device having a first insulated gate field effect transistor driven at a low voltage and a second insulated gate field effect transistor driven at a high voltage. Forming a layer made of amorphous or polycrystalline silicon through a film; and forming the first layer of the layer made of amorphous or polycrystalline silicon.
A first impurity introducing step of introducing an impurity having the same conductivity type as that of the channel and having a large diffusion constant into a region to be a gate electrode of the insulated gate field effect transistor of the first and second insulated gate field effect transistors. A second impurity introducing step of introducing an impurity having a low diffusion constant or a low solid solubility among the plurality of impurities into the gate electrode. 8. After the first impurity introducing step, the amorphous or polycrystalline silicon layer is patterned.
Forming gate electrodes of a first field-effect transistor driven at a low voltage and a second insulated gate field-effect transistor driven at a high voltage, and in the second impurity introducing step, 8. The source and drain regions of an insulated field effect transistor are formed simultaneously.
The manufacturing method of the semiconductor device described in the above. 9. The method according to claim 7, wherein the impurity in the first impurity introducing step is phosphorus, and the impurity in the second impurity introducing step is arsenic. 10. The method according to claim 7, wherein the impurity in the first impurity introducing step is boron, and the impurity in the second impurity introducing step is indium. 11. An impurity in the first and second impurity introducing steps is boron, and in the second impurity introducing step, a concentration is set lower than an impurity concentration in the first impurity introducing step. 8. The method for manufacturing a semiconductor device according to item 7.