JPH05211163A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To manufacture a MIS field-effect transistor having higher field relieving effect by a method wherein at least the nearby part of a gate electrode sidewall out of the sidewall spacers in the device actuating state after the formation of a drain region is to be made of a high dielectric constant material having the specific dielectric constant exceeding three times the dielectric constant of a gate insulating film. CONSTITUTION:An LDD structured MIS type field-effect transistor is composed of a drain region comprising a low concentration impurity layer 2 and a high concentration impurity layer 3, a gate electrode 5 formed on the low concentration layer 2 through the intermediary of a gate insulating film 4 as well as a sidewall spacer 8 formed on the sidewalls of the gate electrode 5 and the low concentration impurity layer 2. In order to manufacture the spacer 8, after the formation of the low concentration impurity layer 2 and a high concentration impurity layer 3 as the drain region, the sidewall spacer 8 made of the high dielectric constant material having the specific dielectric constant exceeding three time of the dielectric constant of the gate insulating film 4 is formed in the nearby part of the sidewall of gate electrode 5. Through these procedures, the element inner electric field can be relieved by affording a wide gate fringe electric field.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, it includes an insulated gate type (hereinafter referred to as MIS type) field effect transistor suitable for high reliability and high current driving capability. And a method for manufacturing the same.

[0002]

2. Description of the Related Art To improve the reliability of a MIS field effect transistor, it is effective to relax the electric field inside the device by improving the drain structure. As a highly reliable structure of a conventionally known MIS field effect transistor, there is a low concentration drain structure, that is, a so-called LDD (Lightly Doped Drain) structure. The low-concentration diffusion layer of the LDD structure relaxes the electric field inside the device and improves the long-term operation reliability of the transistor, but it functions as a resistor connected in series with the transistor and causes a reduction in the current driving capability. Further, even with this LDD structure, when the gate length becomes 0.5 μm or less, it becomes difficult to use the conventional power supply voltage of 5V. Therefore, as a structure having an improved LDD structure with higher reliability and high current drive capability, a structure in which the gate electrode and the low-concentration diffusion layer are sufficiently overlapped with each other is being studied. As an example of this, as discussed in JP-A-62-156873 and JP-A-1-05470, a sidewall spacer made of a conductive film is provided on the low-concentration diffusion layer to provide self-alignment. A structure in which a gate and a drain are sufficiently overlapped with each other and a manufacturing method thereof can be given. Further, as another improved structure, Japanese Patent Laid-Open No. 59-2
As discussed in Japanese Patent No. 31864, there is a structure in which a sidewall spacer made of polycrystalline silicon is provided and a manufacturing method thereof. These manufacturing methods are shown in FIGS. 2 and 3, respectively. 1 is a silicon substrate, 2 is a low impurity concentration source / drain diffusion layer (hereinafter abbreviated as low concentration diffusion layer), 3 is a high impurity concentration source / drain diffusion layer (hereinafter abbreviated as high concentration diffusion layer), 4 Is a gate insulating film, 5 is a gate electrode, and 9 and 10 are sidewall spacers made of polycrystalline silicon.

First, the known example shown in FIG. 2 is a conventional LDD.
The sidewall spacer in the structure is formed by changing the silicon dioxide to polycrystalline silicon. First, as shown in FIG. 2A, after a gate electrode 5 made of polycrystalline silicon is formed in a desired region by a known manufacturing method, a low concentration diffusion layer is formed by ion implantation using the gate electrode 5 as a mask and subsequent heat treatment. Form 2. Next, a polycrystalline silicon film and anisotropic dry etching are used to form the structure shown in FIG.
As described above, the side wall spacer 9 made of polycrystalline silicon is formed. Finally, as shown in FIG. 2C, a high concentration diffusion layer 3 is formed by ion implantation using the gate electrode 5 and the sidewall spacer 9 as a mask and subsequent heat treatment. After that, the transistor is completed by a known technique. At this time, the side wall spacer 9 is also doped with an impurity at a high concentration to become the low resistance element 10.

The known example shown in FIG. 3 is shown in FIG.
After coating the surface of the side wall spacer 9 made of polycrystalline silicon with the silicon dioxide film 13 formed by thermal oxidation as shown in FIG. 3, the gate electrode 5 and the side wall spacers 9 and 10 are formed as shown in FIG. 3B. The high concentration diffusion layer 3 is formed by ion implantation using a mask and subsequent heat treatment. Further, in FIG. 2 or FIG. 3, the electrical contact between the gate electrode 5 and the sidewall spacer electrode 10 can be realized by direct contact, connection through the ultrathin silicon dioxide film 7 on the side wall of the gate electrode, or the like. As a result, the sidewall spacer 10 serves as an overlap electrode with the low-concentration drain 2, so that high reliability and high current driving capability can be realized.

[0005]

In the above-mentioned conventional technique, the LDD structure in which the gate electrode and the low-concentration diffusion layer are sufficiently overlapped can be expected to have higher reliability and higher current driving capability than the normal LDD structure. ..

However, in the known example of FIG. 2 in which the side wall electrode 10 is a conductive film, there is a problem that the electric field concentration in the high-concentration diffusion layer becomes remarkable and the reliability is lowered. Further, in the structure of the known example of FIG. 3, the impurity concentration of the polycrystalline silicon that is the sidewall spacer becomes low, and the electric field relaxation effect can be increased as the conductor becomes a dielectric. It was made clear by the examination. This is because the dielectric constant of silicon can be made larger than that of the gate insulating film material (usually a silicon oxide film) as compared with the conventional LDD structure in which the sidewall spacer is made of the same insulating material as the gate insulating film.
This is because the gate fringe electric field to the low concentration diffusion layer can be increased. However, in the known example of FIG. 3, when the high-concentration source and drain are formed by ion implantation, impurities are introduced through the oxide film above the sidewalls. Therefore, the known example of FIG. 3 also has a problem that the side wall spacer is also a low resistance element, and the electric field concentration becomes remarkable in the high concentration diffusion layer as in the known example of FIG. Therefore, an object of the present invention is to provide a MIS field effect transistor having a large electric field relaxation effect and a method for manufacturing the same.

[0007]

In order to achieve the above object, a semiconductor device according to the basic technical concept of the present invention has a drain region formed of a low concentration impurity layer and a high concentration impurity layer, and a low concentration impurity layer formed on the drain region. An MIS type field effect transistor having an LDD structure having a gate electrode formed via a gate insulating film and a sidewall spacer formed on the side wall of the gate electrode and the low-concentration impurity layer, the drain region At least a portion of the side wall spacer near the side wall of the gate electrode in the device operating state after formation of the above is formed of a high dielectric constant material having a relative dielectric constant three times or more the dielectric constant of the gate insulating film. Is characterized by.

In a method of manufacturing a semiconductor device according to a typical embodiment of the present invention, a drain region is composed of a low concentration impurity layer and a high concentration impurity layer, and is formed on the low concentration impurity layer via a gate insulating film. A MIS field effect transistor having an LDD structure having a gate electrode and a sidewall spacer formed on the side wall of the gate electrode and the low concentration impurity layer, wherein the low concentration as the drain region is provided. After forming the impurity layer and the high-concentration impurity layer, a high dielectric constant material having a relative dielectric constant three times or more the dielectric constant of the gate insulating film is formed in a portion near the sidewall of the gate electrode. Characterize.

[0009]

Therefore, in the semiconductor device according to the basic technical concept of the present invention, the portion near the sidewall of the gate electrode is a high dielectric constant material having a relative dielectric constant three times or more the dielectric constant of the gate insulating film. A large gate fringe electric field can be applied on the low-concentration impurity layer in the region, and the electric field inside the element can be relaxed. This significantly reduces the amount of hot carriers generated.

This will be described in more detail with reference to FIG. FIG. 4 is a computer simulation of the dielectric constant dependency of the spacer material of the maximum electric field in the channel direction in the LDD structure MIS field effect transistor. The dielectric constant is represented by the ratio of the gate insulating film material (silicon oxide film in this case) to the dielectric constant. When this value is 1, the spacer material and the gate insulating film material have the same dielectric constant and have a normal LDD structure. As a result, it was found that when the dielectric constant of the spacer material is increased, the internal electric field sharply decreases when the ratio is 3 or more. That is, it is desirable that the dielectric constant of the portion of the spacer material near the side wall of the gate electrode is three times or more that of the gate insulating film material. As described above, the high dielectric constant material having a relative dielectric constant of 3 or more can be achieved by using substantially non-doped high resistance semiconductors such as silicon and germanium. Therefore, the high-resistance semiconductor may be mixed with a very small amount of impurities as long as it is within the range of acting as a dielectric. Also,
In this structure, the gate fringe electric field becomes weaker in the low-concentration diffusion layer region farther from the gate electrode. For this reason,
In this structure, the electric field relaxation effect acts on the low-concentration diffusion layer near the gate electrode as in the gate-drain overlap structure, and there is almost no decrease in reliability due to electric field concentration at the end of the high-concentration diffusion layer at a distance. become. Other objects and features of the present invention will be apparent from the following examples.

[0011]

<Embodiment 1> A first embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a diagram schematically showing a manufacturing process for forming an n-channel MIS type field effect transistor as a typical manufacturing method of the present invention. A case where a non-doped polycrystalline silicon film is used as the high-resistance semiconductor film will be described. FIG. 1A shows a p-type 1 first.
After forming the element isolation region on the 0 Ω-cm silicon substrate 1,
After the gate insulating film 4 made of silicon dioxide, the polycrystalline silicon 5 heavily doped with phosphorus and the silicon dioxide film 11 are sequentially coated and the gate electrode 5 is patterned,
FIG. 3 is a cross-sectional view after forming an n-type low-concentration impurity layer 2 by ion implantation of phosphorus using the gate electrode 5 as a mask and subsequent heat treatment. Here, the gate insulating film 4 is 8 to 15
nm, and the dose amount of phosphorus in the low concentration impurity layer 2 is 1 to 2
It is × 10 ¹³ / cm ² . Further, since the high selectivity process was used for the gate electrode process, the silicon dioxide film 6 on the low concentration impurity layer 2 was scarcely scraped. Next, FIG. 1 (b)
As described above, a thin film of silicon dioxide 6 is coated to a thickness of 5 to 10 nm by using a CVD method or a thermal oxidation method, and then a polycrystalline silicon film 12 is formed to a thickness of 150 to 150 nm for the first sidewall spacer.
180 nm coating. Subsequently, the polycrystalline silicon film 6 is processed by the film thickness by anisotropic dry etching. As a result, the sidewall spacer 12 made of polycrystalline silicon can be formed on the sidewall of the gate electrode 5 as shown in FIG. At this time, the width of the sidewall spacer 12 is 13
It was 0 to 160 nm. Subsequently, arsenic is added to 2 to 5 × 10 ¹⁵
/ Cm ^{2 is} doped to form the high-concentration impurity layer 3. At this time, arsenic is also introduced into the first sidewall spacer 12. Next, as shown in FIG. 1C, the first sidewall spacer 12 is removed by isotropic dry etching or wet etching. In this example, an alkaline aqueous solution such as ammonia or hydrazine was used. Finally, as shown in FIG. 1D, the non-doped polycrystalline silicon film 8 is again coated to a thickness of 160 to 200 nm for the second sidewall spacer. Subsequently, the polycrystalline silicon film 8 is processed by the film thickness by anisotropic dry etching. As a result, the sidewall spacer 8 made of non-doped polycrystalline silicon can be formed again on the sidewall of the gate electrode 5. At this time, the width of the sidewall spacer 8 was 140 to 180 nm. In the subsequent steps, a film of an interlayer insulating film is formed by a known MIS transistor forming method,
The process is completed by opening contact holes and forming a metal wiring layer. At this time, the interlayer insulating film which is in direct contact with the second sidewall spacer 8 has a multilayer film structure in which a non-doped silicon dioxide film formed by the CVD method is coated and a boron phosphorus silicate glass film is coated thereon. As a result, no impurities were introduced into the second sidewall spacer 8 in the subsequent steps. As described above, the LDD structure having the semiconductor sidewall spacer with high resistance can be formed in a self-aligning manner as in the conventional LDD structure forming process. As a result, since the dielectric constant of the non-doped polycrystalline silicon film 8 is about three times as large as that of the silicon dioxide film, the electric field relaxation effect is sufficiently large as shown in FIG. As a result, the hot carrier withstand voltage (transmission conductance Gm), which is an index of reliability, is higher than that of the MIS field effect transistor having the LDD structure in which the sidewall spacers are also made of silicon dioxide.
Is defined as a drain voltage that fluctuates 10% in 10 years) about 1
V could be improved. Further, in this embodiment, since the high-concentration impurity layer 3 extends to the lower part of the sidewall spacers 8, the current driving ability could be improved by about 20% as compared with the normal LDD structure. Note that the n-channel is used in the above embodiment, but by reversing the conductivity type, a transistor having a similar electric field relaxation effect can be obtained in the p-channel. Further, the high resistance semiconductor material 8 is not limited to the polycrystalline silicon film,
It may be non-doped germanium or non-doped gallium arsenide. Further, the gate electrode material may be any of metal, a multi-layer film of metal and silicon, and the gate oxide film material may be another high dielectric material. In particular, since the silicon oxide film thickness is approaching its thinning limit in the future, it is considered that other high dielectric constant insulators (silicon nitride film, tantalum oxide film, etc.) are used. Better characteristics can be obtained by changing to a high resistance semiconductor. Further, the high-concentration impurity layer 3 does not have to reach the bottom of the high-resistance semiconductor sidewall spacer. In this case, the improvement in current driving capability is small, but the improvement in reliability such as the electric field relaxation effect is the same.
In other words, the high resistance semiconductor film is a part of the upper part of the low concentration layer,
In particular, it may be in the vicinity of the gate electrode. Further, the high-resistance semiconductor film 8 is not limited to the sidewall spacer, but may be a part of the interlayer insulating film that functions as a dielectric if it is in the above position. In particular, the interlayer insulating film is suitable in the case of a high resistance semiconductor material having poor film properties, so-called coverage.

<Second Embodiment> Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 shows a manufacturing method capable of increasing the process margin when forming the sidewall spacers in the first embodiment of the present invention. As the high resistance semiconductor film, the case where a non-doped polycrystalline silicon film is used as described above will be described. Figure 5
(A) shows a gate insulating film 4 made of silicon dioxide and polycrystalline silicon 5 heavily doped with phosphorus after forming an element isolation region on a p-type 10 Ω-cm silicon substrate 1 as in the first embodiment. , Sequentially coating the silicon dioxide film 11,
6 is a cross-sectional view after forming the n-type low-concentration impurity layer 2 by patterning the gate electrode 5, ion implantation of phosphorus using the gate electrode 5 as a mask, and subsequent heat treatment. Here, the gate insulating film 4 has a thickness of 8 to 15 nm, and the dose amount of phosphorus in the low concentration impurity layer is 1 to 2 × 10 ¹³ / cm ² . Further, a silicon dioxide film 11 is coated on the gate electrode 5 in advance to a thickness of 150 to 200 nm. Next in FIG.
As shown in (b), a thin film of silicon dioxide is coated to a thickness of 5 to 10 nm by the CVD method, and subsequently a silicon nitride film 14 is coated to a thickness of 150 to 180 nm for the first sidewall spacer. Then, the silicon nitride film 14 is processed by the thickness of the film coated by anisotropic dry etching. As a result, FIG. 5 (b)
As described above, the sidewall spacer 14 made of the silicon nitride film can be formed on the sidewall of the gate electrode 5. At this time, the width of the sidewall spacer 14 is 130 to 160 nm, and the silicon dioxide film on the silicon substrate other than under the spacer is scarcely left. Subsequently, a thermal oxide film is selectively formed on the silicon substrate to have a thickness of about 15 to 30 nm.
As a result, only the silicon dioxide film 15 on the silicon substrate other than the lower portion of the spacer 14 can be thickened.
That is, the material of the first sidewall spacer 14 needs to be an oxidation resistant material. Then add 2-5x arsenic
A high concentration impurity layer 3 is formed by doping 10 ¹⁵ / cm ² .
Next, as shown in FIG. 5C, the first sidewall spacer 14 is removed by isotropic dry etching or wet etching. Finally, as shown in Fig. 5 (d),
A non-doped polycrystalline silicon film 8 is coated to a thickness of 160 to 200 nm for the second sidewall spacer. continue,
The polycrystalline silicon film 8 is processed by the film thickness by anisotropic dry etching. As a result, the sidewall spacer 8 made of polycrystalline silicon can be formed on the sidewall of the gate electrode 5. At this time, the width of the sidewall spacer 8 is 14
It was 0 to 180 nm. The subsequent steps are completed by the same steps as in the first embodiment. Second sidewall spacer 8
Impurities were not introduced in the subsequent steps, as in the first embodiment. In the transistor formed as described above, the thickness 6 of the silicon dioxide film below the second sidewall spacer 8 is finally 5 to 8 nm through this step, which is thinner than the thickness of the gate insulating film 4. Is becoming Here, the width of the second sidewall spacer 8 is preferably larger than the width of the first sidewall spacer 14 shown in FIG. 5B. On the contrary, if this is small, the silicon substrate may also be processed when the second sidewall spacer 8 is formed.
According to the present embodiment, only the silicon dioxide film 15 on the silicon substrate other than under the spacer can be thickened, so that the silicon substrate is not processed when the second sidewall spacer 8 is formed. , Process tolerance can be very large. However, in this embodiment,
The thickness of the silicon dioxide film 6 below the spacer 14 is as shown in FIG.
In (c), the thickness is required so that it will not be lost when the first sidewall spacer 14 is removed by isotropic etching. However, if the film thickness of the silicon dioxide 6 is too thick, a comparatively thick oxide film remains in the vicinity of the end of the gate electrode, and the electric field relaxation effect becomes small. As a method for preventing this, a method obtained by further improving the present embodiment is shown in FIGS. This is one in which the first sidewall spacer is formed from a thin film 16 of silicon nitride film and a thick film 17 of polycrystalline silicon. A process drawing at this time is shown in FIG. The process up to the formation of the low-concentration impurity layer 2 is the same as in the above embodiment. When removing the first sidewall spacers 16 and 17 made of a multilayer film, the removal of the polycrystalline silicon 17 occupying most of the spacers can be stopped by the silicon nitride film 16. Next, the exposed silicon substrate not covered with the thin silicon nitride film 16 is selectively oxidized as shown in FIG. 5F to form a silicon dioxide film 15 of 20 to 30 nm. Subsequently, the silicon nitride film 16 is removed by isotropic etching, and the process is completed in the same process as that in FIG. As described above, according to the present embodiment, it is possible to further improve the process margin and obtain a transistor having characteristics equal to or higher than those of the first embodiment.

<Third Embodiment> Next, a third embodiment of the present invention will be described with reference to FIGS.

FIG. 6 is a diagram showing a manufacturing method capable of increasing the process margin at the time of forming the sidewall spacers, as in the second embodiment of the present invention. A case where a non-doped polycrystalline silicon film is used as the high-resistance semiconductor film for the sidewall spacer will be described. Figure 6
(A): First, after forming an element isolation region on a p-type 10 Ω-cm silicon substrate 1, a gate insulating film 4 made of silicon dioxide, polycrystalline silicon heavily doped with phosphorus, and a relatively thick silicon dioxide film. After coating 11 and patterning the gate electrode 5 by a known technique, phosphorus is ion-implanted using the gate electrode 5 as a mask and the subsequent heat treatment is performed.
It is a cross-sectional view after forming the low concentration impurity layer 2 of the mold. Here, the gate insulating film 4 has a thickness of 9 to 15 nm, and the phosphorus dose amount of the low concentration impurity layer 2 is 1 to 2 × 10 ^13.
/ Cm ² . Further, since the high selectivity process is used for the gate electrode process, the silicon dioxide film 6 on the low concentration impurity layer 2 is processed.
The shavings were very slight. Next, as shown in FIG.
5-1 on the sidewall of the gate electrode by thermal oxidation in a dry atmosphere
A silicon dioxide film having a thickness of 0 nm is formed, and subsequently, a thin film 40 of a silicon nitride film is coated to a thickness of 10 to 20 nm and a polycrystalline silicon film 12 for a first sidewall spacer is coated to a thickness of 150 to 180 nm by using a CVD method. Subsequently, the polycrystalline silicon film 12 is processed by the film thickness coated by anisotropic dry etching. At this time, the thin film 40 of the silicon nitride film serves as a protective film against the processing of the underlying silicon oxide film. As a result, the sidewall spacers 12 made of polycrystalline silicon could be formed on the sidewalls of the gate electrode 5 as shown in FIG. 6B. At this time, the width of the sidewall spacer is 1
It was 50 to 200 nm. Then add 2-5 × 10 arsenic
^A high-concentration impurity layer 3 is formed by heat treatment in a nitrogen atmosphere at 850 ° C. for about 10 minutes by doping at ¹⁵ / cm ² . At this time, high concentration of arsenic is also introduced into the first sidewall spacer 12. Next, as shown in FIG. 6C, the first sidewall spacer 12 is removed by isotropic dry etching or wet etching, and then the silicon nitride thin film 40 is removed by wet etching. Here, when the first sidewall spacer is made of silicon, if an alkaline aqueous solution such as ammonia or hydrazine is used as the wet etching solution, the selection ratio with respect to the base insulating film can be made very high. Finally, as shown in FIG. 6D, the non-doped polycrystalline silicon film 8 is again provided with 160 to 20 for the second sidewall spacer.
Coating with 0 nm. Subsequently, the polycrystalline silicon film 8 is processed by the film thickness by anisotropic dry etching. As a result, the sidewall spacer 8 made of polycrystalline silicon can be formed again on the sidewall of the gate electrode 5. At this time, the width of the sidewall spacer 8 was 140 to 180 nm. The subsequent steps are completed by forming a film of an interlayer insulating film, opening a contact hole, and forming a metal wiring layer by a known MIS transistor forming method. At this time, the interlayer insulating film in direct contact with the second sidewall spacer 8 is formed by CVD.
A non-doped silicon dioxide film was coated by the method, and a boron phosphorus silicate glass film was coated thereon to form a multilayer film structure. As a result, in the subsequent steps, the second sidewall spacer 8 is formed.
No impurities were introduced into. As described above, the LDD structure having the high-resistance semiconductor sidewall spacer can be formed in a self-aligning manner as in the first embodiment. As a result, the spacer base silicon oxide thin film 6 was not removed when the first sidewall spacer was formed. As a result, it was possible to obtain a MIS field effect transistor having a larger process margin and the same characteristics as those of the first embodiment. In the above embodiment, polycrystalline silicon is used as the protective film material for the first spacer and the underlying oxide film, respectively.
And a silicon nitride film were used. Any material can be used for the first spacer as long as it is a material that can be easily removed.
For example, a silicon nitride film may be used. At this time, polycrystalline silicon may be used as the underlayer protection thin film.
This case is suitable when the surface of the impurity layer and the surface of the gate electrode are silicided in a self-aligned manner.

FIG. 7 shows a sectional view of another MIS type field effect transistor formed by applying the manufacturing method of the third embodiment. First, FIG. 7 (a) shows that the controllability of the thickness of the silicon dioxide thin film below the sidewall spacers 8 is improved in the above embodiment. In the above embodiment, the silicon dioxide thin film is formed together with the gate electrode side wall by thermal oxidation after processing the gate electrode. However, in the case of the n-type highly-doped polycrystalline silicon electrode, a particularly large gate bird's beak is likely to be formed in this method, so that the film thickness cannot be formed too thick. Therefore, in the embodiment of FIG. 7A, the silicon dioxide thin film 41 is formed to a thickness of about 10 to 15 nm by the CVD method before forming the silicon nitride film 40 in FIG. 6B. Thus, without forming the gate bird's beak, the gate electrode side wall silicon oxide film thickness is 10 to 15 nm, the spacer base silicon oxide film thickness is 15 to 20 nm, and the spacer base silicon oxide film thickness is compared with the gate electrode side wall silicon oxide film thickness. And could be thickened. This method is more effective when a material other than silicon is used for the gate electrode.
On the other hand, in FIG. 7B, which is an alternative technique of FIG. 7A, a nitride oxide film 42 formed by using a rapid oxidation and a rapid nitriding method is used as the sidewall spacer base insulating film. This film has better interface characteristics with silicon than a silicon dioxide film, and traps due to hot carriers are less likely to be generated. As a result, the long-term reliability of the transistor formed of this material can be greatly improved. FIG. 7C, which is a similar alternative technique, shows the width of the second spacer 43 made of non-doped polycrystalline silicon shorter than the width of the first spacer in the above embodiment. At this time, the width of the second spacer 43 is shorter than the width of the first spacer by the length by which the high-concentration impurity layer 3 diffuses and extends in the lateral direction. Thereby, the extra parasitic capacitance between the gate and the source / drain could be minimized. FIG. 7 (d), which is a similar alternative technique, shows that the second spacer 8 made of non-doped polycrystalline silicon and the drain 3 in the above-described embodiment are connected by another wiring layer. In this embodiment, the wiring layer 45 made of polycrystalline silicon is used.
Was used. Reference numeral 44 is an interlayer insulating film made of silicon dioxide formed by the CVD method. As a result, the hot carriers injected into the spacer can be quickly discharged, and the long-term reliability can be further improved. Finally, FIG. 7E shows an improvement in the shape of the second spacer made of non-doped polycrystalline silicon in the above embodiment. In the present embodiment, the spacer 46 having a forward taper shape in which the lower portion of the spacer is thicker than the upper portion of the spacer is used under the etching condition in which the sidewall protection deposit is easily attached at the anisotropic drain etching of the spacer. As a result, the step difference of the gate electrode can be greatly alleviated, and the upper wiring layer can be easily formed. In addition, all of the embodiments described above are MIS formed on a silicon substrate.
Regarding the type electric field effect, the substrate may be either thin film silicon formed on an insulating film or polycrystalline silicon.
Further, in this case, the gate electrode may be provided not only on one surface of the thin film silicon but also on both surfaces.

<Embodiment 4> Next, a fourth embodiment of the present invention will be described with reference to FIGS. 8, 9 and 10. These show a manufacturing method capable of reducing the number of steps as compared with the first embodiment of the present invention. As the high resistance semiconductor film, the case where a non-doped polycrystalline silicon film is used as described above will be described.

As shown in FIG. 8A, a gate insulating film 4 made of silicon dioxide and a high concentration of phosphorus are formed after forming an element isolation region on a p-type 10 Ω-cm silicon substrate 1 as in the first embodiment. Polycrystalline silicon 5, silicon dioxide film 1
2 is a cross-sectional view after forming the n-type low-concentration impurity layer 2 by ion-implanting phosphorus with the gate electrode 5 as a mask and subsequent heat treatment after the gate electrode 5 is patterned and the gate electrode 5 is patterned. Here, the gate insulating film 4 has a thickness of 8 to 15 nm, and the dose amount of phosphorus in the low concentration impurity layer is 1 to 2 × 10 ^13.
/ Cm ² . In addition, a silicon dioxide film 11 having a large thickness of 200 to 350 nm is previously coated on the upper portion of the gate electrode to increase the level difference. Next, as shown in FIG. 8B, a thin film 6 of silicon dioxide is coated to a thickness of 5 to 10 nm by the CVD method, and subsequently a non-doped polycrystalline silicon film 19 for the first sidewall spacer is coated to a thickness of 100 to 130 nm. Then, the polycrystalline silicon film 19 is processed by anisotropic dry etching. As a result, sidewall spacers 19 made of a polycrystalline silicon film can be formed on the sidewalls of the gate electrode 5 as shown in FIG. 8B. At this time, the sidewall spacer 19 has a width of 80 to 120 nm, and the spacer height is formed so as to cover a part of the gate electrode step as shown in the figure. Next, a silicon nitride film 20 is coated to a thickness of 100 to 150 nm for the second sidewall spacer. Then, the silicon nitride film 20 is processed by the film thickness by anisotropic dry etching. As a result, as shown in FIG. 8C, the sidewall spacer 20 made of a silicon nitride film can be formed around the sidewall of the gate electrode 5 and the first sidewall spacer 19. Thereafter, as shown in FIG. 8 (d), arsenic is ion-implanted into the high-concentration impurity layer 3 by 2-5 × 10 ¹⁵ / cm ^{2 using} the first and second sidewall spacers 19 and 20 as a mask. .. The subsequent steps are completed by the same steps as those in the second embodiment. An impurity is introduced into the second sidewall spacer 20 made of a silicon nitride film as in the first embodiment, but an impurity is introduced into the first sidewall spacer 19 made of non-doped polycrystalline silicon. It was never done. According to the present embodiment, it is possible to omit the step of forming and removing the sidewall spacer that serves as a mask at the time of forming the high-concentration impurity layer, and it is possible to significantly reduce the number of steps. Further, the thickness of the insulating film below the spacer can be controlled more easily.
The material of the second sidewall spacer 20 may be a silicon oxide film. In this case, the silicon oxide film 6 on the silicon substrate is lost during the processing of the second sidewall spacer, but the silicon oxide film may be coated to a thickness of about 10 nm by the CVD method before implanting the impurity ions for the high concentration impurity layer. Good.

Next, another embodiment will be described with reference to FIGS. 9A and 9B, in which the step of forming a sidewall spacer that serves as a mask and the step of removing the same can be omitted when the high-concentration impurity layer is formed, as in the above-described embodiment. This is because a thin film having oxidation resistance is coated before forming the sidewall spacers, and only the surface of the sidewall spacers is selectively oxidized so that impurities for the high concentration impurity layer are not introduced. is there. First, as shown in FIG. 9A, similarly to the second embodiment, after forming an element isolation region on a p-type 10 Ω-cm silicon substrate 1, a gate insulating film 4 made of silicon dioxide and a highly doped phosphorus film are formed. Crystal silicon 5 and silicon dioxide film 1
2 is a cross-sectional view after forming the n-type low-concentration impurity layer 2 by ion-implanting phosphorus with the gate electrode 5 as a mask and subsequent heat treatment after the gate electrode 5 is patterned and the gate electrode 5 is patterned. Here, the gate insulating film 4 has a thickness of 8 to 15 nm, and the dose amount of phosphorus in the low concentration impurity layer is 1 to 2 × 10 ^13.
/ Cm ² . Further, a silicon dioxide film 11 having a thickness of 150 to 200 nm is formed on the gate electrode in advance. Next, a thin film of the silicon nitride film 21 is formed by using the CVD method.
~ 30 nm coating. Next, as shown in FIG. 9B, subsequently, a non-doped polycrystalline silicon film 8 for the sidewall spacer is coated to a thickness of 170 to 200 nm, and then the polycrystalline silicon film 8 is coated by anisotropic dry etching to a thickness corresponding to the film thickness. To process. As a result, sidewall spacers 8 made of a polycrystalline silicon film can be formed on the sidewalls of the gate electrode 5 as shown in FIG. 9B. At this time, the width of the sidewall spacer is 150 to 180 nm, and the underlying silicon nitride film 21 remains on the entire surface. Next, as shown in FIG. 9C, a thermal oxide film 22 is formed to a thickness of 100 to 150 nm only on the exposed surface portion of the sidewall spacer 8 made of a polycrystalline silicon film. Thereafter, as shown in FIG. 9 (d), arsenic is added in an amount of 2 to 5 × 10 ¹⁵ / cm ^2.
Ions are implanted to form the high-concentration impurity layer 3. The subsequent steps are completed by the same steps as in the above embodiment. At this time, the thickness of the silicon dioxide film 22 on the side wall spacer surface is such that ions cannot pass through in the subsequent ion implantation, whereas the thickness of the insulating film 21 on the silicon substrate is sufficient for ions to pass through. Thickness. For this reason, no impurities were introduced into the sidewall spacers 8 made of polycrystalline silicon as in the first embodiment. Further, in this embodiment, the exposed silicon nitride film 21 may be removed after the step shown in FIG. 9C and before the ion implantation step for forming the high-concentration impurity layer. According to this embodiment, similarly to the above-described embodiments, it is possible to omit the step of forming the sidewall spacer that serves as a mask and the step of removing the same when forming the high-concentration impurity layer, and it is possible to greatly reduce the number of steps. Further, the thickness of the insulating film below the spacer can be controlled more easily.

Further, FIG. 10 shows still another embodiment in which the formation of the sidewall spacers serving as a mask and the removal process thereof can be omitted when forming the high-concentration impurity layer, as in the above-mentioned embodiment. This is because the sidewall spacers are formed to have a sufficiently high height so that the impurities do not substantially reach the gate electrode sidewalls even if the impurities for the high concentration impurity layer are introduced. First, as shown in FIG. 10A, after forming the gate electrode 5 and the low-concentration impurity layer 2 on the silicon substrate 1 as in the second embodiment,
It is a cross-sectional view after forming the sidewall spacer 8 made of non-doped polycrystalline silicon. Here, the gate insulating film 4 has a thickness of 8 to 15 nm, and the dose amount of phosphorus in the low concentration impurity layer is 1 to 2 × 10 ¹³ / cm ² .
Further, a silicon dioxide film 11 having a thickness of 350 to 400 nm, which is a sufficiently thick film, is formed on the gate electrode in advance. Next, as shown in FIG. 10B, a thin film 23 of silicon dioxide is coated to a thickness of 5 to 10 nm by the CVD method, and arsenic is added to a thickness of 2 to 5 × 10 ^15.
/ Cm ² ions are implanted to form the high concentration impurity layer 3. The subsequent steps are completed by the same steps as in the above embodiment. At this time, unlike the first embodiment, the impurities for the high-concentration impurity layer are introduced into the sidewall spacer 8 made of polycrystalline silicon through a thin film of silicon dioxide on the upper portion thereof. However, in this embodiment, FIG.
As shown in (b), the impurities for forming the high-concentration impurity layer exist only in the upper portion of the spacer and do not reach the side wall of the gate electrode even after the subsequent heat treatment step. As a result, almost the same effect as that of the first embodiment could be obtained. In this example,
In order to prevent the above impurities from diffusing to the side wall of the gate electrode, it is necessary to make the thickness of the silicon dioxide film previously formed on the upper part of the gate electrode sufficiently thick and to increase the step. In the subsequent heat treatment, it is necessary to use a rapid annealing method or the like to reduce the thermal history. According to this embodiment, similarly to the above-described embodiments, it is possible to omit the step of forming the sidewall spacer that serves as a mask and the step of removing the same when forming the high-concentration impurity layer, and it is possible to greatly reduce the number of steps. Particularly, the number of steps in this embodiment is almost the same as that of the conventional LDD forming step. In addition, the thickness of the insulating film below the spacer can be controlled more easily.

<Embodiment 5> Next, an embodiment of another structure formed by using the manufacturing method shown in the first, second and third embodiments of the present invention will be described with reference to FIG. First, FIG.
In (a), a source region and a drain region composed of the low-concentration impurity layer 2 and the high-concentration impurity layer 3 are three-dimensionally formed to improve device characteristics. As in the previous embodiment, 1 is a p-type silicon substrate, 2 is a low concentration impurity layer, 3 is a high concentration impurity layer, and 4 is a gate insulating film. A groove of 300 nm is formed, and the gate electrode 27 is embedded therein. At this time, the sidewall spacer 25 made of a high resistance semiconductor is formed in the step portion of the groove in the substrate by any one of the methods described above. As a result, the depth of the source / drain impurity layer can be increased, so that the impurity layer of low resistance and low capacity can be formed,
The same effect as that of the first embodiment can be obtained. Also,
FIG. 11B shows the silicon substrate 1 of the first embodiment changed to a silicon thin film 31 on an insulating substrate 31. The silicon thin film may be single crystal or polycrystalline. In any case, in addition to the above-mentioned effects, a thinning effect occurred, and it was possible to suppress the short channel effect and obtain a further electric field relaxation effect. Further, FIG. 11C shows that in the first embodiment, the low concentration impurity layer 2 is omitted and only the high concentration impurity layer 32 is used for MI.
The S field effect transistor is formed. At this time, the high-concentration impurity layer is formed from outside the spacer by introducing an impurity having a sufficiently large diffusion coefficient and performing sufficient heat treatment. According to the present embodiment, when the reliability is not required to be improved so much, the current driving capability can be improved in, for example, a p-channel MIS field effect transistor. In particular, this embodiment is more suitable when the high-concentration impurity layer is formed by oblique ion implantation.

<Sixth Embodiment> Next, a sixth embodiment of the present invention will be described with reference to FIGS. 12 to 17 show a complementary field effect MIS transistor (CMO) in which the first embodiment of the present invention has a single n channel.
It shows a manufacturing method when applied to the process of S). As the high resistance semiconductor film, the case where a non-doped polycrystalline silicon film is used as described above will be described.

In FIG. 12, first, as in the first embodiment, p
P-type well 5 on a silicon substrate 50 of mold 10 Ω-cm
1. After forming the n-type wells 52 in the regions where the respective elements are to be formed by known methods, the element isolation regions 53 made of thick silicon dioxide and the gate insulating film 5 made of silicon dioxide.
4 is a cross-sectional view after forming No. 4. At this time, the impurity concentration on the well surface is 2 to 4 × 10 ¹⁷ / cm ^3.
And the gate insulating film 54 had a thickness of 8 to 13 nm. Next, as shown in FIG. 13, polycrystalline silicon doped with phosphorus at a high concentration is coated to a thickness of 200 to 300 nm and the gate electrode 55 is patterned. Then, for the n channel, phosphorus ion implantation 56 is performed using the gate electrode 55 as a mask, and the subsequent implantation. An n-type low-concentration impurity layer 58 was formed by heat treatment, boron ion implantation 57 was formed in the p-channel, and a p-type low-concentration impurity layer 59 was formed by subsequent heat treatment. Here, the dose amount of phosphorus and boron in the low-concentration impurity layer is 1 to 2 × 10 ¹³ / cm ² . Then, as shown in FIG. 14, a silicon dioxide thin film 60 is formed to a thickness of 5 to 10 nm by the CVD method, and then a silicon nitride thin film 6 is formed.
1 to 20 to 30 nm, and a doped polycrystalline silicon film 62 in which phosphorus is introduced at a sufficiently high concentration for the first sidewall spacer is coated to 150 to 180 nm by a known CVD method. Next, as shown in FIG. 15, this doped polycrystalline silicon film 62 is processed by the film thickness coated by anisotropic dry etching. As a result, as shown in FIG. 15, the side wall spacer 6 made of a polycrystalline silicon film is formed on the side wall of the gate electrode 55.
3, 64 can be formed. At this time, the width of the sidewall spacers 63 and 64 is 130 to 160 nm. Thereafter, arsenic 65 to the n-channel side, the p-channel side forms a high-concentration impurity layers 67 and 68 in the boron 66 2~5 × 10 ¹⁵ / cm ² Ion implantation and subsequent heat treatment. At this time, high-concentration arsenic is introduced into the sidewall spacer 63 and high-concentration boron is introduced into the sidewall spacer 64. However, what is important at this time is that the sidewall spacer 64 on the p-channel side remains n-type. Next, as shown in FIG. 16, the first sidewall spacers 63 and 64 are removed by isotropic dry etching or wet etching. Generally, isotropic etching with a large selection ratio to the underlying silicon dioxide film (dry etching with SF ₆ gas and wet etching with alkaline aqueous solution)
In, the n-type silicon is etched, but the p-type silicon is hardly etched. Therefore, it is desirable that both the spacers 63 and 64 be n-type for this etching. Finally, as shown in FIG. 17, a non-doped polycrystalline silicon film for the second sidewall spacer is coated to a thickness of 140 to 180 nm. Then, the polycrystalline silicon film is processed by the film thickness coated by anisotropic dry etching. As a result, the sidewall spacer 69 made of non-doped polycrystalline silicon can be formed on the sidewall of the gate electrode 55. At this time, the width of the sidewall spacer 69 was 140 to 180 nm. The subsequent steps are completed by the same steps as the first embodiment. Impurities were not introduced into the second sidewall spacer 69 in the subsequent steps as in the first embodiment. In the transistor formed as described above, the thickness of the silicon dioxide film below the second sidewall spacer 69 is finally 8 to 15 nm after the above steps, which is larger than the gate insulating film thickness. .. Here, the width of the second sidewall spacer 69 is preferably shorter than the width of the first sidewall spacers 63 and 64 shown in FIG. 15, and is about the diffusion end of the high concentration impurity layer 67 in the n channel. good. At this time, in the p-channel, the end of the high-concentration impurity layer 68 reaches the bottom of the second spacer. According to this embodiment, it is possible to obtain a transistor having the characteristics equal to or higher than those of the first embodiment in a self-aligned manner for the n, p channel MIS type field effect transistor and without increasing extra steps. In the above embodiment, the first
CV is used for the polycrystalline silicon for sidewall spacers of
At the time when the film is coated by the D method, a high concentration of n-type impurities is introduced. As the method of introducing impurities into this polycrystalline silicon, the same thermal diffusion method of phosphorus as the method of introducing into a normal gate electrode or the ion implantation method may be used. In any case, the amount of impurities introduced in advance must be sufficiently larger than the amount of impurities introduced for the high-concentration impurity layer of the p channel. In addition, M formed by the manufacturing method of the present embodiment
The IS type field effect transistor is used as a DRAM or SRA.
If it is applied to at least the peripheral circuit of the memory such as M, high speed operation becomes possible without any design change. It is even more suitable for high-speed logic such as a processor.

<Embodiment 7> Finally, a seventh embodiment of the present invention will be described with reference to FIG. This embodiment shows another embodiment of the MIS field effect transistor formed by the manufacturing method shown in the above embodiment. As the high resistance semiconductor film, the case where a non-doped polycrystalline silicon film is used as described above will be described. FIG. 18 shows MI
It is a typical top view of an S-type field effect transistor. In the MIS type field effect transistor formed by the manufacturing method shown in the first and second embodiments, the structure shown in FIG.
8A, sidewall spacers 72 made of non-doped polycrystalline silicon are formed all around the gate electrode 70. Therefore, the sidewall spacers on the source and drain sides are electrically connected with high resistance, and if the upper wiring layer or the contact electrode comes into contact with the spacer, a leak current flows between the source and the drain. On the other hand, in FIG. 18B, a part thereof is removed, and the sidewall spacer 73 is left only in the source / drain portion. According to this embodiment, since the sidewall spacers on the source and drain sides are electrically insulated, there is no problem even if the upper wiring layer or the contact electrode contacts the spacer. Therefore, the distance between the gate electrode and the contact hole can be shortened, and a self-aligned contact used in a highly integrated memory process is also possible.

[0024]

According to the present invention, the portion near the side wall of the gate electrode is a high dielectric constant material having a relative dielectric constant three times or more the dielectric constant of the gate insulating film. A large gate fringe electric field can be applied to the upper portion, and the electric field inside the element can be relaxed.

[Brief description of drawings]

FIG. 1 is a process chart showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process diagram showing a conventional known manufacturing method.

FIG. 3 is a process drawing showing another known manufacturing method.

FIG. 4 is a diagram showing an electric field relaxation effect by a semiconductor spacer.

FIG. 5 is a process drawing showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a process drawing showing the manufacturing method of the semiconductor device according to the third embodiment of the present invention.

FIG. 7 is a process drawing showing another manufacturing method of the semiconductor device of the third embodiment of the present invention.

FIG. 8 is a process drawing showing the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 9 is a process drawing showing another manufacturing method of the semiconductor device of the fourth embodiment of the present invention.

FIG. 10 is a process drawing showing another manufacturing method of the semiconductor device of the fourth embodiment of the present invention.

FIG. 11 is a sectional view of a structure of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 12 is a process drawing showing the manufacturing method of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 13 is a process drawing showing the manufacturing method of the semiconductor device of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 14 is a process drawing showing the manufacturing method of the semiconductor device of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 15 is a process drawing showing the manufacturing method of the semiconductor device of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 16 is a process drawing showing the manufacturing method of the semiconductor device of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 17 is a process drawing showing the method of manufacturing the semiconductor device of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 18 is a plan view of a semiconductor device of a semiconductor device according to a seventh embodiment of the present invention.

[Explanation of symbols]

1, 50 ... Silicon substrate, 2 ... Low concentration diffusion layer, 3, 32
... High-concentration diffusion layer, 4 ... Gate insulating film, 5, 27, 55 ...
Gate electrode, 6, 15, 18, 60 ... Silicon dioxide thin film on silicon substrate, 7, 13, 23, 25, 41 ... Silicon dioxide film, 8, 19, 26, 43, 46, 69 ...
Sidewall spacers made of non-doped polycrystalline silicon, 9, 10, 12, 17, 63, 64 ... Sidewall spacers made of polycrystalline silicon 11, 22, 2
8, 30 ... Silicon dioxide film, 14 ... Side wall spacer made of silicon nitride film, 16, 20, 21, 4
0, 61 ... Silicon nitride film.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Naotaka Hashimoto 1-280 Higashi Koikeku, Kokubunji, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Inventor Toshiaki Yamanaka 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Takashi Hashimoto 1-280, Higashi Koigokubo, Kokubunji, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Inventor Nagatoshi Oki 5-20-1, Kamimizumoto-cho, Kodaira-shi, Tokyo Super LSI Engineering Co., Ltd. (72) Inventor Hiroshi Ishida 5-20-1 Joumizuhoncho, Kodaira-shi, Tokyo Hirate Super LSI Engineering Co., Ltd.

Claims (24)

[Claims] 1. A drain region including a low-concentration impurity layer and a high-concentration impurity layer, a gate electrode formed on the low-concentration impurity layer via a gate insulating film, a sidewall of the gate electrode and the low-concentration layer. An MIS field effect transistor of LDD structure having a sidewall spacer formed on an impurity layer, wherein at least the sidewall of the gate electrode among the sidewall spacers in a device operating state after formation of the drain region. A semiconductor device characterized in that a portion in the vicinity thereof is a high dielectric constant material having a relative dielectric constant three times or more the dielectric constant of the gate insulating film. 2. The high dielectric constant material is a high resistance semiconductor having an impurity concentration of a predetermined concentration or less.
The semiconductor device described. 3. The semiconductor device according to claim 2, wherein the high resistance semiconductor is made of at least any of silicon, germanium and gallium arsenide. 4. A semiconductor device according to claim 3, further comprising an insulating film between the high resistance semiconductor and the gate electrode and the low concentration impurity layer. 5. The semiconductor device according to claim 4, wherein the thickness of the insulating film existing between the high resistance semiconductor and the low concentration impurity layer is thicker than the thickness of the gate insulating film. 6. A drain region comprising a low-concentration impurity layer and a high-concentration impurity layer, a gate electrode formed on the low-concentration impurity layer via a gate insulating film, a sidewall of the gate electrode and the low-concentration layer. A method of manufacturing an MIS field effect transistor having an LDD structure, which includes a sidewall spacer formed on an impurity layer, comprising: forming the low concentration impurity layer and the high concentration impurity layer as the drain region, A method of manufacturing a semiconductor device, comprising: forming a high dielectric constant material having a relative dielectric constant three times or more the dielectric constant of the gate insulating film in a portion near the sidewall of the gate electrode. 7. The high dielectric constant material is a high resistance semiconductor having an impurity concentration of a predetermined concentration or less.
A method of manufacturing a semiconductor device according to claim 1. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the high resistance semiconductor is made of at least any of silicon, germanium and gallium arsenide. 9. A step of forming a gate insulating film and a gate electrode of a MIS field effect transistor on a semiconductor substrate,
Then, a step of forming a low-concentration impurity region as a drain region by introducing an impurity into the semiconductor substrate using the gate electrode as a mask, and a step of forming a first sidewall spacer on a sidewall of the gate electrode thereafter. Forming a high concentration impurity region as the drain region by introducing an impurity into the semiconductor substrate using the gate electrode and the first sidewall spacer as a mask; and removing the first sidewall spacer. A semiconductor device comprising: a step of forming a high dielectric constant material having a relative dielectric constant three times or more the dielectric constant of the gate insulating film in a portion near the sidewall of the gate electrode. Production method. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the high dielectric constant material is a high resistance semiconductor having an impurity concentration of not more than a predetermined concentration. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the high resistance semiconductor is made of at least any of silicon, germanium and gallium arsenide. 12. The first sidewall spacer is a silicon nitride film, and the silicon nitride film as the first sidewall spacer is formed after the formation of the first sidewall spacer and before the removal thereof. 10. The method for manufacturing a semiconductor device according to claim 9, wherein an oxide film is selectively formed on the semiconductor substrate as a mask. 13. The first sidewall spacer is composed of a lower layer silicon nitride thin film and an upper layer polycrystalline silicon thick film, and after forming the high concentration impurity region as the drain region, the first sidewall spacer is formed. An upper polycrystalline silicon thick film of the first sidewall spacer is removed, and an oxide film is selectively formed on the semiconductor substrate using the lower silicon nitride thin film of the first sidewall spacer as a mask. A method of manufacturing a semiconductor device according to claim 9. 14. A base protection film is formed after the formation of the gate insulating film and the gate electrode and before the formation of the first sidewall spacer, and the high-concentration impurity region is formed as the drain region. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the first sidewall spacer is removed after the etching, and then the first sidewall spacer is removed. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the first sidewall spacer and the underlying protective film are polycrystalline silicon and a silicon nitride film, respectively. 16. The method of manufacturing a semiconductor device according to claim 14, wherein the first sidewall spacer and the underlying protective film are a silicon nitride film and polycrystalline silicon, respectively. 17. A step of forming a gate insulating film and a gate electrode of a MIS field effect transistor on a semiconductor substrate, and then introducing an impurity into the semiconductor substrate using the gate electrode as a mask to reduce a drain region. Forming a concentration impurity region, and thereafter forming a sidewall spacer made of a high dielectric constant material having a relative dielectric constant three times or more the dielectric constant of the gate insulating film on the side wall of the gate electrode; A step of selectively forming an impurity introduction mask film on the surface of the sidewall spacer; and a step of forming an impurity as a drain region by introducing an impurity into the semiconductor substrate using the gate electrode, the sidewall spacer and the impurity introduction mask film as a mask. And a step of forming a high-concentration impurity region. The method of manufacturing a semiconductor device, characterized in that the impurity for forming the high concentration impurity region is set to the side wall spacers as not substantially introduced thickness consisting of the high dielectric constant material. 18. The method of manufacturing a semiconductor device according to claim 17, wherein the high dielectric constant material is a high resistance semiconductor having an impurity concentration of not more than a predetermined concentration. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the high resistance semiconductor is made of at least any of silicon, germanium and gallium arsenide. 20. After forming the gate insulating film and the gate electrode, before forming the sidewall spacers, a base protective film is formed, and after forming the high concentration impurity region as the drain region, 18. The method of manufacturing a semiconductor device according to claim 17, wherein the sidewall spacers are removed, and then the sidewall spacers are removed. 21. The method of manufacturing a semiconductor device according to claim 20, wherein the sidewall spacer and the base protection film are polycrystalline silicon and a silicon nitride film, respectively. 22. A step of forming a gate insulating film, a gate electrode and an upper protective insulating film on the gate electrode of a MIS field effect transistor on a semiconductor substrate, and thereafter, forming the gate electrode and the upper protective insulating film. Forming a low-concentration impurity region as a drain region by introducing impurities into the semiconductor substrate used as a mask; and thereafter, forming a low dielectric constant 3 of the gate insulating film on the sidewall of the gate electrode and the sidewall of the upper protective insulating film. A step of forming a sidewall spacer made of a high dielectric constant material having a relative permittivity more than double, a step of selectively forming an impurity introduction mask film on the surface of the sidewall spacer, the gate electrode and the upper protection The impurities are introduced into the semiconductor substrate by using the insulating film, the sidewall spacers, and the impurity introduction mask film as a mask. And a step of forming a high-concentration impurity region as a rain region, wherein the film thickness of the upper protective insulating film is such that the impurities for forming the high-concentration impurity region are near the side wall of the gate electrode. A method of manufacturing a semiconductor device, wherein the thickness is set so as not to be substantially introduced into the sidewall spacer. 23. The method of manufacturing a semiconductor device according to claim 22, wherein the high dielectric constant material is a high resistance semiconductor having an impurity concentration of not more than a predetermined concentration. 24. The method of manufacturing a semiconductor device according to claim 23, wherein the high resistance semiconductor is made of at least any of silicon, germanium and gallium arsenide.