JPH0595113A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a MIS-type field effect transistor having high reliability and high current driving ability and is proper for high integration. CONSTITUTION:A source and a drain have an LDD structure, a sidewall spacer 6 is provided to an area near the sidewall of a gate electrode above a low concentration diffusion layer 2 thereof, a gate electrode bottom part protrudes and a gate electrode protruding part is buried inside a semiconductor substrate 1 in a self-alignment manner. Thereby, it is possible to bury an overlapping part of the low concentration diffusion layer 2 and a gate electrode 5 inside the silicon substrate 1 in a self-alignment manner and to realize a semiconductor device having high reliability and high current driving ability through the plane occupied area of a transistor is small. Furthermore, contact between the transistor and an upper wiring layer can be formed in a self-alignment manner and a plane occupied area of the transistor can be further reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to an insulated gate type (hereinafter abbreviated as MIS type) suitable for high reliability and high current driving capability and high integration.
The present invention relates to a semiconductor device having a field effect transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art To improve the reliability of a MIS field effect transistor, it is effective to relax the electric field inside the device by improving the drain structure. As a structure for improving the reliability of the conventional MIS field effect transistor, for example, Japanese Patent Laid-Open No. 54-44
Low concentration drain structure as discussed in No. 482, so-called LDD (Lightly Doped Drain) structure, or IEE, Electron, Device, Letters, No. 4, 1987, 151-153. (IEEE, Electron Device Letters, Vol.EDL-4, p
p. 151-153, 1987), an improved structure of the LDD structure described above is a structure in which the low-concentration drain and the gate electrode are sufficiently overlapped. Of these, the latter is shown in FIG. 1 is a silicon substrate, 2 is a low impurity concentration source / drain diffusion layer (hereinafter abbreviated as low concentration diffusion layer), 3 is a high impurity concentration source / drain diffusion layer (hereinafter abbreviated as high concentration diffusion layer), 4
Is a gate insulating film, 7 is a gate electrode with an overhang, and 8 is a sidewall spacer made of an insulating film.

[0003]

In the above-mentioned prior art, the former low-concentration diffusion layer 3 of the LDD structure relaxes the electric field inside the element and improves the reliability of long-term operation of the transistor, but is connected in series to the transistor. Functioning as a resistance, causing a decrease in current drive capability. Further, even with this LDD structure, when the gate length becomes 0.5 μm or less, it becomes difficult to use the conventional power supply voltage of 5V. On the other hand, the improved LDD structure as shown in FIG. 2 is expected to have higher reliability and higher current driving capability than the above LDD structure. LD
When the low-concentration diffusion layer of the D structure and the gate electrode are sufficiently overlapped, the electric field in the channel direction near the drain can be relaxed, and the injected hot carriers are trapped in the gate electrode without being trapped in the insulating film. L is injected
It is possible to prevent an inherent deterioration phenomenon in the DD structure (characteristic variation caused by hot carriers captured in the spacer). However, in this structure, the gate electrode 7a for overlapping is the original gate electrode 7a determined by lithography.
Since it projects from b, when the contact hole with the diffusion layer is formed in a self-aligned manner, or when the normal contact hole is shifted and opened on the spacer, the upper wiring is in contact with the projecting electrode 7b. was there. This will be described in more detail with reference to FIG. Figure 3
FIG. 3A is an enlarged sectional view showing only the vicinity of the drain of the known example shown in FIG. This drawing shows the case of an n channel, and further, a contact hole is opened so as to overlap with the sidewall spacer 8 and an upper wiring layer 17 made of polycrystalline silicon is formed. As is clear from this figure, the overhang 19 of the gate electrode and the wiring layer 17 are short-circuited at 18. Reference numeral 16 is an interlayer insulating film. Therefore, in the conventional technique, there is a problem that the occupied area of the transistor becomes large because a margin must be provided so that the end of the sidewall spacer and the contact hole do not come into contact with each other. Further, in this structure, since the low-concentration diffusion layer is arranged on the surface of the silicon substrate in a plane, it is difficult to reduce the occupied area in terms of ensuring reliability.

An object of the present invention is to form a basic device after a process of 0.3 μm by an easy process, and to have a high reliability and a high current driving capability without being restricted by the above-mentioned process.
An object is to provide an IS field effect transistor.

[0005]

In order to solve the above-mentioned problems, the source and drain have the above LDD structure, a sidewall spacer is provided near the side wall of the upper gate electrode of the low concentration diffusion layer, and the bottom of the gate electrode is projected. Further, it is further achieved that the gate electrode projecting portion is embedded in the semiconductor substrate in a self-aligned manner.

[0006]

In the above means, the protruding portion of the bottom portion of the gate electrode, that is, the overlapping portion with the so-called low-concentration diffusion layer is embedded in the silicon substrate, so that the upper wiring layer and the protruding portion can be prevented from directly contacting each other. .. This will be described in detail with reference to FIG. In the figure, 5 is a gate electrode, 6 is a sidewall spacer, and the others are the same as in FIG. From this figure, since the protruding portion of the gate electrode is embedded in the silicon substrate 1, it is sufficiently insulated from the upper wiring layer 17 by the sidewall spacer 6, and both are not short-circuited. In addition, the gate electrode 5
By embedding the overlap portion of the low concentration diffusion layer 2 with the silicon substrate 1, the overlap length can be three-dimensionally obtained in the depth direction.

[0007]

EXAMPLE A typical example of the present invention will be described below with reference to FIGS.
Will be explained. FIG. 1 shows a typical sectional structure when the present invention is applied to an n-channel MOS field effect transistor, and FIG. 4 shows an outline of a typical forming process for forming the structure. is there. In FIG. 1, the sidewall spacer 6 has a width of about 0.15 μm, the gate insulating film 4 is a silicon dioxide film of about 15 nm, and the surface impurity concentration of the n-type low concentration diffusion layer (impurity region) 2 is about 1 × 10 ^18.
It was / cm ³ . As a result, the overlap between the gate electrode and the low-concentration diffusion layer is about 0.1 μm formed in the depth direction in the silicon substrate, and the insulation with the upper wiring layer 18 is performed by the sidewall spacer 6 in a self-aligned manner. It is being appreciated.
As a result, as compared with the conventionally known LDD structure MOS field effect transistor, the hot carrier breakdown voltage (transfer conductance Gm is 10% in 10 years), which is an index of reliability.
The variable drain voltage) was improved by about 2V due to the rise of the gate fringe electric field and the reduction of the hot carrier deterioration phenomenon peculiar to LDD. Further, in this embodiment, the length of the low-concentration diffusion layer can be substantially reduced, and the current driving capability is about 10% as compared with the normal LDD structure.
Since the length of the planar low-concentration diffusion layer can be reduced, the area occupied by the transistor can be reduced.

Although the above is the embodiment for the n-channel, the same electric field relaxation effect can be obtained by reversing the conductivity type also in the p-channel. Further, the gate electrode material may be any of metal, a multi-layer film of metal and silicon, and the gate oxide film and the sidewall spacer material may be another high dielectric film. In particular,
Since the silicon oxide film thickness is approaching its thinning limit in the future, other high dielectric films (silicon nitride film, tantalum oxide film, etc.) may be used. At that time, the spacer material should also be a high dielectric film. The better the characteristics, the better. Further, the high concentration diffusion layer 3 may reach the embedded gate electrode portion. In this case, the current drive capacity is further improved.

Next, a typical process for forming the first embodiment will be described with reference to FIG.

In FIG. 4A, after forming an element isolation region on a p-type 10 Ω-cm silicon substrate 1, a silicon nitride film 10 is formed on the entire surface by a known chemical vapor deposition (CVD) method.
After coating the film with a thickness of 0 to 350 nm and forming a groove 11 having a width of 300 to 350 nm by using a known lithography technique, the silicon substrate is subsequently subjected to isotropic dry etching to a depth of about 0.1 μm.
Processed and further gate insulating film 4 made of silicon dioxide
3 is a cross-sectional view after forming 10 to 13 nm by thermal oxidation. As shown in the figure, the silicon substrate is also laterally etched by about 0.1 μm.

Next, as shown in FIG. 4 (b), a polycrystalline silicon film (about 400 to 500 nm) and etch back are applied to
Polycrystalline silicon is embedded in the groove 11 formed in the silicon nitride film and the silicon substrate. Subsequently, phosphorus is diffused into this polycrystalline silicon at a high concentration to form an electrode. As a result, the gate electrode has an inverted T shape in which the protruding portion at the bottom is embedded in the silicon substrate.

Next, as shown in FIG. 4C, the silicon nitride film 10 is formed.
After removing, the thin film 12 made of silicon dioxide is added to the thin film 5-10.
to form a low-concentration diffusion layer 2 by ion-implanting phosphorus with 1 to 2 × 10 ¹³ / cm ² and then performing heat treatment in a nitrogen atmosphere.

Finally, as shown in FIG.
The side wall spacers 6 are formed by a silicon dioxide film having a thickness of nm and anisotropic dry etching corresponding to the film thickness. At this time, the width of the sidewall spacer 6 is 130.
Was ~ 150 nm. Then, a high concentration diffusion layer 3 is formed by ion implantation of arsenic of ^{2 to} 5 × 10 ¹⁵ / cm ² and subsequent heat treatment. The subsequent steps are completed by forming a film of an interlayer insulating film, opening of contact holes, and a metal wiring layer by a known method.

As described above, a gate / drain overlap LDD structure having a buried inverted T-shaped gate electrode could be formed in a self-aligning manner similar to the conventional LDD structure forming process. As a result, the same effect as that of the first embodiment could be obtained.

Further, in the above embodiment, the minimum value of the groove width 11 is usually determined by the resolution limit of lithography. Therefore, the width is about 0.
It is difficult to form a groove of 3 μm or less. At this time, as shown in FIG. 4E, in the processing of the silicon nitride film 10 in FIG. 4A, another mask layer 13 such as a resist of 0.5 to 1 μm or a silicon dioxide film 130 to is previously formed on the silicon nitride film. A 150 nm film and a groove are formed by processing, and then a sidewall 14 is formed on the side wall of the resist on the silicon nitride film by a film of a silicon dioxide film and anisotropic dry etching corresponding to the film thickness. And (a)
Similarly, the silicon nitride film is processed using 13 and 14 as a mask. Thus, by controlling the width of the sidewall spacers 14, it is possible to form a groove having an arbitrary width equal to or smaller than the resolution limit of lithography.

Further, in the case where an insulating film such as a silicon dioxide film is formed only on the gate electrode of the present invention, before removing the silicon nitride film 10 on the silicon substrate, FIG.
As described above, it may be formed by etching back with the film of the silicon dioxide film. Also, when a metal or metal silicide is formed on the gate electrode made of polycrystalline silicon, it can be formed by the same process. As a result, if the film above the gate electrode is a silicon dioxide film, the contact holes can be opened in a self-aligned manner when the upper wiring layer is formed after FIG. If the film on the gate electrode is made of metal or metal silicide, a low resistance gate electrode can be realized.

Next, another embodiment of the present invention will be described with reference to FIG.

First, FIG. 5 (a) shows that the size of the protruding portion of the bottom portion of the gate electrode is changed in the above embodiment.
In FIG. 4A, after the silicon substrate is exposed, the silicon substrate is first processed by anisotropic dry etching to a depth of about 0.2 μm, and then isotropically etched to about 0.1 μm. As a result, a groove as shown in FIG. 5 (a) is formed. The subsequent steps are completed by the same steps as in the above embodiment. In this embodiment, the low-concentration diffusion layer 21 is formed deeper in the silicon substrate 1 than in the above-mentioned embodiments, the overlapping portion with the gate electrode 20 is increased, and the low-concentration diffusion layer 21 is formed more than the high-concentration diffusion layer 3. Is also deeply formed. As a result, the length of the overlapping portion of the gate electrode 20 and the low-concentration diffusion layer 21 can be lengthened only in the depth direction in a self-aligned manner, so that the area occupied by the transistor is not increased and the reliability is further increased. A high transistor can be obtained. Then, the junction capacitance between the source / drain and the silicon substrate can be reduced.

Next, FIG. 5 (b) shows the high-concentration diffusion layer 22 reaching the lower part of the gate electrode in the above embodiment. This is formed by oblique ion implantation of impurities for the high-concentration diffusion layer in FIG. 4 (d).
As a result, the high-concentration diffusion layer 22 can be extended in the lateral direction as compared with the depth direction, so that the junction depth can be made shallower than that in the low-concentration diffusion layer 2 as in the above embodiment. As a result, the junction capacitance can be reduced and the current drive capability can be significantly improved. In the present invention, the high concentration diffusion layer may or may not reach the lower portion of the gate electrode. This may be determined in consideration of the reliability and the power supply voltage used.

Next, FIG. 5C shows that the sidewall spacer material is changed from the silicon dioxide film to the tantalum oxide film 23 which is a high dielectric film in the above-mentioned embodiment.
As a result, the fringe electric field from the gate electrode can be increased and the current drive capability can be greatly improved without the high-concentration diffusion layer 3 reaching the lower part of the gate electrode.

Finally, FIG. 5 (d) shows the high-concentration buried layer 24 for a punch-through stopper formed only in the deep portion of the silicon substrate below the gate electrode in the above embodiment. This is formed by exposing the silicon substrate 1 in FIG. 4A and then by ion implantation with high energy using the silicon nitride film 10 as a mask. As a result, the high-concentration buried layer 24 for punch-through stopper can be formed only under the gate electrode, so that a fine transistor can be formed without increasing the junction capacitance. As described above, the structure of the present invention is a MIS having high reliability, high current drive capability, and high integration even after the level of 0.2 μm by combining these embodiments.
Type semiconductor device can be formed. This is a semiconductor device suitable not only for logic but also for memory cells such as general-purpose memories.

[0022]

According to the present invention, the overlapping portion of the low-concentration diffusion layer and the gate electrode can be embedded in the silicon substrate in a self-aligned manner, and the length of the overlapping portion can be earned three-dimensionally. It is possible to realize a semiconductor device having high reliability and high current drive capability even if the area occupied by the plane is small. Further, the contact between the transistor and the upper wiring layer can be easily formed in a self-aligning manner, and the margin between the contact hole and the gate electrode can be minimized, so that the planar occupied area of the transistor can be further reduced. For this reason,
Even at a level of 0.3 μm or less, it is possible to obtain a semiconductor device which can be formed by a simple process and can be highly integrated.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a representative embodiment of the present invention.

FIG. 2 is a sectional view of a conventionally known example.

FIG. 3 is a diagram showing a problem of a conventionally known example and an operation of the present invention.

FIG. 4 is a process drawing for forming a representative embodiment of the present invention.

FIG. 5 is a sectional view of another embodiment of the present invention.

[Explanation of symbols]

1 ... Silicon substrate, 2, 21 ... Low concentration diffusion layer, 3, 22
... high-concentration diffusion layer, 4 ... gate insulating film, 5,7,20 ... gate electrode, 6,8,14 ... sidewall spacers made of silicon dioxide, 10 ... silicon nitride film, 11 ... opening portion of silicon nitride film, 12 ... Silicon dioxide film, 13
... resist, 15 ... metal silicide film, 16 ... interlayer insulating film, 17 ... upper wiring layer made of polycrystalline silicon, 23 ...
Sidewall spacers made of tantalum oxide film, 24
… High-concentration buried layer.

Front page continuation (72) Inventor Toshiaki Yamanaka 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Naotaka Hashimoto 1-280, Higashi Koikeku, Tokyo Kokubunji City Inside Hitachi Research Laboratory (72) Inventor Takashi Hashimoto 1-280 Higashi Koigokubo, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Inventor Nagatoshi Oki 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo SII Engineering Co., Ltd. (72) Inventor Hiroshi Ishida 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hirate Super LSI Engineering Co., Ltd.

Claims (7)

[Claims] 1. A semiconductor device having an insulated gate field effect transistor having a source region and a drain region provided on a semiconductor substrate, a channel formed between the source region and the drain region, and a gate electrode exerting a field effect on the channel. A semiconductor device, wherein the bottom portion of the gate electrode has a projecting shape, and the projecting portion of the bottom portion of the gate electrode is embedded in the semiconductor substrate. 2. At least one of a source and a drain of the semiconductor device has a high-concentration impurity region distant from a gate electrode and a low-concentration impurity region which is in contact with the high-concentration impurity region and extends immediately below the gate electrode. Claim 1 characterized by the above-mentioned.
The semiconductor device described. 3. An insulating film on the side wall of the gate electrode of the semiconductor device so as to cover the upper portion of the protruding portion of the gate electrode, or
The semiconductor device according to claim 2, further comprising a sidewall spacer made of a high dielectric constant insulating film or a high resistance semiconductor film. 4. The semiconductor device according to claim 1, wherein the length of the protruding portion of the gate electrode of the semiconductor device is longer in the depth direction of the semiconductor substrate than in the channel direction of the transistor. 5. A method of forming a semiconductor device having an insulated gate field effect transistor, comprising the steps of forming an element isolation region and then coating an oxidation resistant film on the semiconductor substrate, followed by the oxidation resistance. A step of opening a portion to be a gate electrode in the film, a step of subsequently forming a groove in the semiconductor substrate which is larger than the opening in a plane, and a step of subsequently forming a gate insulating film on the groove surface, Next, a step of burying a conductive film in the groove is provided.
A method of manufacturing a semiconductor device according to claim 1. 6. A method of forming a groove larger in plan view than the opening in the semiconductor substrate, wherein anisotropic etching is followed by isotropic etching. 5. The method for manufacturing a semiconductor device according to 5. 7. The method for forming a semiconductor device having the insulated gate field effect transistor, comprising the step of forming a sidewall spacer on a side wall of the gate electrode after forming the gate electrode. A method for manufacturing a semiconductor device as described above.