JPS62249475A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the threshold of a parasitic MISFET and reduce the power consumption of an SRAM by a method wherein the difference between the diffusion speed of 1st conductivity type impurity and the diffusion speed of 2nd conductivity type impurity is utilized and 2nd conductivity type semiconductor region is formed between a high resistance load element and wirings in self-aligning manner. CONSTITUTION:Polycrystalline silicon films are formed on forming regions of a high resistance load element 13B, a source voltage wiring 13A and a wiring 13D and a mask 17 for impurity introduction is formed on the polycrystalline silicon film of the high resistance load element 13B forming region. After that, n-type impurity and p-type impurity which has higher diffusion speed than the n-type impurity are introduced into the polycrystalline silicon film of the source voltage wiring 13A forming region and into the polycrystalline film of the wiring 13D forming region to form the respective wirings. With this constitution, by utilizing the difference between the diffusion speed of the n-type impurity and the diffusion speed of the p-type impurity, a p-type semiconductor region 13C is formed between the source voltage wiring 13A or the wiring 13D and the high resistance load element 13B in a self-aligning manner. In other words, the p-type semiconductor region l3C can be formed so as to be self-aligned with the source voltage wiring 13A, the wiring 13D and the high resistance load element 13B respectively.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit device (hereinafter referred to as SRAM) equipped with a static random access memory. It's about technology.

[Conventional technology]

The memory cell of SRAM has a high resistance load element and a driving M
A flip-flop circuit consisting of an IS FET and a transfer MISF connected to its pair of input/output terminals.
It is composed of ET. The high-resistance load element is made of a polycrystalline silicon film formed integrally with the power supply voltage wiring, and is formed in the upper layer of the N-current MISFET. A high-resistance load element configured in this manner can reduce the memory cell area and increase the integration of the SRAM.

Polycrystalline silicon films used as high resistance load elements are
In order to have a high resistance value, it is constructed without introducing n-type impurities (As or P) that reduce the resistance value. The polycrystalline silicon film used as the wiring for the power supply voltage is constructed by introducing the impurities mentioned above.
No. 30461.

[Problem that the invention seeks to solve]

The inventor of the present invention conducted experiments and studies regarding the electrical characteristics of the above-mentioned SRAM, and as a result, discovered that the following problems occurred.

The memory cell has a multilayer wiring structure to reduce its area, and is configured such that a data line extends above a high-resistance load element through an insulating film.

In a memory cell having such a structure, a parasitic MI S FET having a high resistance load element as a channel formation region is configured. In other words, the parasitic MISFET is configured such that the data line is the gate electrode, the power supply voltage wiring connected to both ends of the high resistance load element is the drain region, and the drain region of the driving MISFET is the source region. . Therefore, a channel is formed in the high resistance load element under the influence of the electric field effect from the data line, and i! Since the amount of current flowing from the 1lfl voltage wiring fluctuates (increases) significantly, power consumption increases.

An object of the present invention is to provide a technology that can reduce the power consumption of an SRAM configured with memory cells having high resistance load elements.

Another object of the present invention is to provide a technique capable of reducing the memory cell area and improving the degree of integration of SRAM.

Another object of the present invention is to provide a technology that can reduce the number of SRAM manufacturing steps.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In an SRAM comprising a memory cell having a high-resistance load element whose end portion is connected to a wiring, a conductive layer whose resistance value can be controlled by introducing impurities into the high-resistance load element and wiring formation region is formed, After forming an impurity introduction mask on the conductive layer in the high resistance load element formation region, using this impurity introduction mask, a first conductivity type impurity for forming a wiring and a first A second conductivity type impurity having a faster diffusion rate than the conductivity type impurity is introduced.

[For production]

According to the above-described means, the first conductivity type impurity and the second conductivity type impurity
A 21st power-squeezing type semiconductor region can be formed between the high resistance load element and the wiring by self-alignment by utilizing the difference in diffusion rate with the conductive type impurity.

Therefore, it is possible to improve the threshold voltage of a parasitic MISFET that uses a high resistance load element as a channel formation region, so that the amount of current flowing through the high resistance load element fluctuates (increases).
It is possible to prevent this and reduce the power consumption of the SRAM.

Further, the extension of the depletion region formed from the wiring to the high resistance load element side can be reduced, and punch-through can be prevented. In addition, since the semiconductor region of the second conductivity type can be formed in self-alignment with each of the high-resistance negative simple element and the wiring, ? The margin area for mask alignment in the two-manufacturing process can be reduced. In other words,
These can reduce the high resistance load element and thus the memory cell area and improve the degree of integration of the SRAM.

Furthermore, since the second conductivity type semiconductor region can be formed using a mask for impurity introduction that forms high resistance load elements and wiring, the number of mask forming steps in the manufacturing process can be reduced.

The configuration of the present invention will be described below along with an embodiment in which the present invention is applied to an SRAM.

It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

〔Example〕

FIG. 1 (equivalent circuit diagram) shows a memory cell of an SRAM which is an embodiment of the present invention.

The memory cell of SRAM is as shown in FIG.

A pair of data lines DL are provided at intersections between DL and word line WL.

The memory cell is composed of a flip-flop circuit having a pair of input/output terminals, and transfer MI 5FETs Qs + and Qs2 connected to the word line WL and the data line DC. The flip-flop circuit includes two high resistance load elements R1, R2 and two driving MI 5FETQ
+, Q2.

The high resistance load element R has one end connected to the power supply voltage wiring Vcc, and the other end connected to the train region of the driving MI S FETQ. The source region of the driving MISFETQ is connected to the reference voltage wiring Vss.

The power supply voltage wiring Vcc is 1, for example, the operating voltage of one circuit 5[
v] is applied and the group l! The s voltage wiring ■ss is configured such that, for example, a circuit ground voltage of 0 [V] is applied thereto.

Next, a specific configuration of this embodiment will be explained.

A memory cell of an SRAM which is an embodiment of the present invention is shown in FIG. 2 (plan view), and FIG. 3 shows a cross section taken along the line 2--2 in FIG. Note that in FIG. 2 and FIG. 4, which will be described later, insulating films other than the field insulating film provided between each conductive layer are not shown in order to make the structure of this embodiment easier to understand.

In FIGS. 2 and 3, 1 is an n-type semiconductor substrate made of single crystal silicon, and 2 is a p-type well region. 3 is a field insulating film, and 4 is a p-type channel stopper region. Field insulating film 3 and channel stopper region 4 are provided on the main surface of well region 2 and are configured to electrically isolate semiconductor elements.

M I S F ETQt constituting the memory cell,
Q2.

Q S I+ Q S 2 is composed of a well region 2, a gate insulating film 5, a gate electrode 7, a pair of n-type semiconductor regions 8, and a pair of n9-type semiconductor regions lo.

The gate electrode 7 is made of a polycrystalline silicon film and a high melting point metal silicide (MoSi□) provided thereon.

TaSi2. It is composed of a composite film (polycide film) consisting of TiSi2, WSi2) films. Impurities (As, P) are introduced into the polycrystalline silicon film to reduce the resistance value. The gate electrode 7 is made of a single layer of high melting point metal (Mo
, Ta, Ti, W) film, a high melting point metal silicide film, or a composite film in which a high melting point all-reflective film is provided on a polycrystalline silicon film.

In addition, a word line (W) is made of the same conductive material as the gate electrode 7.
L) 7A and reference voltage wiring (Vss) 7B are configured. An extended portion of the gate electrode 7 and the reference voltage wiring 7B are electrically connected to a predetermined semiconductor region 10 through a contact hole 6 provided in the gate insulation film 5, so-called direct contact.

Highly doped semiconductor region 10 is used as a source or drain region. The semiconductor region 10 is.

Gate electric t! It is configured with an impurity introducing mask (side wall) 9 provided on the side of the mask 7.

The low concentration semiconductor region 8 is M I S F E T Q
s.

It is provided between the Q channel forming region (well region 2) and the highly doped semiconductor region 10. The semiconductor region 8 is
Tokoro II? L D D (Lightly Doped
A MISFET with a drain) structure is configured.

An interlayer insulating film 11 is provided on the MISFET Q, Qs to cover them. A connection hole 1 is formed in the interlayer insulation 11111 above the predetermined semiconductor region 10.
2 is provided.

The high resistance load elements (R1, R203B) are constructed as shown in FIGS. 2, 3, and 4 (plan views of memory cells).

One end of the high resistance load element 13B is a p-type semiconductor region 1.
It is connected to a power supply voltage wiring (Vcc) 13A extending over one interlayer insulating film 11 through 3C. The other end of the high resistance load element 1313 is connected to one end of a wiring 13D extending on the interlayer insulating film 11 via a p-type semiconductor region 13C. The other end of the wiring 13D is connected to the connection hole 1
2 through M I S FETQs + , the semiconductor region 10 of QS2 and M T S FETQ+ , the gate t1tt of Q2! 7 and is electrically connected.

The power supply voltage wiring 13A, high resistance load element 13B, p
Each of the semiconductor region 13C and the wiring 13D is made of a conductive layer, for example, a polycrystalline silicon film, the resistance of which can be controlled by introducing impurities.

Each of the power supply voltage wiring 13A and the wiring 13D is composed of a polycrystalline silicon pupil (,) into which an n-type impurity (ΔS or P) is introduced to reduce the resistance I hole value.

The n-type impurity is, for example, tols~1016[a
It is composed of a concentration of about t, oms/am21.

The high-resistance load element 13B is made of so-called non-doped polycrystalline silicon in which the impurities that reduce the resistance value are not introduced.
It consists of (1). The high-resistance load element 13B is configured within a region (indicating the pattern of the impurity introduction mask 17) surrounded by a dotted line labeled 13B in FIGS. 2 and 4.

The p-type semiconductor region 13G is made of a polycrystalline silicon film (P) into which a p-type impurity (for example, boron fluoride: BF2 or boron: B) is introduced. This p-type impurity is the power supply voltage wiring 13Δ.

Compared to the n-type impurity introduced into each of the wirings 130,
The rate of spread is increasing. The n-type semiconductor region 13C is, for example, 10'''-10'''
s/cLI+2].

In this way, the power supply voltage wiring 13A, the p-type semiconductor region 13C1, the high resistance load element 13B, the p-type semiconductor region 13
C, and the wiring 13D are n-p in the direction in which the ffi flow flows.
-4-pn type.

14 is power supply voltage wiring 13A, high resistance load element 13T3
An interlayer insulating film 15 covering the semiconductor region 10 of the M I S FET Qs is a contact hole formed by removing the insulating layer 11° 14 above the semiconductor region 10 of the MI S FETQs.

Reference numeral 16 denotes data lines DL, DL, which are electrically connected to the semiconductor region 10 of the MISFETQs through the connection hole 15 and configured to extend over the upper part of the interlayer insulation [14]. The data line 16 is connected to the aluminum film 5
It is composed of an aluminum film or the like containing predetermined additives (Si, Cu).

In this way, by providing the n-type f conductor region 13C between the power supply voltage wiring 13A or the wiring m13D and the high resistance load element (R+, R2) 13B, the high resistance negative 6
Parasitic MISF with jr element 13B as channel formation region
The threshold voltage of ET can be improved. Therefore, since it is possible to prevent the amount of current flowing through the high resistance load element 13B from changing (increasing) due to the electric field effect, SRΔ
The power consumption of M can be reduced. The parasitic MIS
The FET is configured such that the gate insulating film is interlayer insulation [14], the gate electrode is data a16, the power supply voltage wiring 13A is a train region, and the wiring 13D is a source region. The threshold voltage is a voltage applied to the data line 16 which is the gate electrode of the parasitic MISFE'r (for example, 0 to 5
V]). Under the above-mentioned voltage conditions, a channel is formed in the high resistance load element 13B on the W13A side (drain region side) of the FET, power supply II wiring, and the W13A side (drain region side).
The n-type semiconductor region 13 provided on the wiring 13D side (source region side) contributes to a substantial improvement in the threshold voltage.

In other words, it is desirable that the n-type semiconductor region 13C be provided on the side that controls the threshold voltage between the wiring 13D and the high resistance load element 13B.

Further, an n-type semiconductor region 13Cfy:! is located on the source region side of the parasitic MI S FET. 2, it is possible to reduce the extension of the depletion region from the pn junction between the power supply voltage wiring 13A and the high resistance load element 13B, that is, from the train region side of the parasitic MI S FET.
Punch-through between A and the wiring 13D (between the drain and source regions) can be prevented. Therefore, the n-type semiconductor region vi, 13C can reduce the area of the high-resistance load element 13B and reduce the memory cell area.
The degree of integration of RAM can be improved. Parasitic MISF
The n-type semiconductor region 13C on the drain region side of the ET can prevent punch-through, but lowers the breakdown voltage. However, the n-type semiconductor region 13C on the drain region side has minute dimensions approximately determined by the difference in diffusion speed between the n-type impurity and the p-type impurity, and exists in the depletion region. There is virtually no effect on each of , pass through, and breakdown voltage.

Next, the manufacturing method of this embodiment will be briefly explained using FIGS. 5 to 9 (cross-sectional views of the memory cell in each manufacturing process).

First, an n-type semiconductor made of single-crystal silicon is prepared.
Then, a part of the well region 2 is formed.

Thereafter, a field insulating film 3 and an n-type channel stopper region 4 are formed on the main surface of the well region 2 between the semiconductor element forming regions.

Then, as shown in FIG. 5, a gate insulating film 5 is formed on the main surface of the well region 2 in the semiconductor element formation region.

After the step of forming the gate insulating film 5 shown in FIG. 5, a predetermined portion of the gate insulating film 5 is removed and a connection hole 6 for direct contact is formed.

After that, a gate electrode 7 is formed on a predetermined upper part of the gate insulating film 5, and a word line 7A and a reference voltage wiring 7B are formed.
form. Each of the gate electrode 7, the word line 7Δ, and the reference voltage wiring 7B is formed of, for example, a polycide film in which a high melting point metal silicide film 7b is formed on a polycrystalline silicon film 7a. The polycrystalline silicon film 7a is made of, for example, C.
Formed with VD 1. It is formed by diffusing a predetermined impurity (for example, p). Although not marked, polycrystalline silicon film 7a
The impurities diffused into the well region 2 through the connection hole 6
to form an n-type semiconductor region used as part of a source region or a train region. The high melting point metal silicide film 7b is formed by sputtering, for example.

Then, as shown in FIG. 6, an n-type semiconductor region 8 for forming an LDD structure is formed on the main surface of the well region 2 on the side of the gate electrode 7. The semiconductor region 8 is mainly formed by introducing an n-type impurity (for example, P) by ion implantation using the gate electrode 7 and the field insulating film 3 as a mask for impurity introduction.

After the step of forming the semiconductor region 8 shown in FIG. 6, an impurity introduction mask 9 is formed on the side of the gate electrode 7. The impurity introduction mask 9 can be formed, for example, by subjecting a silicon oxide film formed by CvD to anisotropic etching such as reactive ion etching.

Thereafter, as shown in FIG. 7, an n-type semiconductor region 1o to be used as a source region or a drain region is placed on the main surface of the well region 2 on the side of the gate electrode 7 with the impurity introduction mask 9 interposed therebetween. form.

The semiconductor region 10 is doped with, for example, an n-type impurity (eg.

It can be formed by introducing As) by ion implantation.

After the step of forming the semiconductor region @, 1o shown in FIG.
An interlayer insulating film 11 is formed, and a predetermined portion of the interlayer insulating film 11 is formed.
is removed to form the connection hole 12.

After this, a conductive layer for forming power supply voltage wiring, high resistance load elements, etc. is formed on the entire surface of the interlayer insulating film ll. This conductive layer is formed of a polycrystalline silicon film having a thickness of, for example, 2000 to 3000[lambda], whose resistance value can be controlled by introducing impurities.

Then, an impurity introduction mask 17 is formed on the conductive layer in the high-resistance load element formation region (inside the area surrounded by reference numeral 13B in FIGS. 1 and 4). The impurity introduction mask 17 is formed of, for example, a photoresist film.

Thereafter, using the impurity introduction mask 17, as shown in FIG. 8, a p-type impurity (for example) is applied to the conductive layer in the other '1M1jli pressure wiring and the wiring formation region.

BF2) and rt-type impurities (for example, As) are sequentially introduced. This introduction is performed by ion implantation or thermal diffusion. By introducing this impurity, as shown in FIG. 8, a high resistance load element (R+,
R2) 13B is formed, and a power supply voltage wiring 13A and a wiring 13D are formed using n-type impurities, and furthermore, a p-type conductor region 13C is formed using p-type impurities. Each of the power supply voltage wiring 13A and the wiring 13D is
It is formed in self-alignment with respect to the impurity introduction mask 17. Similarly, the p-type semiconductor region 13G is self-aligned with respect to the impurity introduction mask 17 by utilizing the fact that the diffusion rate of p-type impurities in the polycrystalline silicon film is faster than that of n-type impurities. It is formed.

Thereafter, the impurity introduction mask 17 is removed and the conductive layer is patterned in a predetermined manner, thereby forming the power supply voltage wiring 13A, the high resistance wiring 13D, and the high resistance wiring 13D, as shown in FIGS. Load element 13B, p-type conductor region 1
Be able to form each of the 3C's.

In this way, the high resistance load element 13B, the power supply ffl
After forming a polycrystalline silicon film in the voltage wiring 13A and wiring 13D formation regions and forming an impurity introduction mask 17 on the polycrystalline silicon film in the high resistance load element 13B formation region, using this impurity introduction mask 17, In the polycrystalline silicon film of the power supply voltage wiring 13A and wiring 13D formation region,
The difference in diffusion rate between the n-type impurity and the p-type impurity is utilized by introducing an n-type impurity that forms each and a p-type impurity whose diffusion rate is faster than that of the n-type impurity.

A p-type semiconductor region 17 can be formed between the power supply voltage wiring 13A or the wiring 13D and the high resistance load element 13B by self-alignment. That is, since the p-type semiconductor region 13C can be formed in self-alignment with each of the power supply voltage wiring 13A, the wiring 13D, and the high resistance load element 13B, the margin area for mask alignment in the manufacturing process can be reduced. Therefore, since the area of the p-type semiconductor region 13C can be reduced, the area of the memory cell can be reduced.

The degree of integration of S, RAM can be further improved.

Further, the p-type t conductor region 13c is connected to the high resistance load element 13.
B. Since the power supply voltage wiring 13A and the wiring 13D can be formed using the impurity introduction mask 17, the number of mask forming steps in the manufacturing process can be reduced.

Further, in the present invention, the impurity introduction mask 17 can be formed of a film that can withstand heat treatment, such as a silicon oxide film or silicon nitride. This impurity introduction mask can sequentially introduce p-type impurities and n-type impurities and then stretch and diffuse each impurity, so it is possible to control the dimensions of the p-type semiconductor region 13C and to activate the impurities. can be easily converted into

After the steps of forming the power supply voltage wiring 13A, the wiring 13D, the high resistance load element 13B, and the p-type semiconductor region 13C shown in FIG. 9, the interlayer insulating film 14 and the connection hole 15 are sequentially formed. Then, as shown in FIGS. 2 and 3, the M T S F E T Q s is passed through the connection hole 15.
A data line 16 is formed on the interlayer insulating film 14 so as to be electrically connected to one of the semiconductor regions 10 .

By performing these series of manufacturing steps, one S
RAM is completed. Note that a protective film such as a passivation film may be formed after this.

Although the invention made by the present inventor has been specifically explained based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments (although various modifications may be made without departing from the gist thereof). Of course you can get it.

For example, in the present invention, the p-type semiconductor region 13C may be provided only between the high resistance load element 13B and the wiring 13D.

Furthermore, the present invention is not limited to SRAMs, but can be applied particularly to resistive elements that require miniaturization.

[Effects of the Invention] Among the inventions disclosed in this application, the effects that can be obtained by typical inventions are briefly described below.

In an SRAM configured of memory cells having high resistance load elements whose respective ends are connected to wiring, forming a conductive layer whose resistance value can be controlled by introducing impurities into the high resistance load element and wiring formation region, After forming an impurity introduction mask on the conductive layer in the high resistance load element formation region, using this impurity introduction mask, a first conductivity type impurity for forming a wiring and a first By introducing impurities of the second conductivity type, which have a faster diffusion rate than the impurities of the conductivity type, the difference in diffusion rate between the impurities of the first conductivity type and the impurities of the second conductivity type can be used to create a high resistance load element. A second conductivity type semiconductor region that can reduce power consumption through self-alignment with the wiring can be formed.

Reduce the mask alignment margin area in the manufacturing process and improve SRA
The degree of integration of M can be improved.

Furthermore, since the second conductivity type semiconductor region can be formed using a mask for introducing impurities that forms high resistance load elements and wiring, the number of mask forming steps in the manufacturing process can be reduced.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram showing a memory cell of SRA11, which is an embodiment of the present invention. FIG. 2 is a plan view showing an SRAM memory cell according to an embodiment of the present invention, FIG. 3 is a sectional view taken along the line ■-■ in FIG. 2, and FIG. FIG. 3 is a plan view of the memory cell shown in FIG. 2 in a predetermined manufacturing process. FIG. 5 to FIG. 9 show an SRAM which is an embodiment of the present invention.
FIG. 3 is a cross-sectional view of each memory cell in each mounting process. In the figure, 2... Well region, 5... Gate insulating film, 7
...Gate electrode, 7A...Word line (WL), 713
゜Vss...Base 4 voltage wiring, 8,1o...Semiconductor region.

Claims (1)

[Claims] 1. Equipped with a memory function composed of a memory cell having a high resistance load element, one end of which is connected to a power supply voltage wiring and the other end of which is connected to a MISFET via a wiring. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a conductive layer whose resistance value can be controlled by introducing impurities to form the wiring, power supply voltage wiring and high resistance load element, and the high resistance load element. a step of forming an impurity introduction mask on the conductive layer in the formation region; and a first step of forming wiring and power supply voltage wiring on the conductive layer in the wiring and power supply voltage wiring formation region using the impurity introduction mask. 1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: introducing a conductivity type impurity and a second conductivity type impurity having a faster diffusion rate than the first conductivity type impurity. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of forming the conductive layer is a step of forming a polycrystalline silicon film into which no impurities are introduced. 3. The step of introducing the impurity of the first conductivity type is a step of introducing As or P, and the step of introducing the impurity of the second conductivity type is a step of introducing BF_2 or B. A method for manufacturing a semiconductor integrated circuit device according to claim 1. 4. The semiconductor integrated circuit device according to claim 1, wherein the step of forming the impurity introduction mask is a step of forming a photoresist film, a silicon oxide film, or a silicon nitride film. Production method. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the memory cell is a memory cell of a static random access memory.