JPS63316453A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63316453A JPS63316453A JP15256387A JP15256387A JPS63316453A JP S63316453 A JPS63316453 A JP S63316453A JP 15256387 A JP15256387 A JP 15256387A JP 15256387 A JP15256387 A JP 15256387A JP S63316453 A JPS63316453 A JP S63316453A
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- semiconductor
- layer
- saturated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000009792 diffusion process Methods 0.000 abstract description 18
- 229920006395 saturated elastomer Polymers 0.000 abstract description 18
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract description 3
- 230000003321 amplification Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 2
- 238000009933 burial Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- NBJBFKVCPBJQMR-APKOLTMOSA-N nff 1 Chemical compound C([C@H](NC(=O)[C@H](CCC(N)=O)NC(=O)[C@H](CCC(N)=O)NC(=O)[C@@H]1CCCN1C(=O)[C@H](CCCCN)NC(=O)[C@@H]1CCCN1C(=O)CC=1C2=CC=C(C=C2OC(=O)C=1)OC)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)NCC(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CCCCNC=1C(=CC(=CC=1)[N+]([O-])=O)[N+]([O-])=O)C(=O)NCC(O)=O)C1=CC=CC=C1 NBJBFKVCPBJQMR-APKOLTMOSA-N 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔虚業上の利用分野〕
本発明に半導体装置に係り、特に同一エピタキシャル領
域に共存させた素子のいず庇かが回路動作上飽和した場
合の絶縁構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a semiconductor device, and more particularly to an insulation structure when any of the elements coexisting in the same epitaxial region is saturated in terms of circuit operation.
従来、同一半導体基板上で回路動作上飽和する素子に1
個々に単独絶縁してい次。Conventionally, elements that saturate in circuit operation on the same semiconductor substrate were
The following are individually insulated.
第2図に従来の半導体装置の構at示す。同図において
、P型半碑体基板6上に、N型埋込#5とN型エピタキ
シャル層7を有し、そのN型エピタキシャル層7は、絶
縁層4で互いに絶縁分離嘔nている。その公庫さnたN
型エピタキシャル層7の内部に、N型拡散層2やP型拡
散層3が複数存在して素子を横取している。FIG. 2 shows the structure of a conventional semiconductor device. In the figure, an N-type buried #5 and an N-type epitaxial layer 7 are provided on a P-type half-base substrate 6, and the N-type epitaxial layers 7 are insulated and separated from each other by an insulating layer 4. That public treasury
A plurality of N-type diffusion layers 2 and P-type diffusion layers 3 exist inside the type epitaxial layer 7 and occupy the elements.
前述のように、素子を個々にi/I!3縁分離していた
のでは、素子1個当りの大きさが大きくなってしまう、
その為、いくつかの素子を同−N型エピタキシャル領域
内に設置するが、この場合設置した素子のいずnかが飽
和すると、飽オロし九P型板散層をエミッタ、N型具ビ
タキンヤル層金ペース。As mentioned above, the elements are individually i/I! If the three edges were separated, the size of each element would become large.
Therefore, several elements are installed in the same N-type epitaxial region, but in this case, when any of the installed elements is saturated, it becomes saturated and the 9P-type platelet scattering layer is placed at the emitter and the N-type epitaxial region. layer gold pace.
それらの近傍にあるP型拡散層をコレクタとする寄生P
NP )ランジスタの作用により、飽和したP型拡散層
から近傍のP型拡散層へJi、流を引き込む為、飽和す
る素子は同−N型エピタキシャル領域内に?i置できな
いという欠点がある。Parasitic P whose collector is the P-type diffusion layer in the vicinity of these
NP) Due to the action of the transistor, Ji current is drawn from the saturated P-type diffusion layer to the nearby P-type diffusion layer, so the saturated element is located within the same -N-type epitaxial region? There is a drawback that it cannot be set.
本発明の目的は、前記欠点を屏決し、飽和する素子を同
−型のエピタキシャル領域内に他の系子と共存させた際
の寄生PNPの発生を防ぐ工うにした半導体装Tilを
提供することにちる。It is an object of the present invention to solve the above-mentioned drawbacks and to provide a semiconductor device Til which is designed to prevent the generation of parasitic PNP when a saturated element is made to coexist with other elements in the epitaxial region of the same type. Nichiru.
本発明の構成げ、一導電型の半導体基板の主面に形成さ
扛た低濃度の逆4電型のエピタキシャル領域内に一導電
型の半導体領域が複数形成され、前記一導電型の半導体
領域の下部にそnぞれ位置し、かつ前記半導体基板と前
記エビタキクヤル憤域との境界に位置する高裏度の逆専
II型の半導体領域が複数形成さf′L友半導体装置に
おいて、前記逆*、電型の半纏体穎域は互いに分醐して
おり、前記エピタキシャル領域中であって、かつ駒記−
導!型の半導体領域どうしの間に高^度の通導電型の半
導体領域全形成したことを特徴とする。In the structure of the present invention, a plurality of semiconductor regions of one conductivity type are formed in a low concentration inverted quaternary type epitaxial region formed on a main surface of a semiconductor substrate of one conductivity type, and the semiconductor region of one conductivity type In the f'L friend semiconductor device, a plurality of high-reverse-type II type semiconductor regions are formed, each of which is located at the lower part of the semiconductor substrate and at the boundary between the semiconductor substrate and the recessed area. *, the electrotype semi-integral regions are separated from each other, are in the epitaxial region, and are
Guide! It is characterized in that a semiconductor region of high conductivity type is entirely formed between the semiconductor regions of the mold.
〔ち^4Mロレリ〕
次に本発明について図面を参照して詳細に説明する。第
1図μ不発明の一実施例の半導体装置を示すF!trI
f1図である。同図において、P型半導体6上のN型エ
ピタキンヤル鳩71t杷縁層4で分離した領域内に、4
1数のP型拡散層3やへ型拡散鳩2が存在している。こ
こで、飽和する素子の直下にある埋込層5′を、他の素
子との間で断ち切り、素子間にP型基板の領域を設ける
。そして七のP型基板の真上にN型拡叔tita2′を
配置する。[Chi^4M Loreli] Next, the present invention will be described in detail with reference to the drawings. FIG. 1 shows a semiconductor device according to an embodiment of the invention. trI
It is an f1 diagram. In the figure, in a region separated by an N-type epitaxial layer 71t on a P-type semiconductor 6, 4
A number of P-type diffusion layers 3 and hemi-type diffusion layers 2 are present. Here, the buried layer 5' immediately below the saturated element is cut off from other elements to provide a P-type substrate region between the elements. Then, an N-type expansion plate 2' is placed directly above the P-type substrate No. 7.
このような構造にすれば、飽和したP型拡散層3’ f
Z ミッタ、 Nff1工ビタ千ンヤル層V全ベース、
P型基板6をコレクタとじ友奇主PNPトランジスタに
より、飽和した電流を基板側−\逃がすことができる。With such a structure, the saturated P-type diffusion layer 3' f
Z Mitta, Nff1 Engineering Bitasenyar Layer V All Bases,
By connecting the P-type substrate 6 to the collector and using the main PNP transistor, the saturated current can be released to the substrate side.
素子間に収けfcP型基板6の真上にあるNm拡散層2
′に、寄生PNPトランジスタで近傍にめるP型拡敢t
=3*コレクタとして@翻しょうとしfC除に、寄生P
NP)ランジスタのベースの不純物濃度を上げて、電流
増幅率を下げ、飽和した電流を効率よくP型基板6へ逃
がす為のものでちる。Nm diffusion layer 2 located between the elements and directly above the fcP type substrate 6
', a P-type expansion t placed nearby by a parasitic PNP transistor
= 3 * As a collector, except fC, parasitic P
This is done to increase the impurity concentration in the base of the NP transistor, lower the current amplification factor, and efficiently release the saturated current to the P-type substrate 6.
本実施例の半導体gMfは、飽和する素子と他の素子と
を共存させた際、この飽和する素子のP型拡散層と他の
素子のP型拡散層との間に、N型菰散層の領域を有し、
かつ飽和する素子と他の素子の直下にあるN型埋込層が
先のN型拡散層の直下で分離しているような構造を有し
ている。In the semiconductor gMf of this example, when a saturated element and another element coexist, an N-type diffusion layer is formed between the P-type diffusion layer of the saturated element and the P-type diffusion layer of the other element. It has an area of
In addition, it has a structure in which the element to be saturated and the N-type buried layer immediately below the other element are separated immediately below the previous N-type diffused layer.
以上説明したように1本発明は5回路動作上飽和する素
子でも同−型エピタキシャル領域内に設置することがで
き、もって素子1イ固当9のサイズが縮小できるという
効果がある。As described above, the present invention has the effect that even elements which are saturated in the operation of five circuits can be installed in the same type epitaxial region, thereby reducing the size of the element 1 and the fixing member 9.
第1図は本発明の一実施例の半導体装1qの断面図、第
2図は従来の半導体装置のifr面囚である。
1・・・・・・酸化膜、2,2’・・・・・・N型拡散
層、3.3’・・・・・・P型拡散r=% 4・−・・
・・絶縁ツ、5.5’・・・・・・埋込層、6・・・・
・・P型半導体基板、7・・・・・・N型エピタキシャ
ル層。FIG. 1 is a sectional view of a semiconductor device 1q according to an embodiment of the present invention, and FIG. 2 is an IFR view of a conventional semiconductor device. 1...Oxide film, 2,2'...N type diffusion layer, 3.3'...P type diffusion r=% 4...
...Insulation, 5.5'...Buried layer, 6...
...P-type semiconductor substrate, 7...N-type epitaxial layer.
Claims (1)
電型のエピタキシャル領域内に一導電型の半導体領域が
複数形成され、前記一導電型の半導体領域の下部にそれ
ぞれ位置し、かつ前記半導体基板と前記エピタキシャル
領域との境界に位置する高濃度の逆導電型の半導体領域
が複数形成された半導体装置において、前記逆導電型の
半導体領域は互いに分離しており、前記エピタキシャル
領域中であって、かつ前記一導電型の半導体領域どうし
の間に、高濃度の逆導電型の半導体領域を形成したこと
を特徴とする半導体装置。A plurality of semiconductor regions of one conductivity type are formed in a low concentration epitaxial region of an opposite conductivity type formed on a main surface of a semiconductor substrate of one conductivity type, and each semiconductor region is located under the semiconductor region of one conductivity type, and In a semiconductor device in which a plurality of highly-concentrated semiconductor regions of opposite conductivity types are formed at the boundary between the semiconductor substrate and the epitaxial region, the semiconductor regions of opposite conductivity types are separated from each other, and in the epitaxial region, the semiconductor regions of opposite conductivity types are separated from each other. 1. A semiconductor device, wherein a highly doped semiconductor region of an opposite conductivity type is formed between the semiconductor regions of one conductivity type.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62152563A JP2538599B2 (en) | 1987-06-18 | 1987-06-18 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62152563A JP2538599B2 (en) | 1987-06-18 | 1987-06-18 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63316453A true JPS63316453A (en) | 1988-12-23 |
JP2538599B2 JP2538599B2 (en) | 1996-09-25 |
Family
ID=15543216
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62152563A Expired - Lifetime JP2538599B2 (en) | 1987-06-18 | 1987-06-18 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2538599B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6734522B2 (en) | 2000-07-25 | 2004-05-11 | Sharp Kabushiki Kaisha | Transistor |
-
1987
- 1987-06-18 JP JP62152563A patent/JP2538599B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6734522B2 (en) | 2000-07-25 | 2004-05-11 | Sharp Kabushiki Kaisha | Transistor |
Also Published As
Publication number | Publication date |
---|---|
JP2538599B2 (en) | 1996-09-25 |
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