JPH04113629A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04113629A JPH04113629A JP23306590A JP23306590A JPH04113629A JP H04113629 A JPH04113629 A JP H04113629A JP 23306590 A JP23306590 A JP 23306590A JP 23306590 A JP23306590 A JP 23306590A JP H04113629 A JPH04113629 A JP H04113629A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- type diffusion
- region
- electrode
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 235000012489 doughnuts Nutrition 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 1
- 239000010953 base metal Substances 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 241000255789 Bombyx mori Species 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にバイポーラＮＰＮ）ラ
ンジスタ構造をもった集積回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to an integrated circuit board having a bipolar NPN (NPN) transistor structure.
従来この種の半導体装置は、第３図、第４図に示す構造
を有し、その等価回路は活性領域の場合第５図、飽和領
域の場合第６図に示すようになっていた。即ち、第３図
乃至第６図において、Ｎ型拡散層１上にコレクタの電極
となるＮ型拡散層３とベースとなるＰ型拡散層２とを設
け、前記Ｐ型拡散層２内にエミッタとなるＮ型拡散層３
′を有し、基板４０と接続されているＰ形波散層２０で
他の領域と絶縁していた。尚、Ｎ型拡散層ｌは、Ｐ型半
導体基板４０内に形成され、その低部はＮ型埋込層３０
が形成されている。Conventionally, this type of semiconductor device has the structure shown in FIGS. 3 and 4, and its equivalent circuit is shown in FIG. 5 for the active region and FIG. 6 for the saturated region. That is, in FIGS. 3 to 6, an N-type diffusion layer 3 serving as a collector electrode and a P-type diffusion layer 2 serving as a base are provided on an N-type diffusion layer 1, and an emitter is formed in the P-type diffusion layer 2. N-type diffusion layer 3
', and was insulated from other regions by the P-type wave diffusion layer 20 connected to the substrate 40. Note that the N-type diffusion layer l is formed in the P-type semiconductor substrate 40, and its lower part is the N-type buried layer 30.
is formed.
さらに、表面に絶縁層８が形成され、その開口部１２；
１０，９に、それぞれコレクタの金属電極７、ベー
スの金属電極４、エミッタの金属電極５が形成される。Further, an insulating layer 8 is formed on the surface, and an opening 12 thereof;
A collector metal electrode 7, a base metal electrode 4, and an emitter metal electrode 5 are formed at 10 and 9, respectively.
第５図では、非飽和領域での第３図、第４図のトランジ
スタ１００が示されており、飽和すると第６図に示すよ
うに、トランジスタ１００のベースをエミッタ、コレク
タをベース、接地ヲコレクタとする寄生ｐｎＰ）ランジ
スタ２００が生じる。In FIG. 5, the transistor 100 of FIGS. 3 and 4 is shown in the non-saturation region, and when saturated, the base of the transistor 100 becomes the emitter, the collector becomes the base, and the ground becomes the collector. A parasitic pnP) transistor 200 is generated.
前述した従来の半導体装置は、飽和領域で使用すると、
等価回路は第６図に示すように、Ｐ型半導体基板４０と
接続されているＰ型拡散層２０に対し、寄生ＰＮＰ ）
ランジスタ２００が生じ、電流が基板（ＳＵＢ）に流れ
出してしまうという欠点がある。When the conventional semiconductor device mentioned above is used in the saturation region,
As shown in FIG. 6, the equivalent circuit is as follows:
There is a drawback that the transistor 200 is generated and current flows to the substrate (SUB).
本発明の目的は、このような欠点を除き、寄生ＰＮＰ
）ランジスタが生じないようにした半導体装置を提供す
ることにある。The purpose of the present invention is to eliminate such drawbacks and to eliminate parasitic PNPs.
) An object of the present invention is to provide a semiconductor device in which transistors are not generated.
本発明の半導体装置の構成は、半導体基板上の第１の導
電型の拡散層内に、バックゲートの電極となる第２の導
電型の第１領域とベースとなる第２領域とを設け、この
第２領域内に、エミッタとなる第３領域とコレクタとな
る第４領域とを設け、前記第３領域は第４領域でドーナ
ツ状に囲まれていることを特徴とする。The structure of the semiconductor device of the present invention is such that a first region of a second conductivity type serving as a back gate electrode and a second region serving as a base are provided in a diffusion layer of a first conductivity type on a semiconductor substrate; A third region serving as an emitter and a fourth region serving as a collector are provided within the second region, and the third region is surrounded by the fourth region in a donut shape.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図、第２図は本発明の一実施例の半導体装置の平面
図、断面図である。第１図において、本実施例は、Ｎ型
拡散層１に、この拡散層ｌをバイアスする為のＮ型拡散
層３を設け、その上の絶縁層８に開口１２を設けて電極
７を設け、チップ内の最高電位でバイアスした領域を設
け、Ｐ型拡散層２を形成し、その上の絶縁層８に開口１
１を設け、これを介して電極６を設けてベースとし、Ｐ
型拡散層２内にエミッタとなるＮ型拡散層３″と、前記
拡散層３″をドーナツ状に囲むコレクタとなるＮ型拡散
層３″とを形成し、絶縁層８にそれぞれ開口１０．１１
と電極５，６とを設けている。開口９を介して拡散層２
と接続されたベースの金属電極４を形成する。ベースと
なる拡散層２内に、エミッタとなるＮ型拡散層３″とエ
ミッタをドーナツ状に囲むコレクタとなるＮ型拡散層３
″を有しており、Ｎ型拡散層ｌは、電極７により最高電
位でバイアスされているので、飽和領域において、第６
図に示すような基板４０に対する寄生ＰＮＰトランジス
タが発生しない。また、エミッタをコレクタによりドー
ナツ状に囲んでいるので、エミッタに対するコレクタの
対向面が４方向と十分な為、電流増幅率ｈＦＥが大きく
なる。1 and 2 are a plan view and a sectional view of a semiconductor device according to an embodiment of the present invention. In FIG. 1, in this embodiment, an N-type diffusion layer 3 is provided in an N-type diffusion layer 1 for biasing this diffusion layer 1, an opening 12 is provided in an insulating layer 8 thereon, and an electrode 7 is provided. , a region biased at the highest potential within the chip is provided, a P-type diffusion layer 2 is formed, and an opening 1 is formed in the insulating layer 8 above it.
1 is provided, an electrode 6 is provided through this as a base, and P
An N-type diffusion layer 3'' serving as an emitter and an N-type diffusion layer 3'' serving as a collector surrounding the diffusion layer 3'' in a donut shape are formed in the type diffusion layer 2, and openings 10 and 11 are formed in the insulating layer 8, respectively.
and electrodes 5 and 6 are provided. Diffusion layer 2 through opening 9
A base metal electrode 4 connected to the base metal electrode 4 is formed. In the diffusion layer 2 which is the base, there is an N-type diffusion layer 3'' which is the emitter and an N-type diffusion layer 3 which is the collector and surrounds the emitter in a donut shape.
'', and the N-type diffusion layer l is biased at the highest potential by the electrode 7, so in the saturation region, the sixth
A parasitic PNP transistor to the substrate 40 as shown in the figure does not occur. Furthermore, since the emitter is surrounded by the collector in a donut shape, the number of opposing surfaces of the collector and the emitter in four directions is sufficient, so that the current amplification factor hFE becomes large.
以上説明したように、本発明は、特に第５図に示す等価
回路を飽和領域においても実現することができ、電流を
半導体基板に流さないという効果がある。また、従来の
バーチカル型ＮＰＮ トランジスタに対し、本発明は、
ラテラル型ＮＰＮ）ランジスタなので、トランジスタを
順方向、逆方向で使用しても、寄生ＰＮＰ ）ランジス
タが生じないので、双方向スイッチ回路に最適となると
いう効果もあり、さらにｈＦＨの大きさはエミッタに対
するコレクタの対向面で決定される為、本発明は、エミ
ッタをコレクタでドーナツ状に囲んでいるため、十分大
きなｈｙｔを提供できるという効果もある。As explained above, the present invention is particularly effective in realizing the equivalent circuit shown in FIG. 5 even in the saturation region, and in preventing current from flowing through the semiconductor substrate. Furthermore, compared to the conventional vertical type NPN transistor, the present invention
Since it is a lateral type NPN) transistor, no parasitic PNP) transistor is generated even if the transistor is used in the forward or reverse direction, making it ideal for bidirectional switch circuits. Since the hyt is determined by the facing surface of the collector, the present invention has the effect that a sufficiently large hyt can be provided because the emitter is surrounded by the collector in a donut shape.
図、第２図は第１蚕のｘ−ｘ’線に沿った断面図、第３
図、第４図は従来の半導体装置のそれぞれ平面図および
断面図、第５図は第３図の活性状態の等価回路図、第６
図は第３図の飽和状態の等価回路図である。Figure 2 is a cross-sectional view of the first silkworm along the line x-x';
4 are a plan view and a sectional view, respectively, of a conventional semiconductor device, FIG. 5 is an equivalent circuit diagram of the active state of FIG. 3, and FIG.
The figure is an equivalent circuit diagram of the saturated state shown in FIG.
■・・・・・・Ｎ型拡散層、２・・・・Ｐ型拡散層、３
・・Ｎ型拡散層、４，５，６．７・・・・・・金属電極
、８・・・・・・絶縁層、９，１０，１１．１２・・印
・開口、１００・・・・・・ＮＰＮ）ランジスタ、２０
０・旧・・寄生ＰＮＰ）ランジスタ、２０・川・・Ｐ型
拡散層、３ｏ・・・・・Ｎ型埋込層、４０・・・・・・
Ｐ型半導体基板。■...N-type diffusion layer, 2...P-type diffusion layer, 3
...N-type diffusion layer, 4,5,6.7...Metal electrode, 8...Insulating layer, 9,10,11.12...Mark/opening, 100... ...NPN) transistor, 20
0. Old... Parasitic PNP) transistor, 20. River... P-type diffused layer, 3o... N-type buried layer, 40...
P-type semiconductor substrate.
代理人 弁理士 内 原 晋Agent: Patent Attorney Susumu Uchihara
Claims (1)
トの電極となる第２の導電型の第１領域とベースとなる
第２領域とを設け、この第２領域内に、エミッタとなる
第３領域とコレクタとなる第４領域とを設け、前記第３
領域は第４領域でドーナツ状に囲まれていることを特徴
とする半導体装置。A first region of a second conductivity type that becomes an electrode of a back gate and a second region that becomes a base are provided in a diffusion layer of a first conductivity type on a semiconductor substrate, and an emitter and an emitter are provided in this second region. a third region that is a collector and a fourth region that is a collector;
A semiconductor device characterized in that the region is surrounded by a fourth region in a donut shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23306590A JPH04113629A (en) | 1990-09-03 | 1990-09-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23306590A JPH04113629A (en) | 1990-09-03 | 1990-09-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04113629A true JPH04113629A (en) | 1992-04-15 |
Family
ID=16949253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23306590A Pending JPH04113629A (en) | 1990-09-03 | 1990-09-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04113629A (en) |
-
1990
- 1990-09-03 JP JP23306590A patent/JPH04113629A/en active Pending
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