JPS60260153A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60260153A
JPS60260153A JP11606184A JP11606184A JPS60260153A JP S60260153 A JPS60260153 A JP S60260153A JP 11606184 A JP11606184 A JP 11606184A JP 11606184 A JP11606184 A JP 11606184A JP S60260153 A JPS60260153 A JP S60260153A
Authority
JP
Japan
Prior art keywords
region
emitter
collector
base
electrode connecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11606184A
Other languages
Japanese (ja)
Inventor
Kenji Oka
健次 岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11606184A priority Critical patent/JPS60260153A/en
Publication of JPS60260153A publication Critical patent/JPS60260153A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/735Lateral transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To form a lateral P-N-P transistor having the more superior characteristics by a method wherein a part of a collector provided in the circumference of an emitter is cut apart, and a diffusion layer for base contact and a contact window are formed at this part. CONSTITUTION:A collector region 15 is made as not to exist at the part whereat an emitter region 14 is facing with a base electrode connecting region 16, and the base electrode connecting the region 16 is provided in place of the collector region as to approach the emitter region 14. Because a part of the collector 15 is removed, and the base electrode connecting region 16 is provided, a base current is made to flow more easily to the part facing to the base electrode connecting region 16 of the emitter 14 than the part directly under the emitter 14. Accordingly, implantation of minority carriers from the mitter 14 is increased at the periphery of the metal 14, the distance to reach the collector is shortened, and the amplification factor of the current is increased. Moreover, base resistance is reduced also because the base electrode connecting region 16 is provided in the neighborhood of the emitter 14.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体集積回路を構成するPNP )ランジス
タの構造に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a PNP transistor constituting a semiconductor integrated circuit.

(従来技術) 半導体集積回路はNPN)ランジスタ、PNPトランジ
スタ、抵抗、ダイオード、コンデンサ。
(Prior art) Semiconductor integrated circuits include NPN transistors, PNP transistors, resistors, diodes, and capacitors.

FET等から構成されるが、リニア集積回路ではNPN
)ランジスタが主に使用されることから、P型基板にN
型エピタキシャル層を形成し、その表面に素子を形成す
ることが一般的である。この場合素子を形成すべきN型
エピタキシャル層上にいかにしてPNP)ランジスタを
形成するかでいろいろな工夫がされてきた。
It is composed of FET, etc., but in linear integrated circuits it is NPN.
) Since transistors are mainly used, N
It is common to form a type epitaxial layer and form elements on the surface thereof. In this case, various efforts have been made to determine how to form a PNP transistor on the N-type epitaxial layer on which the device is to be formed.

従来のPNP )ランジスタに、N型エピタキシャル層
をベースとし、表面からP型不純物を近接して2個所に
選択拡散させて、その一方をエミ。
A conventional PNP) transistor is based on an N-type epitaxial layer, and P-type impurities are selectively diffused into two places close to each other from the surface, and one of them is made into an emitter.

り、他方をコレクタとしたものがある。このトランジス
タは電流が横方向に流れるので横型PNPトランジスタ
と呼ばれている。
There is one in which the other is the collector. This transistor is called a lateral PNP transistor because current flows horizontally.

ここで従来の横型PNP トランジスタの構造を第1図
に示す。第1図(a)は横型PNP)ランジスタの構造
を示す断面図s (b>は平面図である。
The structure of a conventional lateral PNP transistor is shown in FIG. FIG. 1(a) is a cross-sectional view showing the structure of a horizontal PNP transistor (FIG. 1(a) is a plan view).

第1図(a)で1はP型半導体基板、2はN型埋込層、
3はP型組縁領域、4はエミッタ、5はコレ。
In FIG. 1(a), 1 is a P-type semiconductor substrate, 2 is an N-type buried layer,
3 is the P-type assembly region, 4 is the emitter, and 5 is this.

フタ、6はベース電極用のオーミック拡散層、7は表面
の絶縁層、8,9.10はそれぞれエミ。
The lid, 6 is an ohmic diffusion layer for the base electrode, 7 is an insulating layer on the surface, and 8, 9, and 10 are emitters.

り、コレクタ、ベース電極である0電備増幅率(hrE
)を上げるためエミ、り4の周囲にこれを囲むようにコ
レクタ5を配置させることが多い。
0 power amplification factor (hrE), which is the collector and base electrodes.
), a collector 5 is often arranged around the emitter 4 so as to surround it.

この中でN型埋込層2はエミ、り4からP型基板1へ電
流が流れるのを妨げ、P型基契1とエミ。
In this, the N-type buried layer 2 prevents current from flowing from the emitter layer 4 to the P-type substrate 1, and connects the P-type base layer 1 and the emitter layer 4 to the P-type substrate 1.

り4との間で寄生PNPトランジスタが生じないように
するためである。
This is to prevent a parasitic PNP transistor from occurring between the transistor and the transistor 4.

(発明が解決しようとする問題点) ところが従来の構造では次の様な欠点がある。(Problem that the invention attempts to solve) However, the conventional structure has the following drawbacks.

1つは電流増幅率が小さいことであり、もう1つはベー
ス抵抗が大きいことである。
One is that the current amplification factor is small, and the other is that the base resistance is large.

hFEが小さい原因はエミ、り4とコレクタ5とは平面
的に配置されており、これらの距離がiスフで決定され
るため、距離を小さぐできないことと、表面を電流が流
れる時再結合しやすいことと、エミッタからのキャリア
の注入がエミ、り直下のベース領域に多く、このためコ
レクタに到達する割合いが少いこと等である。又、ベー
ス抵抗が大きい原因はベース電極10がコレクタ5の外
でベース電極用の拡散層6に接続されているためであし
、よりすぐれた特性を有する横型PNP )ランジスタ
を提供することにある。
The reason why the hFE is small is that the emitter 4 and the collector 5 are arranged in a plane, and the distance between them is determined by the i space, so the distance cannot be made smaller, and the recombination occurs when a current flows through the surface. In addition, many carriers are injected from the emitter into the base region directly below the emitter, and therefore the proportion of carriers reaching the collector is small. Further, the reason for the large base resistance is that the base electrode 10 is connected to the base electrode diffusion layer 6 outside the collector 5, and the purpose is to provide a lateral PNP transistor with better characteristics.

(問題点を解決するための手段) 本発明の特徴はエミ、りの周囲に設置されているコレク
タの一部を分断し、その部分にベースコンタクト用の拡
散及びコンタクト窓を形成することである。
(Means for Solving the Problems) The feature of the present invention is to divide a part of the collector installed around the emitter and ri, and form a diffusion and contact window for the base contact in that part. .

(実施例) 次に、本発明の一実施例を第2図によシ説明する0 第2図(a)で11はP型基板、12はN型埋込層、1
3はP型絶縁領域、14はエミ、り、15はコレクタ、
16はベース電極用のオーミ、り拡散層、17は表面絶
縁層、18,19.20はそれぞれエミ、り、コレクタ
、ベース電極である。従来の構造とp違いはペース電極
20が従来はコレクタ領域5の外側でペース電極接続領
域6に接続しているのに対し、本実施例ではコレクタ領
域15のエミッタ領域14がベース電極接続領域16に
対向する部分で存在しないようにし、その代わシにペー
ス電極接続領域16をエミ、り領域14に接近するよう
に設けたことである。
(Embodiment) Next, an embodiment of the present invention will be explained with reference to FIG. 2. In FIG.
3 is a P-type insulating region, 14 is an emitter, 15 is a collector,
16 is an ohmic diffusion layer for the base electrode, 17 is a surface insulating layer, and 18, 19, and 20 are ohmic, radial, collector, and base electrodes, respectively. The difference from the conventional structure is that conventionally, the pace electrode 20 is connected to the pace electrode connection region 6 outside the collector region 5, whereas in this embodiment, the emitter region 14 of the collector region 15 is connected to the base electrode connection region 16. Instead, the pace electrode connection region 16 is provided so as to be close to the emitter region 14.

次に本発明が従来の欠点を緩和する理由を述べる。第3
図に従来の構造によるベース電流の流れを示す。この図
でわかる通9ベース電流はエミ。
Next, the reason why the present invention alleviates the conventional drawbacks will be described. Third
The figure shows the flow of base current in a conventional structure. The 9 base current that can be seen in this diagram is emmi.

り4の周辺よシもエミ、り4の直下から集中的に流れる
。ペース電流の分布はエミ、り4からの少数キャリアの
分布と同じなので、エミ、り4からの少数キャリアの注
入はエミ、り4周辺よシもエミッタ4の直下に多く発生
し、このエミ、り4の直下の少数キャリアはコレクタ5
に到達するまでの距離が長く、再結合しやすい。すなわ
ち電流増幅率を低下させてしまう。またベース抵抗に関
してはペース電極接続領域6とエミッタ4との距離が長
いため大きくなる。
The water flows intensively from the area around Ri4 and directly below Ri4. The distribution of the pace current is the same as the distribution of minority carriers from emitters and ri4, so many minority carriers are injected from emitters and ri4 directly under emitter 4 as well as around emitters and ri4. The minority carrier directly under RI 4 is collector 5.
The distance it takes to reach is long and it is easy to recombine. In other words, the current amplification factor is reduced. Furthermore, the base resistance becomes large because the distance between the pace electrode connection region 6 and the emitter 4 is long.

第4図に本実施例によるペース電流の流れを示す。コレ
クタ15の一部をとり去シ、ペース電極接続領域16を
置いであるため、ペース電流はエミ、り14の直下よシ
もエミ、り14のペース電極接続領域16に面する部分
に流れやすくなる。
FIG. 4 shows the flow of pace current according to this embodiment. Since a portion of the collector 15 is removed and the pace electrode connection area 16 is left in place, the pace current easily flows from directly under the emitter 14 to the part of the emitter 14 facing the pace electrode connection area 16. Become.

このためエミ、り14からの少数キャリアの注入はエミ
、り14の周辺に多くな勺、コレクタへ到達する距離は
短かくなシミ流増幅率が増す。またペース抵抗もエミ、
り14の近くにペース電極接続領域16があるため下が
る。
For this reason, the minority carriers injected from the emitter 14 are concentrated around the emitter 14, and the distance to reach the collector is short, increasing the spot flow amplification factor. Also, the pace resistance is Emi,
The pace electrode connection area 16 is located near the wall 14 so that it is lowered.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来構造の横型PNP)ランジスタを示し、同
図(a)は平面図、同図(b)は同図(a)のA−A’
での断面図である。 第2図は本発明の一実施例による横型PNP)ランジス
タを示し、(a)は平面図、同図(b)は同図(a)の
B−B’での断面図である。 第3図は従来構造の横型PNPの断面図を示し、第4図
は本発明の一実施例による横型PNPの断面図で、それ
ぞれペース電流の流れを示すためのものである。 1.11・・・・・・P型半導体基板、2.12・・・
・・・N型埋込層、3.13・・・・・・P型絶縁分離
領域、4゜14・・・・・・エミ、り領域、5.15・
・・・・・コレクタ領域、6.16・・・・・・ペース
電極接続領域、7.17・・・・・・絶縁膜、8.18
・・・・・・エミ、り電極、9.19・・・・・・コレ
クタ電極、10.20・・・・・・ペース電極。 竿 1vpr 第 2 図 竿 3I!gI $ 4 閏
Figure 1 shows a horizontal PNP transistor with a conventional structure, in which (a) is a plan view, and (b) is a line AA' in (a).
FIG. FIG. 2 shows a horizontal PNP transistor according to an embodiment of the present invention, in which (a) is a plan view and FIG. 2 (b) is a sectional view taken along line BB' in FIG. 2 (a). FIG. 3 shows a cross-sectional view of a horizontal PNP having a conventional structure, and FIG. 4 shows a cross-sectional view of a horizontal PNP according to an embodiment of the present invention, each of which shows the flow of pace current. 1.11...P-type semiconductor substrate, 2.12...
...N type buried layer, 3.13...P type insulation isolation region, 4゜14...Emitter region, 5.15.
... Collector region, 6.16 ... Pace electrode connection region, 7.17 ... Insulating film, 8.18
... Emi electrode, 9.19 ... Collector electrode, 10.20 ... Pace electrode. Pole 1vpr 2nd figure Pole 3I! gI $ 4 Leap

Claims (1)

【特許請求の範囲】[Claims] ベース領域として作用する一導電型°の半導体領域と、
該半導体領域内に設けられた他の導電型のエミッタ領域
と、該エミ、り領域を一部を除いて囲むように前記半導
体領域に形成された前記他の導電型のコレクタ領域と、
該コレクタ領域の分断されている個所に形成されたベー
ス電極接続領域とを有することを特徴とする半導体装置
a semiconductor region of one conductivity type acting as a base region;
an emitter region of another conductivity type provided within the semiconductor region; and a collector region of the other conductivity type formed in the semiconductor region so as to surround the emitter region except for a portion thereof;
A semiconductor device comprising a base electrode connection region formed at a portion where the collector region is divided.
JP11606184A 1984-06-06 1984-06-06 Semiconductor device Pending JPS60260153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11606184A JPS60260153A (en) 1984-06-06 1984-06-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11606184A JPS60260153A (en) 1984-06-06 1984-06-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60260153A true JPS60260153A (en) 1985-12-23

Family

ID=14677738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11606184A Pending JPS60260153A (en) 1984-06-06 1984-06-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60260153A (en)

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