JPS60227471A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the generation of a current concentration up to secondary breakdown by forming a plurality of collector electrode layers in the periphery of a plurality of base regions and connecting these collector electrode layers to a collector wiring layer through collector electrodes. CONSTITUTION:A second layer insulating film 11 is formed on a first layer insulating film 8, a base first electrode layer 9, collector first electrode layers 10, emitter first electrode layers 16, an emitter first wiring layer 17 and a base first wiring layer 14. Collector contact holes CC1-CC3 for exposing the surface sections of a plurality of the layers 10 and emitter contact holes CE1, CE2 for exposing the surface sections of the layers 16 are shaped to the film 11. A collector second electrode wiring layer 15 connected in common with the layers 10 through these holes CC1-CC3 is formed, and an emitter second electrode wiring layer 13 connected to the layers 16 through the holes CE1, CE2 is shaped. Accordingly, since N<+> type layers 7a-7c are formed around base regions 5a, 5b and the layers 10 are connected a collector series resistance value is reduced.

Description

[Detailed description of the invention] [Technical field] The present invention relates to a semiconductor integrated circuit device.

[Background Art] In general, power transistors in a semiconductor integrated circuit require a large current, so as disclosed in Japanese Utility Model Publication No. 46-28166, at least two or more A transistor is built into a semiconductor substrate, and the emitter electrode, base electrode, and collector electrode of each transistor are commonly connected through a wiring layer, and the transistor is used as if it were a single power transistor.

As is well known, power transistors are transistors that can withstand high output, so their structure is inevitably large, and the width of the wiring layer formed on the surface of the semiconductor substrate is also large accordingly. There is.

In addition, power transistors can provide large output,
In order to prevent current concentration between the emitter layer, base layer, and collector layer, which causes secondary breakdown that can lead to destruction of the power transistor, the electrodes should be placed on the emitter layer, base layer, and collector layer as much as possible. The length of each electrode facing each other is increased.

Therefore, as described above, the area occupied by the wiring layer of a semiconductor integrated circuit incorporating a power transistor manufactured using the single-layer electrode wiring technology has become large.

In reality, the area occupied by this wiring layer is the emitter layer, base layer,
The area is approximately twice that of the area where the upper and collector layers are formed.

As described above, even the area of the power transistor itself is large, and the area becomes even larger by forming such a wiring layer, which has been a major hindrance in terms of improving the degree of integration of semiconductor integrated circuits.

[Object of the Invention] Therefore, the present invention has been made to eliminate such drawbacks, and its purpose is to provide a semiconductor integrated circuit with an improved degree of integration, and also to provide a power transistor in the semiconductor integrated circuit. It is an object of the present invention to provide a new electrode wiring structure of an emitter electrode, a base electrode, and a collector electrode, which is effective in preventing the occurrence of current concentration phenomenon that leads to secondary breakdown breakdown of a transistor for use in a semiconductor device.

[Summary of the Invention 1 To achieve this object, the basic configuration of the present invention includes at least a single collector region of a first conductivity type, a plurality of base regions of a second conductivity type formed within the collector region, and a plurality of base regions of a second conductivity type formed within the collector region. The plurality of second conductivity type base regions are electrically commonly connected to each other, and the plurality of second conductivity type emitter regions are electrically connected to each other, and the plurality of second conductivity type emitter regions are electrically connected to each other. In a semiconductor integrated circuit device comprising at least a transistor configured by having emitter regions of a first conductivity type electrically connected to each other in common, a first layer insulating film is formed on the main surface of the semiconductor substrate,
The first layer insulating film has a plurality of emitter first window openings for exposing most of the surface portions of the plurality of emitter regions on the main surface of the semiconductor substrate, and a plurality of emitter first window openings for exposing most of the surface portions of the plurality of base regions. a plurality of base first window openings for exposing a majority of the surface portion and a plurality of collector first window openings for exposing the surface portion of the single collector region at a plurality of locations; A plurality of emitters are connected to each other by a single electrode wiring layer.
multiple or single emitter first electrode layers each or in common ohmic contact to the multiple emitter regions via window openings and common to the multiple base regions via the multiple base first window openings; A single base first electrode wiring layer is formed in ohmic contact with the collector region, and a plurality of collector first electrode layers are respectively in ohmic contact with the collector region at the plurality of collector first window openings, and the first layer insulating film is A second layer insulating film is formed on the top and the first layer electrode wiring layer, and the second layer insulating film has a plurality of layers for exposing at least a portion of the surface portion of the plurality of collector first electrode layers. At least a collector second window opening is formed on the second layer insulating film, and a second layer electrode wiring layer is formed on the second layer insulating film to connect the plurality of flapers through the plurality of collector second window openings.
A single collector electrically connected to the electrode layer
It is characterized in that at least a l's2 electrode wiring layer is formed.

[Embodiment 1] FIG. 4 shows a sectional view of a main part of a completed semiconductor integrated circuit device according to the present invention, in which an N+ type N2 is selectively formed on a P type semiconductor substrate 1. And said P
On the type semiconductor substrate 1 and the N+ type layer 2, an N type layer 3 is formed, for example, by epitaxial growth. Further, a P-type layer 4, which is an isolation layer, is formed around the N+-type layer 2 in order to electrically isolate the N+-type layer in the N-type layer. On the surface of the N-type layer 3 surrounded by the P-type layer 4, P-type layers 5a and 5b are formed, which serve as base layers of the power transistor. N+ type layers 6a and 6b, which serve as emitter layers, are formed in the surface regions of these P type layers 5a and 5b. Also, on the surface of the N-type layer 3, in areas other than the P-type layers 5a and 5b, is there an N+-type layer? a, 7b and 7c are of the form r&
has been done. This becomes a contact layer for the N-type layer 3 which becomes a collector layer. An oxide film 8, which is an insulating layer, is formed on the surface of the semiconductor substrate 1 on which various impurity layers have been formed. A hole is made in a part of the region located on the impurity layer to form a base electrode 9 seal and a collector electrode 10. Further, an oxide film 11 is formed on the base electrode 9 and collector electrode 10 as well as on the oxide film 8. In this oxide film 11, a hole is formed in a part of the region above the N-type layers 6a and 6b, which are emitter layers, and an emitter electrode 12 is formed here, and this emitter electrode 12 is connected by a wiring layer 13. ing.

FIG. 5 is a two-dimensional perspective view of the wiring layer structure on the semiconductor substrate.
are collectively taken out as wiring 114. An oxide film 11 is formed on this upper surface, and a wiring layer 1 connected to the emitter electrode 12 by a through hole is formed on this surface.
3 runs within the power transistor formation region. Further, a wiring layer 15 also connected to the collector electrode 10 through a through hole runs within the power transistor formation region.

2 and 3 are main parts of a structure during the manufacturing process of a semiconductor integrated circuit device according to the present invention, in order to explain the structure of the first layer insulating film and the first electrode wiring layer according to the embodiment of the present invention. A cutaway view and a plan view are shown. As shown in the figure, a first layer insulating film 8 is formed on the main surface of the semiconductor substrate, and this first M insulating film 8 covers most of the surface portions of the plurality of emitter regions 6a, 6b on the main surface of the substrate. a plurality of emitter first contact holes Ce, Ce2 for exposure;
A plurality of base first contact holes Cl) for exposing most of the surface portions of the plurality of base regions 5a and 5b.
, Cb 2 and a plurality of flefter first contact holes Cc for exposing the surface portions of the plurality of high impurity concentration regions 7a, 71), 70 in the single collector layer 3.

Ce2. Ce3 is formed, and a single emitter first electrode layer 16 is commonly ohmically contacted to the plurality of emitter regions 6a and 6b through the plurality of emitter first contact holes Ce1lCe2 by the first layer electrode wiring layer; A single base first electrode layer 9 is in common ohmic contact with the plurality of base regions 5a, 5b via the base first contact holes CbIICb2, and the plurality of flefter first contact holes CCIICc2. A plurality of collector first electrode layers 10 are formed in ohmic contact with each of the high impurity concentration regions 7af7I)f7c via Ce3.

In addition, in FIGS. 2 and 3, Jeb is an emitter-base PN junction, Jbc is a base-collector PN junction,
Jcc indicates a collector high impurity concentration region junction, and Jci indicates a collector isolation region junction.

Furthermore, as shown in FIG. 3, each emitter region 6a.

Most of the surface portion of the emitter first contact hole Ce1. It is in ohmic contact with the emitter first electrode layer 16 via Ce2, and most of the surface portion of each base region 5a, 5b is formed into a base first contact hole Cb1. Cb =
Since the base is in ohmic contact with the first electrode layer through the emitter-base PN junction, the current density of the current flowing across the emitter-base PN junction Jel+ is almost uniform at each part of the emitter-base PN junction, which prevents secondary breakdown breakdown of the transistor. It is possible to prevent the current concentration phenomenon.

Further, referring back to FIGS. 4 and 5, the first layer insulating film 8 and the first layer electrode wiring layer 9.10°16.17.1
A second layer insulating film 11 is formed on the second layer insulating film 11, and collector second contact holes CC for exposing at least a portion of the surface portions of the plurality of collector first electrode layers 10 are formed in the second layer insulating film 11. cc2. cc3 and emitter second contact holes CE, cc2 for exposing at least a portion of the surface portion of the emitter first electrode scrap 16 are formed, and a plurality of collector second contact holes cc, cc2 are formed by the second layer electrode wiring layer. , cc, , cc, a single collector PS2 electrode wiring layer 15 electrically commonly connected to the plurality of collector ff1l electrode layers via the plurality of emitter second contact holes CE, is formed.

An emitter second electrode wiring layer is formed which is electrically connected to the emitter first electrode layer 16 via cc2.

In this way, a plurality of high impurity concentration regions 7a+7by 7c are formed around the plurality of base regions 5a, 5b and are connected to the collector electrode 10, so that the resistance value rc9 of the collector series resistance is reduced.

[Effects] According to the embodiment of the present invention described above, the plurality of emitter first electrode layers 16 are electrically commonly connected by the emitter first wiring layer 17 and the emitter second wiring layer 13, and the plurality of base first Since the electrode layer 9 is electrically connected through the common mound by the base NS1 wiring layer, it is possible to obtain a power transistor in which the emitter and pace/flutter are commonly connected as shown in the equivalent circuit of Fig. 1. I can do it.

[Modification] According to the embodiment of the present invention described above, the common connection of the emitter electrodes is performed by the first layer electrode wiring layer and the second layer electrode wiring layer, but the present invention is limited to this. However, the common connection of the emitter electrodes may be made by using only one of the first electrode wiring layer and the second wiring layer.

By creating a multilayer wiring structure in this way, the wiring layer that was conventionally formed within the power transistor formation area can be formed within the power transistor formation area, which increases the degree of integration.
I can measure two.

In this embodiment, the semiconductor integrated circuit is formed on the surface of the P-type semiconductor substrate, but it may also be formed on the surface of the N-type semiconductor substrate. However, in this case, it is of course necessary that the conductivity types of the impurity layers are all reversed.

Further, in this embodiment, the insulating film interposed between the wiring layers is a silicon dioxide film, but is not limited to this, and may be an insulating resin, PSG (phosphorus silicate glass), BSG (boron silicate glass), or the like.

[Brief explanation of the drawing]

FIG. 1 shows an equivalent circuit of a power transistor configured in a semiconductor integrated circuit, and FIGS. 2 and 3 are cross-sectional views of essential parts of a structure during the manufacturing process of a semiconductor integrated circuit device according to the present invention, and FIG. A plan view is shown, and FIGS. 4 and 5 are a sectional view and a plan view of essential parts of a completed semiconductor integrated circuit device according to the present invention. 1--P type semiconductor substrate, 216a+ 61) 17a+7
13, 7c...N+ type layer, 3--N type layer, 4.5a. 5b: P-type layer, 8: First layer insulating film, 11: Second layer insulating film, 9: Base first electrode layer, 14: Base first
Wiring layer, 16...Emitter first electrode layer, 17...Emitter first wiring layer, 10...Collector first electrode layer, 13...
Emitter second wiring layer, 15...Collector second wiring layer. −ze −/

Claims (1)

[Claims] At least a single reflector region of a first conductivity type, a plurality of base regions of a second conductivity type formed within the collector region, and a single reflector region of a single conductivity type formed within the plurality of base regions of the second conductivity type. a semiconductor substrate comprising a first conductivity type emitter region;
A semiconductor integrated device comprising at least a trannostar configured such that the plurality of second conductivity type base regions are electrically commonly connected to each other and the plurality of first conductivity type emitter regions are electrically commonly connected to each other. In the circuit device, a first layer insulating film is formed on the main surface of the semiconductor substrate,
The first layer insulating film includes a plurality of emitter first window openings for exposing most of the surface portions of the plurality of emitter regions on the main surface of the semiconductor substrate, and a surface portion of the plurality of base regions. Multiple bases to expose most of the 1st
A window opening and a plurality of collector first window openings for exposing the surface portion of the single collector region at a plurality of locations are formed, and the first electrode wiring layer exposes each or a common collector region to the plurality of emitter regions. a plurality or single emitter first electrode layer in ohmic contact with the plurality of emitter first electrode layers; a single base first electrode wiring layer in common ohmic contact with the plurality of base regions via the plurality of base first window openings; A plurality of collector first electrode layers are formed in ohmic contact with the collector region at the plurality of collector first window openings, and a second layer insulating film is formed on the first layer insulating film and on the first layer electrode wiring layer. A plurality of collector second window openings are formed in the second layer insulating film to expose at least a portion of the surface portions of the plurality of collector first electrode layers, and a second layer electrode wiring layer is formed. A semiconductor integrated circuit comprising at least a single collector second electrode wiring layer electrically commonly connected to the plurality of collector first electrode layers via the plurality of collector second window portions. circuit device.