JP3244292B2 - Transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor,
In particular, the present invention relates to a high breakdown voltage, large current bipolar transistor.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional high breakdown voltage, large current
FIG. 4 is a cross-sectional view of a cell portion of a mirror-type transistor. semiconductor
The substrate 1 is N⁺ N on the mold layer^- Silicon with mold layer
Semiconductor substrate. This semiconductor substrate 1 is a transistor
N, not shown⁺ The lower part of the mold layer
A collector electrode is taken out from the pole. Base area 2
P-type and N of the semiconductor substrate 1^- Layer. P type
The base region 2 of N ⁺ Type emitter region 3 is provided
It is. An opening provided in the insulating film 9 is formed in the emitter region 3.
, The emitter electrode 11 is connected. Base area
2, the base electrode 10 is connected through the opening of the insulating film 9
Is done. The lower part of the base electrode 10 is P⁺ Low resistance area of mold
Is a contact of the base electrode 10 with the P-type base region 2
It is provided for. High voltage, large current bipolar
Type transistor chips have many such cells,
It is formed by being arranged in a plane.

FIG. B. FIG. 3 is an explanatory diagram of ASO.
R. B. ASO (Reverse Bias Area of Safe Operatio
n) is a reverse-bias safe operation area, in which a reverse bias is applied to the junction between the base and the emitter, that is, the transistor is turned off and a constant base current is pulled, and the collector current with respect to the collector voltage for safe operation Is shown. In the case of the transistor having the conventional structure shown in FIG. B. As shown by the dotted line in FIG. 8, the ASO has a tendency that the operating region becomes narrow in a region where the collector current is large.

It is needless to say that a power transistor having a high withstand voltage and a large current needs to have a wide safe operation area (ASO). However, in the structure of the conventional transistor shown in FIG. 9, current is concentrated in the emitter region 3 immediately below the emitter electrode at the time of reverse bias, so that
R. B. ASO was weak. When the transistor is in the ON state, the bias becomes deeper in the peripheral portion due to the presence of the base resistor, and the collector current mainly flows from the peripheral portion of the emitter region 3 to the base region 2, passes through the collector region of the semiconductor substrate 1, and is not shown. Flows to the collector electrode. That is, the ON current is most active on the side surface of the emitter region 3. On the other hand, when the transistor is in the OFF state (state in which the base-emitter junction is reverse-biased), the bias at the central portion becomes deeper, and the collector current passes through the central portion of the emitter region from the collector electrode (not shown). Therefore, it is considered that the current flows to the emitter electrode 11. For this reason,
The collector current flows directly below the emitter electrode 11 and causes the transistor to break down.

[0005] The conventional transistor shown in FIG.
R. B. To improve ASO, see Japanese Patent Application Laid-Open No. 62-1423.
No. 56 discloses that P ⁺ is located immediately below an N ⁺ type emitter region 3.
A technique for providing a mold low-resistance region is disclosed. According to this publication, the P ⁺ -type low-resistance region immediately below the emitter region is formed by inactivating the N ⁺ -type emitter region.
This is intended to avoid concentration of current at the time of reverse bias and to improve the secondary breakdown strength (that is, RB ASO).

However, in a production line, h
_In order to control the _FE , the diffusion depth of the N ⁺ -type emitter region is often changed. At this time,
When the emitter region is deepened to increase h _FE , h
_{Although the FE} is improved, the technique disclosed in this publication discloses that P
^Since the depth of the ⁺ type low resistance region does not change, B. A
There is a problem that the effect of strengthening SO is weakened.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention, the conventional view of the problems of the technology, is not affected by h _FE, reinforced R.
B. ASO, and F.A. B. It is an object of the present invention to provide a transistor with an enhanced ASO (forward bias safe operation area).

[0008]

The emitter region of the transistor according to the present invention comprises an inactive portion of the high-concentration region of the first conductivity type connected to the emitter electrode, and a low-concentration region of the first conductivity type around the inactive portion. It comprises an operating portion of the first conductivity type high concentration region provided through the concentration region, and a second conductivity type low resistance region provided below the inactive portion.

[0009]

[Action] operation unit acts as an emitter, by controlling the diffusion depth, it is possible to control the h _FE of transistor to a desired value. Below the inactive portion of the emitter region, there is a low-resistance region of the second conductivity type.
B. Strengthen ASO. Further, since the operating portion of the emitter region is connected to the emitter electrode from the inactive portion through the first conductivity type low concentration region, the low concentration region acts as a kind of ballast resistor. B. ASO (Forward Bias Safe Operating Area) is strengthened.

[0010]

FIG. 1 is a sectional view of a cell portion of a transistor according to an embodiment of the present invention. In the figure, the structure other than the emitter region 3 is the same as that of the conventional technique shown in FIG. In the emitter region 3, the inactive portion 6 of the N ⁺ -type high-concentration region and the operating portion 5 are separated from each other, and the N ^-- type low-concentration region 12 forms part of the inactive portion 6 and the operating portion 5. It is arranged deeply to encompass. Further, below the N ⁻ -type low-concentration region 12, a P ⁺ -type low-resistance region 8 is arranged as a buried diffusion region.

FIG. 2 is an explanatory view of a cross section of the emitter region according to one embodiment of the present invention. The N ⁻ type low concentration region 12 functions as a ballast resistor 13. Therefore, in terms of an equivalent circuit,
The inactive section 6 is connected to the operation section 5 via the ballast resistor 13. Since the operating section 5 of the emitter region 3 faces the P-type base region, it operates as a normal emitter. Therefore, by controlling diffusion to an appropriate depth with respect to the base region 2, a desired region can be obtained. h _FE can be obtained.
On the other hand, the inactive portion 6 connected to the emitter electrode 11
Is an N ⁺ -type high-concentration region, and a P ⁺ -type low-resistance region 8 is arranged below the N ⁺ -type low-concentration region 12 via an N ⁻ -type low-concentration region 12.

FIG. 3 is an explanatory plan view of an emitter region according to one embodiment of the present invention. The emitter region 3 has N ⁺
An inactive portion 6 of the high-concentration region is provided with a P ⁺ -type low-resistance region 8 therebelow. The N ⁺ -type high-concentration region operating unit 5 is arranged in a donut shape at a distance from the inactive unit 6 via an N ⁻ -type low-concentration region 12 functioning as a ballast resistor 13.

Therefore, in the emitter region of one cell, the ballast resistor 13 is provided over the entire circumference between the donut-shaped operating portion 5 and the inactive portion 6 at the center.
Therefore, in one cell, the distribution of the current from the operation section 5 to the inactive section 6 is made uniform over the entire circumference. Further, in a high-withstand-voltage, large-current bipolar transistor chip, for example, several hundreds of the illustrated transistor cells are arranged in a plane. In each cell, a ballast resistor 13 is connected to the emitter equivalently. For this reason, the ballast resistor 13 makes the distribution of the current flowing from the collector to the emitter uniform within one chip over the entire chip.

FIGS. 4 to 7 are cross-sectional views showing a manufacturing process according to an embodiment of the present invention. FIG. 4 is a cross-sectional view in which a P ⁺ -type low-resistance region is formed immediately below a base electrode. Here, the thickness of the base region is about 20 to 30 μm, and its surface concentration is 10 ¹⁷
/ Cm ³ .

FIG. 5 is a cross-sectional view in which the P ⁺ -type low resistance region 8 is formed as a buried diffusion layer. P ⁺ type low resistance region 8
Is formed to a thickness of about 1 to 2 μm and an impurity concentration of about 10 ¹⁸ / cm ³ at a depth of 4 to 6 μm from the surface by MeV class high voltage ion implantation.

FIG. 6 is a cross-sectional view in which the N ⁻ type low concentration region 12 is formed. The N ⁻ -type low-concentration region 12 is diffused and formed from the surface of the P ⁺ -type low-resistance region 8 by ion implantation or the like. Its surface concentration is about 10 ¹⁸ / cm ³ .

FIG. 7 is a cross-sectional view in which the operating portion 5 and the inactive portion 6 in the emitter region are formed. Both the operating section 5 and the inactive section 6 are N ⁺ -type high-concentration regions, and are simultaneously formed by diffusion. Its surface concentration is 10 ¹⁹ to 10 ²⁰ / cm ³ and its depth is 3 to 5 μm.

The inactive portion 6 is ohmic-connected to the emitter electrode 11 and has a P ⁺ -type low resistance region 8 below it. Therefore, when the transistor is turned on, the current flows from the collector electrode (not shown) to the semiconductor substrate 1.
Through the collector region and the base region 2 and into the emitter region 3 from the side surface of the operating portion 5, and from the ballast resistor 13 to the emitter electrode 11 through the inactive portion 6. During the OFF operation of the transistor, the current tries to flow the shortest distance between the collector electrode and the emitter electrode 11, but P ⁺
In the inactive portion 6 having the low-resistance region 8, the current does not easily flow because the inverse β is low. For this reason, the current at the time of the OFF operation is distributed to avoid the inactive portion 6 and flow through the surrounding operating portion 5. B. ASO becomes stronger.

FIG. B. FIG. 3 is an explanatory diagram of ASO.
According to the present embodiment, the collector voltage V _CEX of about 600 V with respect to the collector current I _c of 6 A conventionally can be increased to about 1200 V. Also, by controlling the diffusion depth of the operating part 5 of the emitter region 3,
The h _FE of the transistor can be controlled to a desired value of about several hundreds.

F. B. ASO (forward-bias safe operation area) is a range of the collector voltage and the collector current in which the junction between the base and the emitter is forward-biased (that is, the transistor is in an ON state) and the safe operation is performed. Transistor breakdown is ultimately due to current concentration in the weaker parts of the weaker cells. By making the current distribution in the cell uniform by the ballast resistor 13 and making the current distribution between the cells in the chip uniform by the ballast resistor 13, F.F. B. ASO gets stronger. In this embodiment, the ballast resistor 13 is estimated to be about 20Ω per cell. B. ASO is about 20% stronger.

[0021]

As described in detail above, according to the structure of the emitter region of the present invention, the R.D. B. A
SO and F.I. B. While enhancing the ASO, it is possible to control the h _FE of transistor to a desired value.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a cell portion of a transistor according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram of an emitter region according to one embodiment of the present invention.

FIG. 3 is an explanatory diagram of an emitter region according to one embodiment of the present invention.

FIG. 4 is a cross-sectional view of a process for manufacturing a transistor of one embodiment of the present invention.

FIG. 5 is a cross-sectional view of a process for manufacturing a transistor of one embodiment of the present invention.

FIG. 6 is a cross-sectional view of a process for manufacturing a transistor of one embodiment of the present invention.

FIG. 7 is a cross-sectional view of a process for manufacturing a transistor of one embodiment of the present invention.

FIG. B. FIG.

FIG. 9 is a cross-sectional view of a cell portion of a conventional transistor.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/331 H01L 29/73

Claims (1)

(57) [Claims] 1. A semiconductor substrate forming a first conductivity type collector region, a second conductivity type base region provided in the semiconductor substrate, and a first conductivity type emitter region provided in the base region. A first conductive type emitter region connected to an emitter electrode , the first conductive type high concentration region being an inactive portion;
An operating portion comprising a first conductivity type high concentration region provided around the inactive portion via a first conductivity type low concentration region, further comprising: A transistor comprising: a second conductivity type low resistance region having a higher impurity concentration than the base region via a first conductivity type low concentration region.