JP3843570B2 - Horizontal diode - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a lateral diode among semiconductor elements mainly used in a power IC.
[0002]
[Prior art]
In a power IC in which a high-voltage output circuit (for example, 50 V or more) and a control circuit for driving the same are integrated on the same silicon chip, MOS devices that are voltage-driven devices are often used in recent years. This is because, in particular, with the advent of insulated gate bipolar transistors (hereinafter referred to as IGBTs), the drive current can be made extremely small compared to conventional bipolar transistors, and a small current can be switched. .
[0003]
In application of the MOS device, consideration must be given so that the gate voltage does not exceed the breakdown voltage of the gate oxide film. Therefore, it is common to connect a gate protection diode between the gate and source and cut the excessive voltage using the reverse breakdown voltage (avalanche voltage) of this protection diode so that the gate oxide film is not destroyed. Has been done.
[0004]
FIG. 7 is a cross-sectional view of a main part of a conventional protective diode. This lateral diode is a lateral diode in which a p diffusion region 2a is formed on the surface layer of the n ⁻ substrate 1, and a p ⁺ region 4 and an n ⁺ region 3a are formed on the surface layer of the p diffusion region 2a.
In FIG. 7, a p-type diffusion region 2a having a medium concentration is selectively formed on the surface layer of an n ⁻ substrate 1 which is a low concentration n-type semiconductor substrate. Further, the high concentration n ⁺ region 3a and the p ⁺ region 4 are formed so as not to contact the surface layer of the p-type diffusion region 2a, and metal electrodes 5 and 6 are formed on the regions 3a and 4 respectively. . The metal electrode 5 is connected to the cathode terminal K, and the metal electrode 6 is connected to the anode terminal A. This lateral diode has an advantage that the avalanche voltage can be arbitrarily changed by changing the impurity concentration of the p-type diffusion region 2a.
[0005]
FIG. 8 is a cross-sectional view of a main part of another conventional protective diode. This lateral diode is a lateral diode in which a p diffusion region 2 a and an n diffusion region 7 are formed on the surface layer of the n ⁻ substrate 1.
In FIG. 8, a p-type diffusion region 2b having a medium concentration and an n-type diffusion region 7 are selectively formed on the surface layer of an n ⁻ substrate 1 which is a low concentration n-type semiconductor substrate. Further, n ⁺ region 3a is formed in the surface layer of n type diffusion region 7, and high concentration p ⁺ region 4 is formed in the surface layer of p type diffusion region 2b. Metal electrodes 5 and 6 are formed on these regions 3 and 4, and the metal electrode 5 is connected to the cathode terminal K and the metal electrode 6 is connected to the anode terminal A. This lateral diode has the advantage that the overcurrent resistance is large because current flows through the n ⁻ substrate 1 and does not concentrate on the surface layer.
[0006]
FIG. 9 is a diagram showing a driving circuit and an output stage circuit of a totem pole circuit as an application example of the protective diode.
In FIG. 9, 31 is a drive circuit and 32 is an output stage circuit. The diodes indicated by symbols D1 and D2 in the figure are gate protection diodes. Each diode is connected between the gate and source of N1 which is an n-channel MOSFET and P1 which is a p-channel MOSFET. A signal from the input 1 (IN1) turns on the N3 MOSFET N3. When N3 is turned on, current I1 flows through the path R3-N3-R4. When I1 flows, the gate voltage of P1 decreases with respect to the source by the voltage generated by the gate resistors R3 and I1, P1 is turned on, and the current I2 flows. When the current I2 flows, the gate voltage of N1 rises with respect to the source by the gate resistances R1 and I2, N1 is turned on, and current is supplied from the high voltage power supply VDD to the load connected to the output terminal OUT. During this series of operations, N2 which is a low-side device and is an n-channel IGBT is in an off state. The voltage applied between the gate and source of N1 and P1 is reverse biased for the protection diodes D1 and D2. Resistors R2 and R4 in the circuit are introduced as limiting resistors for currents I2 and I1. In a steady state, a voltage applied between the gate and the source, that is, a so-called gate voltage is constant, but in a transient state such as switching, an excessive voltage may be applied instantaneously. When this voltage exceeds the breakdown voltage of the protection diode D1, an avalanche current flows through the protection diode, an excessive voltage is suppressed, and a voltage equal to or higher than the breakdown voltage (BV: Breakdown Voltage) is not applied between the gate and the source.
[0007]
The breakdown voltage of this protective diode is adjusted to about 7 V so that the electric field strength does not exceed 3 MV / cm when the thickness of the gate oxide film is 25 nm. In general, a Zener diode is used. In the case of a power IC, for example, as shown in FIG. 7, it is formed of a p-type diffusion region 2a having a medium impurity concentration and a high concentration n ⁺ region 3a. This breakdown voltage is controlled by utilizing an avalanche phenomenon occurring in a depletion layer formed on both sides of the pn junction. Further, since the breakdown voltage can control the electric field strength of the depletion layer by changing the impurity concentration of the p-type diffusion region 2a, a desired breakdown voltage can be obtained.
[0008]
When a load such as a capacitor charged in one direction (DC charged) is short-circuited, N2 which is a low-side device is turned on, and a short-circuit current is passed from the load to GND through D1 and N2. At this time, the high-side device N1 is in an off state. D1 is required to have a capability of flowing a sufficient forward current commensurate with the energization capability of N2. Therefore, when this is taken into consideration, the occupied area of the element of D1 becomes wider than D2 which functions as a simple protection diode. However, since an n-channel MOSFET is conventionally used for N2, the occupied area of D1 may be about 20% of the occupied area of the n-channel MOSFET conventionally used as N2.
[0009]
[Problems to be solved by the invention]
In recent years, when the IGBT is applied to the low-side device N2 as shown in FIG. 9, a larger current is also required for the forward current of D1.
The IGBT's current-carrying capacity is slightly more than five times that of the n-channel MOSFET having the same occupation area. Accordingly, since the occupied area of D1 necessary for flowing the current of more than five times is substantially the same as the occupied area of the IGBT, the chip area of the power IC is increased and the cost is increased.
[0010]
In the lateral diode of FIG. 7, the anode-cathode distance is short, the electrical resistance is relatively low, and the high-density current flows in the lateral direction through the p-type diffusion region 2a having a shallow diffusion depth. easy. On the other hand, in order to prevent breakdown, it is necessary to reduce the current density. For this purpose, an occupied area larger than that of the IGBT is required, which increases the cost.
[0011]
Further, in the lateral diode shown in FIG. 8, the introduction of the n diffusion region 7 causes the current path to spread not only near the surface but also relatively inside the n ⁻ substrate 1, so that it is difficult to break, but the breakdown voltage during reverse bias is n ^- constraints come out of the control of determined by the concentration of the substrate 1.
An object of the present invention is to solve the above-mentioned problems and to provide a lateral diode that can be easily set to a breakdown voltage, is difficult to break down, and is integrated in a low-cost power IC.
[0012]
[Means for Solving the Problems]
In order to solve this problem, the first diffusion region and the second diffusion region made of the second conductive type having a medium concentration are selectively formed on the surface layer of the semiconductor substrate made of the first conductive type having a low concentration. In addition, a third diffusion region made of the first conductivity type having a medium concentration is selectively formed apart from the first diffusion region and the second diffusion region on the surface layer of the semiconductor substrate made of the low concentration first conductivity type. A first region having a high concentration of the second conductivity type is formed on the surface layer of the first diffusion region, and a second region having the high concentration of the first conductivity type is formed on the surface layer of the second diffusion region. A third region having a high concentration of the first conductivity type is formed on the surface layer of the third diffusion region, and the first, second, and third electrodes are formed on the surfaces of the first, second, and third regions, respectively. Are formed, and the second electrode and the third electrode are connected to each other.
[0013]
As described above, by providing the second diffusion region and the second region, the breakdown voltage can be arbitrarily set by changing the concentration of the second diffusion region. Further, the current-carrying capacity can be improved by passing a current through this region. Further, since current flows through the semiconductor substrate, current concentration does not occur in the surface layer, and the element is not easily destroyed.
A fourth region (buffer region) made of the first conductivity type with a high concentration may be formed in the surface layer of the semiconductor substrate sandwiched between the first diffusion region and the second diffusion region.
[0014]
By doing so, carrier injection from the first diffusion region of the parasitic thyristor formed by the first diffusion region-semiconductor substrate-second diffusion region-second region is suppressed, and latch-up is prevented.
It is also effective if a resistor is connected between the second electrode and the third electrode. These electrodes are preferably connected with a material having resistance. The second electrode may be formed of a material having resistance. Moreover, it is preferable that a material having resistance be interposed between the second electrode and the second region. The material having the resistance may be polysilicon.
[0015]
By doing so, the current flowing through the parasitic thyristor is suppressed, thereby preventing latch-up.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a cross-sectional view of an essential part of a lateral diode according to a first embodiment of the present invention.
In FIG. 1, the first p diffusion region 2 and the second p diffusion region 11 having a medium concentration are formed in contact with the surface layer of the n ⁻ substrate 1, which is a low concentration n-type semiconductor substrate. A second n ⁺ region 12 is formed in the surface layer of the second p diffusion region 11. The n diffusion region 7 is selectively formed on the surface layer of the n ⁻ substrate 1 without contacting the first p diffusion region 2 and the second p diffusion region 11, and the first n ⁺ region 3 is formed on the surface layer of the n diffusion region 7. Is done. A p ⁺ region 4 is formed in the surface layer of the first p diffusion region 2. First n ⁺ region 3, second n ⁺ region 12 and p ⁺ region 4 are connected to metal electrodes 5, 13 and 6, respectively. The metal electrodes 5 and 13 are connected to the cathode terminal K, and the metal electrode 6 is connected to the anode terminal A. Here, the second p diffusion region 11 does not directly contact the metal electrode. In an actual element, there are a surface protective film, an element isolation region, and the like, but since they are not directly related to the present invention, description thereof is omitted here.
[0017]
A lateral diode with this structure can be manufactured using basic LSI manufacturing technology. In this trial manufacture, each element formation area was secured on the bonded SOI wafer by dielectric separation technology, and a plurality of horizontal diodes having different manufacturing specifications such as a mask pattern were formed in the element formation area. A semiconductor region for forming elements on the SOI wafer has a thickness of 10 μm and an impurity concentration of 3 × 10 ¹⁴ atoms / cm ³ , and this region becomes the n ⁻ substrate 1. First, n-type impurities are selectively introduced into the surface of the n ⁻ substrate 1 by ion implantation and finally diffused by about 5 μm by heat treatment to form an n diffusion region 7. The impurity concentration on the surface of the n diffusion region 7 is 6 × 10 ¹⁷ atoms / cm ³ . Similarly, the first p diffusion region 2 and the second p diffusion region 11 are formed by selectively ion-implanting p-type impurities into the surface of the n ⁻ substrate 1 and performing heat treatment to diffuse 2 μm in the depth direction. To do. In consideration of diffusion in the lateral direction, an interval of about 1.2 μm is provided so that the two p diffusion regions 2 and 11 do not contact each other. These impurity concentrations were set to 5 × 10 ¹⁸ atoms / cm ³ . A first n ⁺ region 3 and a second n ⁺ region 12 having a depth of about 0.4 μm are formed on the surfaces of the n diffusion region and the second p diffusion region. A p ⁺ region 4 having a depth of about 0.4 μm is formed. These three regions 3, 12, and 4 have an impurity concentration of about 1 × 10 ²⁰ atoms / cm ³ so that electrical contact with an electrode formed of aluminum or the like is good. The electrodes 5 and 13 are connected to the cathode terminal K of the lateral diode, and the electrode 6 is connected to the anode terminal A. The manufacturing conditions shown here are merely examples, and the planar pattern of the lateral diode is not shown, but there are various types such as a circle, a rectangle, and a waveform depending on application.
[0018]
Next, the operation of this lateral diode will be described. When a reverse bias is applied (the anode terminal A is negative and the cathode terminal K is positive), the n ⁻ substrate 1 is contacted with the n ⁻ substrate 1 and the first p diffusion region 2 to the n ⁻ substrate 1 side where the concentration is low. The depletion layer extends and reaches the second p diffusion region 11 arranged at a distance of 1.2 μm at a very low voltage. After reaching, the second p diffusion region 11 and the first p diffusion region 2 behave as if they are electrically integrated. Therefore, from this stage, the same function as p diffusion region 2a of FIG. 7 is performed. When the reverse bias voltage is increased, the pn junction between the second p diffusion region 11 and the second n ⁺ region 12 which are reverse biased causes an avalanche phenomenon. Due to this avalanche phenomenon, avalanche carriers are generated, electrons flow to the cathode electrode K side, and holes flow to the anode electrode A side while accelerating in the depletion layer. Since the breakdown voltage causing this avalanche is determined by the impurity concentration of the second p diffusion region 11, the breakdown voltage can be arbitrarily set by changing this concentration.
[0019]
On the other hand, when forward bias is applied (the anode terminal A is positive and the cathode terminal K is negative), at a low current density, the pn junction between the n ⁻ substrate 1 and the first p diffusion region 2 is forward biased and the first p diffusion region 2-n ^- a forward current flows in the path of the substrate 1-n diffusion region 7.
As the forward bias voltage is increased and the current density is increased, conductivity modulation in the n ⁻ substrate 1 proceeds and holes that are minority carriers are filled in the n ⁻ substrate 1. Most of the holes become current components to the n diffusion region 7, but some of them enter the second p diffusion region 11 and flow out as current to the electrode 13 side. At this time, since the current path flows not in the vicinity of the surface but in the n ⁻ substrate 1 in a relatively deep portion, unlike the lateral diode as shown in FIG. 7, there is no breakdown due to current concentration in the surface layer. In addition, since part of the current also flows into the electrode 13, the on-voltage is lower than that of the conventional lateral diode having the structure shown in FIG. The lateral diode has a parasitic thyristor having a pnpn structure including a first p diffusion region 2-n ^- substrate 1-second p diffusion region 11-second n ⁺ region 12, but a current range in which the parasitic thyristor does not operate. Operate with.
[0020]
FIG. 2 is a current-voltage characteristic diagram when forward-biased. FIG. 2A shows the product of the present invention, and FIG. 2B shows the conventional product of FIG. In the figure, the horizontal axis represents the forward bias voltage VAK (same as the ON voltage), and the vertical axis represents the forward current IAK.
In FIG. 2, in this characteristic diagram, when the forward bias voltage is about 2 V, the conventional product has a forward current of about 10 A / cm ² , but in the case of the present product, it is about 1.6 times 32 A / cm ^2. It was confirmed that the current-carrying capacity was improved by providing the second p diffusion region 11 and the second n ⁺ region 12 with a current density of about a level. Therefore, by using the product of the present invention, the area occupied by the lateral diode is made about one-third of the occupied area of the IGBT, regardless of whether N2 in FIG. 9 is an IGBT or a N2 gate protection diode. Can do.
[0021]
FIG. 3 is a schematic diagram showing the flow of holes and electrons when the lateral diode having the structure of FIG. 1 is forward-biased. First, the anode terminal A is biased positive and the cathode terminal K is biased negative. Holes are injected from the first p diffusion region 2 into the n ⁻ substrate 1, and electrons are injected from the n diffusion region 7 into the n ⁻ substrate 1 so as to neutralize the holes, and the conductivity inside the n ⁻ substrate 1 is modulated. And a current flows through the lateral diode with a low on-voltage. When this current increases, some of the holes injected into the n ⁻ substrate 1 enter the second p diffusion region 11, raise the potential of the second p diffusion region 11, and inject electrons from the n ⁺ region 12. The electrons pass through the second p diffusion region 11 and enter the n ⁻ substrate 1. There are two paths, a path through which the current exits from the second n ⁺ region 3 and a path through which the current exits from the n ⁺ region 12, so that a large current can flow. In the conventional structure as shown in FIG. 7, the current path flows only on the surface, but in the lateral diode of FIG. 1, current flows on the surface because it flows through the n ⁻ substrate 1. Compared with the conventional structure of FIG. 8, the current flows through the second p diffusion region 11 -n ⁺ region 12 and also to the electrode 13, so the on-voltage is lowered. Further, the avalanche voltage can be arbitrarily determined by the concentration of the first p diffusion region 11 as in the conventional structure of FIG.
[0022]
FIG. 4 is an enlarged view showing the flow of holes in the simulation when the lateral diode of FIG. 1 is forward-biased. The enlarged view is the enlarged portion shown in FIG. 3, the direction of the arrow indicates the direction in which holes flow, and the length indicates the magnitude of the hole flow. From the figure, it can be seen that holes flow into the second p diffusion region 11 and are not concentrated in the surface layer.
[0023]
FIG. 5 is a sectional view showing the principal part of a lateral diode according to the second embodiment of the present invention. In order to prevent the parasitic thyristor having the pnpn structure formed by the first p diffusion region 2-n type semiconductor substrate 1-second p diffusion region 11-n ⁺ region 12 from operating, the lateral diode is provided with the first p diffusion region 2 An n ⁺ buffer region 15 is formed in the surface layer of the n ⁻ substrate 1 between the first p diffusion region 11 and the second p diffusion region 11. As a result, the efficiency of hole injection from the first p diffusion region 2 of the parasitic thyristor is reduced, latch-up is prevented, and the pulse current resistance is improved. The n ⁺ buffer region 15 may enter the first and second p diffusion regions 2 and 11. In that case, the effect is the same.
[0024]
FIG. 6 is a diagram of a lateral diode according to a third embodiment of the present invention. A resistor 14 of about 3Ω is inserted between the metal electrode 13 and the metal electrode 5 in FIG. 1 to suppress the current flowing out of the metal electrode 13 to prevent the parasitic thyristor from being latched up and to increase the pulse current resistance. Improve. As for the resistor 14, the metal electrode 13 itself may be formed of polysilicon or the like, or the metal electrode 13 and the metal electrode 5 may be wired with polysilicon, and this wiring may be used as the resistance.
[0025]
Further, the effect can be further enhanced by combining the second embodiment and the third embodiment.
The lateral diode of the present invention is a gate protection diode connected between the gate and source of the MOS device so that an excessive voltage is not applied to the gate of the MOS device (N1, P1) used in the totem pole circuit of FIG. Used as (D1 and D2). When an excessive voltage is applied between the gate and the source of the MOS device, the lateral diode is inserted into the gate and the source so as to cause an avalanche (breakdown). For example, in the case of an n-channel device, the gate is connected to the cathode of the lateral diode, and the source is connected to the anode of the lateral diode. On the other hand, in the case of a p-channel device, the gate is connected to the anode of the lateral diode, and the source is connected to the cathode of the lateral diode.
[0026]
【The invention's effect】
According to the present invention, by providing the second p diffusion region and the second n ⁺ region, the current concentration on the surface is suppressed, and the current flows from this region to the cathode terminal, thereby improving the current carrying capacity. As a result, the area occupied by the lateral diode can be reduced, and the element is difficult to be destroyed. Further, by providing an n ⁺ buffer region or inserting a resistor between the metal electrodes 12 and 5, the parasitic thyristor is prevented from being latched up, and the pulse current resistance can be improved. Furthermore, the breakdown voltage, which is an important characteristic for the protective diode, can be easily set. By using this lateral diode for gate protection of, for example, a MOS device that constitutes a totem pole circuit, a highly reliable and inexpensive power IC can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a main part of a lateral diode according to a first embodiment of the present invention. FIG. 2 is a current-voltage characteristic diagram when forward-biased. FIG. ) Is a characteristic diagram of the conventional product of FIG. 8. [FIG. 3] A schematic diagram showing the flow of holes and electrons when the lateral diode of the structure of FIG. 1 is forward biased. [FIG. 4] FIG. FIG. 5 is a cross-sectional view of the principal part of a lateral diode according to a second embodiment of the present invention. FIG. 6 is a diagram of a lateral diode according to a third embodiment of the present invention. 7 is a cross-sectional view of a main part of a conventional protection diode. FIG. 8 is a cross-sectional view of a main part of another conventional protection diode. FIG. 9 is a driving circuit and an output stage of a totem pole circuit as an application example of the protection diode. Diagram showing the circuit 【Explanation of symbols】
1 n ⁻ substrate 2 1 p diffusion region 2 a p diffusion region 2 b p diffusion region 3 1 n ⁺ region 3 a n ⁺ region 4 p ⁺ region 5 metal electrode 6 metal electrode 7 n diffusion region 11 second p diffusion region 12 second n ⁺ region 13 Metal electrode 14 Resistance 21 Load 31 Drive circuit 32 Output stage circuit N1 n-channel MOSFET
N2 n-channel IGBT
N3 n-channel MOSFET
P1 p-channel MOSFET
D1 Protection diode D2 Protection diode R1 Gate resistance R2 Limit resistance R3 Gate resistance R4 Limit resistance IN1 Input 1
IN2 input 2
VDD High voltage power supply OUT Output terminal GND Ground A Anode terminal K Cathode terminal I1 Current I2 Current

Claims (7)

A first diffusion region and a second diffusion region made of a medium-concentration second conductivity type are selectively formed on the surface layer of the semiconductor substrate made of the low-concentration first conductivity type, and the low-concentration first conductivity is formed. A third diffusion region having a first conductivity type having a medium concentration is selectively formed apart from the first diffusion region and the second diffusion region in a surface layer of the semiconductor substrate having a shape; and a surface of the first diffusion region A first region having a high concentration of the second conductivity type is formed in the layer; a second region of the high concentration of the first conductivity type is formed in a surface layer of the second diffusion region; and the surface of the third diffusion region A third region having a first conductivity type with a high concentration is formed in the layer, and first, second, and third electrodes are respectively formed on surfaces of the first, second, and third regions, and the second electrode And a third electrode are connected to each other. 2. The lateral type according to claim 1, wherein a fourth region (buffer region) made of a high-concentration first conductivity type is formed in a surface layer of the semiconductor substrate sandwiched between the first diffusion region and the second diffusion region. diode. The lateral diode according to claim 1, wherein a resistor is connected between the second electrode and the third electrode. 4. The lateral diode according to claim 3, wherein the second electrode and the third electrode are connected by a material having resistance. 2. The lateral diode according to claim 1, wherein the second electrode is made of a material having resistance. The lateral diode according to claim 1, wherein a material having resistance is interposed between the second electrode and the second region. 7. A lateral diode according to claim 4, wherein the material having resistance is polysilicon.

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