JPH0314224B2 - - Google Patents
Info
- Publication number
- JPH0314224B2 JPH0314224B2 JP58152742A JP15274283A JPH0314224B2 JP H0314224 B2 JPH0314224 B2 JP H0314224B2 JP 58152742 A JP58152742 A JP 58152742A JP 15274283 A JP15274283 A JP 15274283A JP H0314224 B2 JPH0314224 B2 JP H0314224B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- electrode
- base
- terminal
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000013070 direct material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明はベース電流制限用のベース抵抗を内蔵
した縦方向PNPトランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a vertical PNP transistor having a built-in base resistor for limiting base current.
従来縦方向PNPトランジスタのベースに抵抗
を付加するには、PNPトランジスタチツプに抵
抗体を接続したハイブリツド型がほとんどであつ
た。そのため接続工数が必要となり直材費も高く
なる。
Conventionally, in order to add a resistor to the base of a vertical PNP transistor, most of the transistors were of a hybrid type, in which a resistor was connected to the PNP transistor chip. Therefore, additional man-hours are required for connection, and direct material costs also increase.
本発明は、抵抗体の接続の必要がないベース抵
抗を同一チツプに内蔵した縦方向PNPトランジ
スタを提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a vertical PNP transistor in which a base resistor that does not require connection of a resistor is built into the same chip.
本発明はＰ型半導体基板内に第一のＮ領域と第
二のＮ領域が、第一のＮ領域内に第二のＰ領域が
第二のＮ領域内に第三のＰ領域がそれぞれ形成さ
れ、基板本来の第一のＰ領域、第二のＰ領域、第
一、第二のＮ領域はそれぞれ一つのオーム接触電
極を、第三のＰ領域は離れて位置する二つのオー
ム接触電極をそれぞれ有し、第一のＰ領域の電極
はコレクタ端子に、第二のＰ領域の電極はエミツ
タ端子に、第三のＰ領域の一方の電極はベース端
子に、前記第二のＮ領域の電極は前記ベース端子
の電位が前記エミツタ端子の電位より高くなると
前記第三のＰ領域から前記第二のＮ領域を介して
電流が流れるように前記エミツタ端子に接続さ
れ、かつ第一のＮ領域の電極と第三のＰ領域の他
方の電極が相互に接続されていることによつて上
記の目的を達成する。
In the present invention, a first N region and a second N region are formed in a P-type semiconductor substrate, a second P region is formed in the first N region, and a third P region is formed in the second N region. The first P region, the second P region, and the first and second N regions of the substrate each have one ohmic contact electrode, and the third P region has two ohmic contact electrodes located apart. The electrode of the first P region serves as a collector terminal, the electrode of the second P region serves as an emitter terminal, one electrode of the third P region serves as a base terminal, and the electrode of the second N region serves as a base terminal. is connected to the emitter terminal such that a current flows from the third P region through the second N region when the potential of the base terminal becomes higher than the potential of the emitter terminal, and The above object is achieved by interconnecting the electrode and the other electrode of the third P region.
第１図は本発明の一実施例を示し、Ｐ形シリコ
ン基板１内に二つのＮ領域２，３が上面からの選
択拡散により形成されている。さらにＮ領域２，
３の内部には再び上面からの選択拡散によりＰ領
域４，５が形成されている。このＰ形基板の本来
のＰ領域１をコレクタ領域、Ｎ領域２をベース領
域、Ｐ領域４をエミツタ領域としてPNPトラン
ジスタを構成し、Ｐ領域５によつてベース抵抗を
構成する。すなわちＰ領域５に間隔を置いた二つ
の電極６，７をオーム接触させ、ベース領域２に
N+領域２１を介してオーム接触する電極８と電
極７とを接続する。このようにしてＰ領域４の電
極９をエミツタ端子Ｅに、Ｐ領域５の電極６をベ
ース端子Ｂに、基板１にP+層１１を介して接触
する電極１０をコレクタ端子Ｃに接続すればベー
ス抵抗１２を内蔵するPNPトランジスタができ
上がるが、ベース端子Ｂとエミツタ端子Ｅに逆電
圧が加わつた場合にベース・エミツタ接合を保護
するべく、Ｐ領域５からＮ領域３を介してエミツ
タ端子に電流が流れるようにするために、Ｎ領域
３にN+領域３１を介して接触する電極１３をエ
ミツタ端子Ｅと接続する。Ｐ領域５は通常の動作
状態では抵抗として、またベース端子Ｂとエミツ
ク端子Ｅに逆電圧が加わつた場合には入力保護ダ
イオードのアノードとして働くことになる。この
結果得られたPNPトランジスタの等価回路は第
２図に示した通りで、二つの寄生ダイオード１
４，１５が形成される。寄生ダイオード１４のア
ノードは、Ｐ領域５が兼ねている。
FIG. 1 shows an embodiment of the present invention, in which two N regions 2 and 3 are formed in a P-type silicon substrate 1 by selective diffusion from the top surface. Furthermore, N area 2,
P regions 4 and 5 are again formed inside P regions 3 by selective diffusion from the upper surface. A PNP transistor is constructed by using the original P region 1 of this P type substrate as a collector region, the N region 2 as a base region, and the P region 4 as an emitter region, and the P region 5 as a base resistor. That is, two electrodes 6 and 7 spaced apart from each other are brought into ohmic contact with the P region 5, and the base region 2 is connected to the base region 2.
Electrode 8 and electrode 7 are connected through N + region 21 in ohmic contact. In this way, the electrode 9 of the P region 4 is connected to the emitter terminal E, the electrode 6 of the P region 5 is connected to the base terminal B, and the electrode 10 that contacts the substrate 1 via the P + layer 11 is connected to the collector terminal C. A PNP transistor with a built-in base resistor 12 is completed, but in order to protect the base-emitter junction when a reverse voltage is applied to the base terminal B and emitter terminal E, current flows from the P region 5 to the emitter terminal via the N region 3. An electrode 13 that contacts the N region 3 via the N + region 31 is connected to the emitter terminal E in order to allow the current to flow. P region 5 acts as a resistor under normal operating conditions and as an anode of an input protection diode when a reverse voltage is applied to base terminal B and emitter terminal E. The resulting equivalent circuit of the PNP transistor is shown in Figure 2, with two parasitic diodes 1
4 and 15 are formed. P region 5 also serves as the anode of parasitic diode 14.
本発明は縦方向PNPトランジスタのＰ形基板
に別にＮ領域に囲まれたＰ形の抵抗領域を形成し
ベース領域に接続してベース抵抗として内蔵させ
ると共に、抵抗領域とこれを囲むＮ領域で入力保
護ダイオードを兼ねるようにしたもので、抵抗内
蔵のため外部接続の必要がなく、しかもトランジ
スタ各領域の形成と同一工程で形成できるため工
数および直材原価の低減と信頼性の向上が達せら
れる。
The present invention separately forms a P-type resistance region surrounded by an N region on the P-type substrate of a vertical PNP transistor, connects it to the base region and incorporates it as a base resistor, and inputs the resistance region and the N region surrounding it. It is designed to also function as a protection diode, and since it has a built-in resistor, there is no need for external connections.Furthermore, it can be formed in the same process as forming each transistor region, reducing man-hours and direct material costs, and improving reliability.
第１図は本発明の一実施例の断面図、第２図は
その等価回路図である。
１……Ｐ形基板、２……ベース領域、４……エ
ミツタ領域、５……ベース抵抗領域、１２……ベ
ース抵抗。
FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. DESCRIPTION OF SYMBOLS 1...P-type substrate, 2...Base region, 4...Emitter region, 5...Base resistance region, 12...Base resistance.
Claims (1)
領域が、第一のＮ領域内に第二のＰ領域が、第二
のＮ領域内に第三のＰ領域がそれぞれ形成され、
基板本来のＰ領域、第二のＰ領域、第一、第二の
Ｎ領域はそれぞれ一つのオーム接触電極を、第三
のＰ領域は離れて位置する二つのオーム接触電極
をそれぞれ有し、第一のＰ領域の電極はコレクタ
端子に、第二のＰ領域の電極はエミツタ端子に、
第三のＰ領域の一方の電極はベース端子に、前記
第二のＮ領域の電極は前記ベース端子の電位が前
記エミツタ端子の電位より高くなると前記第三の
Ｐ領域から前記第二のＮ領域を介して電流が流れ
るように前記エミツタ端子にそれぞれ接続され、
かつ第一のＮ領域の電極と第三のＰ領域の他方の
電極が相互に接続されたことを特徴とする縦方向
PNPトランジスタ。1 A first N region and a second N region in a P-type semiconductor substrate.
a second P region is formed within the first N region, and a third P region is formed within the second N region;
The original P region of the substrate, the second P region, the first and second N regions each have one ohmic contact electrode, and the third P region each has two ohmic contact electrodes located apart. The electrode of the first P region is the collector terminal, the electrode of the second P region is the emitter terminal,
One electrode of the third P region becomes a base terminal, and the electrode of the second N region moves from the third P region to the second N region when the potential of the base terminal becomes higher than the potential of the emitter terminal. are respectively connected to the emitter terminals so that a current flows through them,
and a longitudinal direction characterized in that the electrode of the first N region and the other electrode of the third P region are connected to each other.
PNP transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15274283A JPS6045061A (en) | 1983-08-22 | 1983-08-22 | Vertical p-n-p transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15274283A JPS6045061A (en) | 1983-08-22 | 1983-08-22 | Vertical p-n-p transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6045061A JPS6045061A (en) | 1985-03-11 |
| JPH0314224B2 true JPH0314224B2 (en) | 1991-02-26 |
Family
ID=15547162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15274283A Granted JPS6045061A (en) | 1983-08-22 | 1983-08-22 | Vertical p-n-p transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6045061A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010048140A1 (en) | 1997-04-10 | 2001-12-06 | Inao Toyoda | Photo sensing integrated circuit device and related circuit adjustment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5242386A (en) * | 1975-09-30 | 1977-04-01 | Nec Corp | Semiconducteor device |
-
1983
- 1983-08-22 JP JP15274283A patent/JPS6045061A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5242386A (en) * | 1975-09-30 | 1977-04-01 | Nec Corp | Semiconducteor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6045061A (en) | 1985-03-11 |
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