JPH0110937Y2 - - Google Patents

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Publication number
JPH0110937Y2
JPH0110937Y2 JP3335482U JP3335482U JPH0110937Y2 JP H0110937 Y2 JPH0110937 Y2 JP H0110937Y2 JP 3335482 U JP3335482 U JP 3335482U JP 3335482 U JP3335482 U JP 3335482U JP H0110937 Y2 JPH0110937 Y2 JP H0110937Y2
Authority
JP
Japan
Prior art keywords
contact
resistor
type
region
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3335482U
Other languages
Japanese (ja)
Other versions
JPS58135964U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3335482U priority Critical patent/JPS58135964U/en
Publication of JPS58135964U publication Critical patent/JPS58135964U/en
Application granted granted Critical
Publication of JPH0110937Y2 publication Critical patent/JPH0110937Y2/ja
Granted legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Elimination Of Static Electricity (AREA)

Description

【考案の詳細な説明】 本考案は半導体装置に関し、特に半導体抵抗と
してその一端が外部端子に他の素子を介さずに直
接接続されており、さらにこの抵抗素子が形成さ
れている半導体層が所定電位の外部端子に他の素
子を介さずに直接接続されている構造のものを有
する半導体集積回路装置に関するものである。
[Detailed description of the invention] The present invention relates to a semiconductor device, in particular a semiconductor resistor, one end of which is directly connected to an external terminal without intervening other elements, and furthermore, the semiconductor layer on which this resistor element is formed is connected to a predetermined area. The present invention relates to a semiconductor integrated circuit device having a structure in which it is directly connected to an external potential terminal without using other elements.

半導体集積回路装置における抵抗素子は、一般
にN型エピタキシヤル層に形成されたP型領域に
より構成されるが、これらを電気的に分離するた
めに通常はそのエピタキシヤル層は高電位(例え
ば電源電圧)に接続されている。ところが、この
エピタキシヤル層を高電位に接続している部分
(以下、この部分をC1と呼ぶ)が外部端子に直
接接続されており(以下この外部端子をT1と呼
ぶ)、さらに、このエピタキシヤル層中に配置さ
れたP型拡散抵抗領域のコンタクト部の一端が外
部端子に直接接続されていると(以下、このコン
タクト部をC2、外部端子をT2とそれぞれ呼
ぶ)、T1を正、T2を負とした極性の静電気に
より破壊してしまう場合がある。その静電気破壊
のレベルが、メーカーの製造工程から製品として
出荷されてユーザーでの実装工程迄の間で遭過す
る周囲環境及び人体からの静電気のレベルを下ま
わると問題となる。
A resistive element in a semiconductor integrated circuit device is generally composed of a P-type region formed in an N-type epitaxial layer, but in order to electrically isolate these regions, the epitaxial layer is usually kept at a high potential (for example, at a power supply voltage). )It is connected to the. However, the part that connects this epitaxial layer to a high potential (hereinafter this part will be referred to as C1) is directly connected to an external terminal (hereinafter this external terminal will be referred to as T1), and furthermore, this epitaxial layer If one end of the contact portion of the P-type diffused resistance region arranged in the layer is directly connected to the external terminal (hereinafter, this contact portion will be referred to as C2 and the external terminal as T2), T1 is positive and T2 is It may be destroyed by negative polarity static electricity. A problem arises when the level of static electricity damage is lower than the level of static electricity from the surrounding environment and the human body that is encountered during the manufacturing process at the manufacturer, shipping as a product, and the mounting process at the user.

それ故、静電気破壊レベルを向上させるため
に、従来はエピタキシヤル層およびP型拡散抵抗
の接合とP型拡散抵抗のコンタクトとの距離を十
分にとることにより対処していた。しかし、この
ような対策を施したP型拡散抵抗と回路特性の都
合から相対精度をとる必要のある抵抗が存在する
場合、この相対精度を必要とする抵抗のコンタク
ト部も前記の対策をする必要が生じ、このために
その数が多い場合にはペレツト面積の増大につな
がる恐れがあり、またパターン設計が繁雑にな
る。
Therefore, in order to improve the level of electrostatic damage, conventional measures have been taken by providing a sufficient distance between the junction of the epitaxial layer and the P-type diffused resistor and the contact of the P-type diffused resistor. However, if there is a P-type diffused resistor that has taken such measures and a resistor that requires relative accuracy due to circuit characteristics, the contact part of the resistor that requires this relative accuracy must also take the above measures. If the number of pellets is large, the pellet area may increase and the pattern design becomes complicated.

本考案の目的は、ペレツト面積をできるだけお
さえて静電破壊に強い抵抗素子を有する半導体装
置を提供することにある。
An object of the present invention is to provide a semiconductor device having a resistive element that is resistant to electrostatic damage while minimizing the pellet area.

本考案によれば、半導体抵抗のコンタクト部と
この抵抗が形成された半導体層のコンタクト部と
の間の半導体層に抵抗領域と同じ導電型の領域を
設け、さらにこの領域に設けられたコンタクト部
と抵抗領域のコンタクト部とを短絡した半導体装
置が得られる。この構造によれば、抵抗領域以外
の領域の存在により静電気が直接抵抗領域のPN
接合に印加されることがないので、抵抗領域の接
合部と抵抗のコンタクトとの距離を長くとること
なく静電気破壊強度を向上させることが出来る。
当然のことながら、間に設ける領域の静電気破壊
強度は十分に大きいものとする。また、この領域
は、拡散抵抗あるいは絶縁分離領域等の抵抗領域
と同じ導電型ならいずれを用いてもよいが、拡散
抵抗に比べて濃度の高いものの効果が大きい。
According to the present invention, a region of the same conductivity type as the resistor region is provided in the semiconductor layer between the contact portion of the semiconductor resistor and the contact portion of the semiconductor layer in which this resistor is formed, and the contact portion provided in this region is further provided. A semiconductor device is obtained in which the contact portion of the resistance region and the contact portion of the resistance region are short-circuited. According to this structure, due to the existence of a region other than the resistance region, static electricity is directly applied to the PN of the resistance region.
Since no voltage is applied to the junction, the electrostatic breakdown strength can be improved without increasing the distance between the junction of the resistor region and the contact of the resistor.
Naturally, it is assumed that the electrostatic breakdown strength of the region provided between the two is sufficiently large. Further, this region may be made of any conductivity type that is the same as that of the resistance region such as the diffused resistor or the insulation isolation region, but the effect is greater if the concentration is higher than that of the diffused resistor.

以下に図面を用いて本考案をより詳細に説明す
る。
The present invention will be explained in more detail below using the drawings.

第1図は従来の半導体集積回路装置のP型拡散
抵抗附近の一例を示す断面図及び平面図である。
P型基板1上に成長させたN型エピタキシヤル層
2にP型拡散抵抗3が、その下部にはN+埋込層
4がそれぞれ配置されている。P型拡散抵抗3上
の酸化ケイ素膜5の一部を除去してコンタクト6
が設けられ、その上の金属配線7とボンデイング
線8を経て外部端子に接続されている。また、エ
ピタキシヤル層2には高濃度N拡散層9が形成さ
れ、この上の酸化ケイ素膜5の一部を除去してコ
ンタクト10が設けられ、その上の金属配線11
とボンデイング線12を経て外部端子に接続され
ている。
FIG. 1 is a cross-sectional view and a plan view showing an example of the vicinity of a P-type diffused resistor of a conventional semiconductor integrated circuit device.
A P-type diffused resistor 3 is disposed in an N-type epitaxial layer 2 grown on a P-type substrate 1, and an N + buried layer 4 is disposed below it. A part of the silicon oxide film 5 on the P-type diffused resistor 3 is removed to form a contact 6.
is provided and connected to an external terminal via metal wiring 7 and bonding wire 8 thereon. Further, a high concentration N diffusion layer 9 is formed in the epitaxial layer 2, and a contact 10 is provided by removing a portion of the silicon oxide film 5 thereon, and a metal wiring 11 thereon is formed.
and is connected to an external terminal via a bonding wire 12.

上記の構造を有する半導体集積回路装置におい
て、コンタクト10を正、P型拡散抵抗3の外部
端子側のコンタクト6を負とした極性の静電気が
印加されると、静電気は13又は14に示すよう
な経路で抜ける。通常は、N+埋込層4の層抵抗
が低い為に13方向に静電気は加わりやすいが、
13方向の静電気破壊強度が14方向の静電気破
壊強度に比べて強い場合は14方向における破壊
が問題となり、その強度を上げる為にN型エピタ
キシヤル層2とP型拡散抵抗3のジヤンクシヨン
からコンタクト6までの距離Aを長くする場合が
あつた。これでは、コンタクト6が設けられる部
分の領域も抵抗として寄与し、かつこれと抵抗比
を精度よくとる必要のある抵抗も同じように形成
する必要がある。
In the semiconductor integrated circuit device having the above structure, when static electricity is applied with a polarity such that the contact 10 is positive and the contact 6 on the external terminal side of the P-type diffused resistor 3 is negative, the static electricity will be as shown in 13 or 14. Exit by route. Normally, static electricity is easily applied in the 13 directions because the layer resistance of the N + buried layer 4 is low.
If the electrostatic breakdown strength in the 13th direction is stronger than the electrostatic breakdown strength in the 14th direction, the breakdown in the 14th direction becomes a problem, and in order to increase the strength, the contact 6 is There were cases where the distance A was made longer. In this case, the region where the contact 6 is provided also contributes as a resistor, and a resistor that needs to have a precisely controlled resistance ratio with this region also needs to be formed in the same way.

第2図は本考案の一実施例を示した断面図及び
平面図であり、第1図と同一番号のものは、同一
機能を示す。この図からわかるように、P型拡散
抵抗3と高濃度N拡散層9との間にP型拡散層1
5を設けてあり、さらに、このP型拡散層15上
の酸化ケイ素膜5の一部を除去してコンタクト1
6が設けられて金属配線7によりコンタクト6と
短絡されている。従つて、コンタクト10を正、
P型拡散抵抗3の外部端子側のコンタクト6を負
とした極性の静電気が印加された場合の静電気破
壊経路は13及び17方向である。14方向と1
7方向を比較した場合、コンタクト10からコン
タクト16への直列抵抗は、コンタクト10から
コンタクト16への直列抵抗より小さい為、14
方向には静電気はほとんど加わらない。従つて、
コンタクト6の部分からN型エピタキシヤル層2
とP型拡散抵抗のジヤンクシヨンまでの距離A長
くする必要はなくなる。当然のことながら間に設
けるP型拡散層15はそのコンタクト面積を十分
にとる、P型拡散層15とN型エピタキシヤル層
のジヤンクシヨンからP型拡散層15のコンタク
ト16までの距離を十分にとる等の配慮により十
分な静電気破壊強度をもつものとする。よつて、
該P型拡散抵抗3と相対精度を必要とする抵抗が
多数存在してもそのコンタクト部に特別な配慮な
く設計が可能である。
FIG. 2 is a sectional view and a plan view showing an embodiment of the present invention, and the same numbers as in FIG. 1 indicate the same functions. As can be seen from this figure, a P-type diffused layer 1 is located between the P-type diffused resistor 3 and the high concentration N diffused layer 9.
Further, a part of the silicon oxide film 5 on this P type diffusion layer 15 is removed to form a contact 1.
6 is provided and short-circuited to the contact 6 by a metal wiring 7. Therefore, the contact 10 is
When static electricity with a negative polarity is applied to the contact 6 on the external terminal side of the P-type diffused resistor 3, the electrostatic breakdown paths are in directions 13 and 17. 14 directions and 1
When comparing seven directions, the series resistance from contact 10 to contact 16 is smaller than the series resistance from contact 10 to contact 16, so 14
Almost no static electricity is applied in this direction. Therefore,
N-type epitaxial layer 2 from the contact 6 part
It is no longer necessary to increase the distance A between the P-type diffused resistor and the junction. Naturally, the P-type diffusion layer 15 provided in between should have a sufficient contact area, and the distance from the junction between the P-type diffusion layer 15 and the N-type epitaxial layer to the contact 16 of the P-type diffusion layer 15 should be sufficient. It shall have sufficient electrostatic breakdown strength by considering the following. Then,
Even if there are a large number of resistors that require relative precision to the P-type diffused resistor 3, it is possible to design the contact portions without special consideration.

このように本考案はエピタキシヤル層を高電位
に接続している部分が外部端子に直接接続されて
おり、又エピタキシヤル層中にP型拡散抵抗が含
まれその一端のコンタクト部も外部端子に直接接
続されている場合、P型拡散抵抗のコンタクト部
と前記エピタキシヤル層を高電位に接続している
部分との間にさらにP型拡散層を設け、かつこの
P型拡散層とP型拡散抵抗のコンタクト部とを短
絡することを特徴とするが、この間に入れるP型
拡散層はP型拡散抵抗、絶縁P等のP型のものな
らいずれも用いてもよい。P型拡散抵抗に比べの
濃度の高いものの効果が大きい。またその位置
は、第2図の平面図の15′に示すようにコンタ
クト部を取り囲むように設計してもよい。
In this way, in the present invention, the part that connects the epitaxial layer to a high potential is directly connected to the external terminal, and the epitaxial layer includes a P-type diffused resistor, and the contact part at one end of the resistor is also connected to the external terminal. In the case of direct connection, a P-type diffusion layer is further provided between the contact part of the P-type diffused resistor and the part connecting the epitaxial layer to a high potential, and the P-type diffusion layer and the P-type diffusion Although the feature is that the contact portion of the resistor is short-circuited, the P-type diffusion layer interposed therebetween may be any P-type material such as a P-type diffused resistor or an insulating P layer. The effect of the higher concentration than that of P-type diffused resistance is large. Further, its position may be designed to surround the contact portion as shown at 15' in the plan view of FIG.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aは従来の半導体集積回路装置の拡散抵
抗附近の断面図、第1図bはその平面図、第2図
aは本考案の一実施例を示す断面図、第2図bは
その平面図である。 1……P型サブストレート(基板)、2……N
型エピタキシヤル層、3……P型拡散抵抗、4…
…N+埋込層、5……酸化ケイ素膜、6,10,
16……コンタクト、7,11……金属配線、
8,12……ボンデイング線、9……高濃度N拡
散層、13,14,17……静電気破壊経路、1
5,15′……P型拡散層。
FIG. 1a is a sectional view of a conventional semiconductor integrated circuit device near a diffused resistor, FIG. 1b is a plan view thereof, FIG. 2a is a sectional view showing an embodiment of the present invention, and FIG. FIG. 1...P type substrate (substrate), 2...N
type epitaxial layer, 3...P type diffused resistor, 4...
...N + buried layer, 5... silicon oxide film, 6, 10,
16...Contact, 7,11...Metal wiring,
8, 12... Bonding line, 9... High concentration N diffusion layer, 13, 14, 17... Static electricity breakdown path, 1
5,15'...P type diffusion layer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一導電型の半導体層に形成された他導電型の抵
抗領域を有し、該半導体層および該抵抗層に電圧
を供給するためのコンタクトがそれぞれ設けられ
ている半導体装置において、これら二つのコンタ
クトの間に他導電型の半導体領域を設け、該半導
体領域と前記抵抗領域のコンタクトを短絡するこ
とを特徴とする半導体装置。
In a semiconductor device having a resistive region of a different conductive type formed in a semiconductor layer of one conductive type, and contacts for supplying voltage to the semiconductor layer and the resistive layer, respectively, these two contacts are connected to each other. A semiconductor device characterized in that a semiconductor region of a different conductivity type is provided in between, and a contact between the semiconductor region and the resistor region is short-circuited.
JP3335482U 1982-03-10 1982-03-10 semiconductor equipment Granted JPS58135964U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3335482U JPS58135964U (en) 1982-03-10 1982-03-10 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3335482U JPS58135964U (en) 1982-03-10 1982-03-10 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS58135964U JPS58135964U (en) 1983-09-13
JPH0110937Y2 true JPH0110937Y2 (en) 1989-03-29

Family

ID=30044902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3335482U Granted JPS58135964U (en) 1982-03-10 1982-03-10 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS58135964U (en)

Also Published As

Publication number Publication date
JPS58135964U (en) 1983-09-13

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