JPS61276250A - Semiconductor device - Google Patents

Abstract

PURPOSE:To unify a bipolar transistor and a MOS transistor without increasing an element area, and to augment output currents by forming an emitter region in the bipolar transistor into a drain region in the MOS transistor and shaping an extremely thin oxide film and a first conduction type polycrystalline silicon layer onto the emitter region. CONSTITUTION:Reverse conduction type first and second semiconductor regions 5, 13 separated and formed in one conduction type semiconductor layer 3, a conductor layer 11 shaped onto the semiconductor layer in the regions 5, 13 through an insulating film 10, one conduction type semiconductor region 6 formed in the first semiconductor region 5 and an extremely thin oxide film 7 and one conduction type polycrystalline silicon layer 8 shaped onto the region 6 are formed. A region such as the P-type drain region 5 in a MOS transistor functions as a base region in a bipolar transistor in combination, the N<+> emitter region 6 is shaped onto the base region 5, and the polycrystalline silicon layer 8 is formed onto the region 6 through the extremely thin oxide film 7. Accordingly, a semiconductor device, which is shown in an equivalent circuit in the figure and in which currents flowing through the MOS transistor are amplified by the bipolar transistor and output currents are increased, is acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate.

[Conventional technology]

Conventionally, in ICs constructed using MOS) transistors, the output current of the MOS) transistor is small. When a bipolar transistor is provided, stain current amplification is particularly possible.

[Problem that the invention seeks to solve]

The above-described conventional method has drawbacks such as requiring a bipolar transistor in addition to the IC when a bipolar transistor is provided outside the IC, and requiring man-hours to connect the bipolar transistor.

Furthermore, when a bipolar transistor is provided inside the IC, the emitter region 6° and the pace region 2
2. A pieboiler transistor consisting of an Nfi epitaxial layer 3 and the like serving as a collector region, and a source region 13. A MOS transistor consisting of a drain region 23°, a gate electrode 11, etc. must be provided on a semiconductor substrate, and the device area of the bipolar transistor and wiring area for connection with the MOS transistor are required. The disadvantage is that it increases the chip area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which eliminates the above drawbacks, integrates a bipolar transistor and a MOS transistor without increasing the device area, and whose output current is sufficiently larger than that of a conventional MOS transistor.

[Means for solving problems]

The semiconductor device of the present invention includes first and second semiconductor regions of opposite conductivity type provided spaced apart in a -conductivity type semiconductor layer, and an insulating film on the semiconductor layer between the first and second semiconductor regions. a conductor layer provided through the first semiconductor region, a one conductivity type semiconductor region formed in the first semiconductor region, an extremely thin oxide film and a one conductivity type polycrystalline silicon layer formed on the one conductivity type semiconductor region. It has a structure with.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of FIG. 1.

In FIG. 1, an N+ type buried region 2 and an N type epitaxial layer 3 are formed on a P+ type semiconductor substrate 1.
, this N-type epitaxial layer 3 is provided with a P-type drain region 5 and a P-type source region 13 of a MOS transistor. This drain region 5 also serves as a space region t- of the bipolar transistor.

On this pace region 5 is an N+ type emitter region 6.
Further, a polycrystalline silicon layer 8 is formed on the emitter region 6 with an extremely thin oxide film 7t interposed therebetween. This extremely thin oxide film 7 is formed by thermal oxidation, and is provided to be extremely thin in order to block only the holes that are to become the pace current of the bipolar transistor. N++
The emitter region 6 is, for example, arsenic (
AS) can be formed by ion implantation and heat treatment.

Further, a gate oxide film 10 and a gate electrode 11 made of polycrystalline silicon are formed on the N-type epitaxial layer 3 between the source and drain regions 13 and 5.
1 surface is covered with an insulating film 12. An An electrode 9a is provided on the polycrystalline silicon layer 8 and the source region 13.
, 9b are formed.

In this embodiment formed in this way, the N type epitaxial layer 3 and the N+ type buried region 2 function as the collector region of the bipolar transistor. Further, the An electrode 9a is connected to the emitter electrode of the bipolar transistor.
Electrode 9b serves as the source electrode of the MOS transistor and the collector electrode of the bipolar transistor, respectively.

Therefore, the semiconductor device shown in FIG. 1 is amplified by the tit bipolar transistor flowing through the MOS transistor, as shown by the circuit shown in FIG. 2, and a semiconductor device with an increased output current can be obtained. In particular, the extremely thin oxide film 7 provided between the emitter region 6 and the polycrystalline silicon layer 80 has the effect of increasing the current amplification factor of the bipolar transistor several times.

〔Effect of the invention〕

As explained above in detail, according to the present invention, a gold film is formed on the emitter region of a bipolar transistor in the drain region of an IMOS transistor, and a very thin oxide film and a polycrystalline silicon layer made of a conductive material are formed on the emitter region. By providing this, it is possible to obtain a semiconductor device in which a bipolar transistor and a MOS transistor are integrated, which has a current amplification factor that is 1 larger without increasing the element area.

This semiconductor device operates in the same way as a conventional MOS transistor and has the effect of obtaining a large output current.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG. 3 is a sectional view for explaining a conventional semiconductor device. 1...P+ type semiconductor substrate, 2...N+
Type buried region 3...N type epitaxial layer, 4
······Oxide film. 5...Base region and drain region, 6...
...Emitter region, 7...Very thin oxide film, 8...Polycrystalline silicon layer, 9.9a, 9b
...AJ electrode, 10...gate oxide film, 11...gate electrode% 12...insulating film, 13...source region, 21...
Collector electrode, 22...Pace area, 23...
...Drain area. To, Agent Patent Attorney Atsushi Susumu Vcc ￥21￥]

Claims (1)

[Claims] A first semiconductor layer of an opposite conductivity type provided spaced apart from one conductivity type semiconductor layer.
and a conductor layer provided on the semiconductor layer between the second semiconductor region and the first and second semiconductor regions via an insulating film, and a semiconductor region of one conductivity type formed in the first semiconductor region. A semiconductor device comprising an extremely thin oxide film formed on the one conductivity type semiconductor region and a one conductivity type polycrystalline silicon layer.