JPH01140666A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration by providing the high- concentration impurity region of the resistance element made of a semiconductor film in contact with the active layer of a transistor comprising an impurity diffusion layer. CONSTITUTION:There are provided a transistor 34 having impurity diffusion layers 4-6 selectively provided in a P-type silicon substrate 1 as an active layer, and an anti-oscillation resistance 32 made of polycrystalline silicon which is provided through a field oxide film 7 having an opening on the P-type substrate 1 and has high-concentration impurity regions 8-1, 8-2 on both ends thereof. And the high-concentration impurity region 8-1 of the anti-oscillation resistance 32 is provided in contact with the active layer of the transistor 34. Since the resistance is directly connected to the active layer of the transistor in this way, the connecting points can be reduced, whereby the reduction of the chip size of a semiconductor integrated circuit and the improvement of the reliability can be accomplished.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a transistor and a resistance element.

[Conventional technology]

A conventional technique will be explained with reference to FIGS. 3 and 4. FIG. 3 is a circuit diagram of an example of an integrated circuit having a transistor and an oscillation prevention resistor. The configuration consists of an input terminal 311, an oscillation prevention resistor 32. Resistor 33 connected to the emitter terminal. Transistor 34. Transistor emitter electrode 38. It consists of a base electrode 39, a collector electrode 40, an internal circuit 35, and power terminals 36 and 37.

Next, the operation will be explained. When the transistor 34 has excellent characteristics, for example when the current amplification gain is very large, positive feedback occurs due to parasitic capacitance between the terminals, causing oscillation of the transistor. As a method of suppressing this oscillation, by providing an oscillation prevention resistor 32 before and after the base electrode 39 of the transistor 34, the amount of feedback can be reduced and oscillation can be suppressed.

FIG. 4 is a plan view of the mask pattern of this integrated circuit. Oscillation prevention resistor 32 and base electrode 3 of transistor 34
9 are formed independently and then connected using a low wiring resistance material such as an aluminum film.

[Problem that the invention seeks to solve]

In the conventional semiconductor integrated circuit described above, the resistance element inserted between the external terminal and the active layer of the transistor is connected via the aluminum wiring, so that contact is made with the glabella insulating film provided between the resistance element and the aluminum wiring. There is a drawback that a large number of openings 41 are required, and the degree of integration is reduced accordingly.

[Means for solving problems]

The semiconductor integrated circuit of the present invention includes a transistor having an impurity diffusion layer selectively provided on a semiconductor substrate as an active layer, and a semiconductor film provided directly on the semiconductor substrate or with an insulating film interposed therebetween. A high concentration impurity region of the resistance element is provided in contact with the active layer of the transistor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(a) is a plan view of a mask pattern according to an embodiment of the present invention, and FIG. 1(b) is a cross-sectional view of a semiconductor chip taken along the line 8-A' in FIG. 1(a). It is.

In this embodiment, impurity diffusion layers 4, 5, and 6 selectively provided on a P-type silicon substrate 1 are used as active layers, and a transistor 34 and a field oxide film having an opening are formed on the P-type silicon substrate. The anti-oscillation resistor 32 is made of polycrystalline silicon and has high-concentration impurity regions 8-1 and 8-2 at both ends. (The P-type impurity diffusion layer 6, which is a base layer, is formed in the trench-separated element formation region.).

The oscillation prevention resistor 32 may be formed by implanting boron at a high concentration into both ends of a rectangular high-resistance polycrystalline silicon film and then annealing the film.

The input signal line 31' and the power supply lines 36' and 37' are all constructed of first layer aluminum wiring 10.

Comparing Figure 1 (a> with Figure 4), the input signal line 31'
It can be seen that the number of contact holes 41 between the base electrode 39 and the base electrode 39 is reduced by two.

FIG. 2 is a plan view of a mask pattern of a variant of this embodiment. In addition to the oscillation prevention resistor 32, an emitter resistor 33 and a collector load resistor 30 are also made of a polycrystalline silicon film similar to the oscillation prevention resistor. , the high concentration impurity regions are in contact with the emitter region and the collector region, respectively. However, the high concentration impurity regions of the emitter resistance 33 and collector load resistance are as follows:
It is assumed that it is formed by ion implantation of arsenic or phosphorus.

〔Effect of the invention〕

As described above, the present invention can reduce the number of connection points by directly connecting a resistor to the active layer of a transistor, thereby reducing the chip size of a semiconductor integrated circuit and improving reliability.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of a mask pattern according to an embodiment of the present invention, and FIG. 1(b) is a cross-sectional view of a semiconductor chip taken along the line 8-A' in FIG. 1(a). , FIG. 2 is a plan view of a mask pattern of a variation of this embodiment, FIG. 3 is a circuit diagram of an example of a semiconductor integrated circuit, and FIG. 4 is a plan view of a mask pattern of a conventional example. 1... P-type silicon substrate, 2... silicon oxide film,
3... Polycrystalline silicon filling material, 4... N1 type impurity diffusion layer, 5... N type impurity diffusion layer, 6... P type impurity diffusion layer, 7... Field oxide film, 8- 1.8-2
・、. High concentration impurity region of polycrystalline silicon film, 8-3... Resistance region of polycrystalline silicon film, 9... Interlayer insulating film, 10.
...First layer aluminum wiring, 31...Input terminal, 3
1'... Input signal line, 32... Oscillation prevention resistor, 33
...Emitter resistance, 34...Transistor, 36.
37...Power terminal, 36', 37'...Power wiring,
38...Emitter electrode, 3...Base electrode, 40
...Collector load resistance, 41...Contact opening. Agent Br - Rijobi 1 Hara Shindo a) FP type Nrikoshi bottom and 2 9th Ihi silicon A soto b) Multi 1 figure Z Article 4 figure

Claims (1)

[Claims] a transistor having an impurity diffusion layer selectively provided on a semiconductor substrate as an active layer; and a resistive element made of a semiconductor film provided directly on the semiconductor substrate or with an insulating film interposed therebetween; A semiconductor integrated circuit characterized in that a high concentration impurity region of a resistance element is provided in contact with an active layer of the transistor.