JPS623570B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to semiconductor integrated circuits, particularly I ² L devices (integrated injection logic).
Related to the manufacturing method.

The basic structure of the I ² L device is, as shown in FIGS. 1 and 2, for example, an N-type epitaxial layer 2 with a lower concentration is provided on a highly doped N-type substrate 1. A first P-type region 3 corresponding to the base region of the inverter transistor and a second P-type region (implanted region) 4 corresponding to the emitter region of the transistor functioning as an injector are formed by diffusion, and the first P-type region 3 corresponds to the base region of the inverter transistor. A plurality of N-type regions 5 [5a, 5
b and 5c] are formed. Then, a so-called NPN vertical transistor for an inverter is formed in which the epitaxial layer 2, the first P-type region 3, and the plurality of N-type regions 5 are used as an emitter, a base, and a multi-collector, respectively, and the second P-type region 4 and the epitaxial layer 2
A so-called injector PNP lateral transistor is formed with the first P-type region 3 serving as an emitter, a base, and a collector, respectively. 6 are conductive layers made of aluminum or the like, and the terminals E are connected to the back surface of the substrate 1 through these conductive layers 6.
Terminal B is connected to the 1P type area 3, terminal I is connected to the second P type area 4, and terminal is connected to each of the N type areas 5a, 5b, and 5c.
C ₁ , C ₂ , and C ₃ are derived, respectively. 7 is an insulating layer made of SiO ₂ film or the like.

As is clear from FIG. 1, such an I ² L device normally uses a silicon substrate S with a lower concentration epitaxial layer formed on a high concentration substrate 1, and the substrate S is used as an NPN transistor for an inverter. A so-called reverse transistor, which serves as an emitter, is used. For this reason, in this NPN transistor, the area of the region 5 that becomes the collector is smaller than the area of the region 3 that becomes the base, and the current amplification rate h
The disadvantage is that _{the FE} becomes very small. Furthermore, since the difference in area between the region 3 serving as the base and the region 5 serving as the collector is large, the larger the number of regions 5 serving as the collector, the larger the overall area of the I ² L device.

In view of these points, the present invention makes the area corresponding to the collector of the inverter transistor as close as possible to the area of the region corresponding to the base, and the inverter transistor (reverse transistor)
The present invention provides a method for manufacturing a semiconductor integrated circuit, that is, an I ² L device, which increases the current amplification factor h _FE and further reduces the overall area of the I ² L device.

Hereinafter, using FIGS. 3 and 4, the present invention will be described.
Let us explain an example of the method for manufacturing an I ² L device. In addition, the third
Figures A' to E' are sectional views taken along the line Y--Y of Figures 3 A to E, respectively, and Figure 4 is a finally obtained plan view.

First, as shown in FIGS. 3A and A', an N-type high concentration substrate 10 with a specific resistance of 0.01 Ωcm, for example, is prepared, and an N-type epitaxial layer 11 with a specific resistance of 5 Ωcm is formed on this substrate 10. , constitute an N-type semiconductor substrate 12. 13 is an insulating film made of SiO ₂ film or the like.

Next, this insulating film 13 serving as a diffusion mask is photoetched to form diffusion windows 14 and 15A.
Thereafter, an impurity of the conductivity type opposite to that of the substrate 12, that is, P type, is diffused through the diffusion windows 14 and 15A in an oxidizing atmosphere to form P type regions 16 and 17 having a sheet resistance ρs of about 30Ω/□. This P-type region 16 is used as an emitter (ie, an injection region) of a transistor functioning as a so-called injector. The P-type region 17 serves as a lead region for a region corresponding to the base of the inverter transistor, and has an electrode lead portion 17A and a lead portion 17B extending over the length of a region corresponding to a multi-collector to be formed later. It is formed in an L-shape when viewed from the top. During the diffusion process, a SiO ₂ film is formed on the diffusion windows 14 and 15A (FIGS. 3B and B').

Next, photoetching is performed on the insulating film 13, and a plurality of diffusion windows 18 [18
A, 18B, and 18C] and then diffuse an impurity of the conductivity type opposite to that of the substrate 12, that is, P type, through the diffusion windows 18A, 18B, and 18C in a nitrogen atmosphere to form the P type diffusion regions 19A, 19B, and 19, respectively.
A P-type diffusion region 19 is formed in which C is connected to each other in the epitaxial layer 11 and is also connected to the previously formed lead region 17. This P-type diffusion region 19 corresponds to the base region of the inverter transistor, and its sheet resistance ρ
s is selected to be approximately 250Ω/□. Since this diffusion process is performed in a nitrogen atmosphere, no SiO ₂ film is formed on each diffusion window 18A, 18B, and 18C (FIG. 3C and C').

Next, each of the same diffusion windows 18A, 18B and 18
A plurality of independent N-type diffusion regions 2 are formed in the P-type diffusion region 19 by diffusing an impurity of the same conductivity type as the substrate 12, that is, N-type, through C (in an oxidizing atmosphere).
0 [20A, 20B and 20C]. Each of these N-type diffusion regions 20A, 20B and 20C corresponds to a multi-collector region of an inverter transistor (FIGS. 3D and D').

In the process shown in FIG. 3C, the region 19 is diffused in an oxidizing atmosphere, and each window 1 is
A thin SiO ₂ film is formed including on 8A, 18B and 18C, and the windows 18A, 18B and 18C are formed by shallow etching on the entire surface using the difference in thickness of the SiO ₂ film.
It is also possible to reproduce the following N-type regions 20A, 20B and 20C through the reproduced windows 18A, 18B and 18C.

After that, electrode windows are opened, and electrodes 2 made of, for example, aluminum are formed in the P-type diffusion regions 16, 17A and the N-type diffusion regions 20A, 20B, and 20C, respectively.
1 and terminals I, B, C ₁ , C ₂ from the electrodes respectively.
and C ₃ , and at the same time, an electrode 21 is formed on the back surface of the base 12 and a terminal E is led out from there. In this way, the desired I ² L device as shown in FIGS. 3E, E' and 4 is obtained.

According to this manufacturing method, when forming regions 19 and 20 corresponding to the base region and multi-collector region of the inverter transistor, impurities are diffused through substantially the same diffusion windows 18A, 18B and 18C, and region 19 is Since the diffusion regions through each diffusion window are connected to each other in the epitaxial layer 11, and the regions 20 are formed independently, the area of the region 19 corresponding to the base region and the multi-collector region are different. The difference in area from the area of the region 20 can be made extremely small. Incidentally, as an example, when the area of the region corresponding to the collector region is constant ^1050μ2 , the area of region 3 corresponding to the base region is ^3562.5μ2 in the case of the conventional manufacturing method shown in FIG. In the case of the manufacturing method of the present invention shown in Figure 4, the area 17 corresponds to the base area.
The area of 19 and 19 is _2925.0μ2 , which is about 82% of that in the case of FIG. When the area of the region corresponding to the base is 1.0, the area ratio of the collector and the base is 0.29 in the conventional case shown in FIG. 2 and 0.36 in the case of the present invention shown in FIG. Therefore, since the area of the region 20 corresponding to the multi-collector can be made closer to the region 19 corresponding to the base in this way, the current amplification factor h _FE of the NPN vertical transistor for the inverter can be increased compared to the conventional one. ,moreover
The overall area of the I ² L device is smaller. Furthermore, individual regions 19A, 19B, and 19C are formed through each diffusion window 18A, 18B, and 18C, and are interconnected to form a base region 19. Therefore, each area 1
In 9A, 19B, and 19C, the impurity concentration of the portions diffused to the lateral periphery is lower than that of the diffusion window portion, and even if they overlap in adjacent regions, the impurity concentration will be lower than the impurity concentration of the diffusion window portion. .
Therefore, each area 19A, 1 of the base area 19
Since the overlapping connection portion of 9B and 19C has a low concentration and high resistance, it is difficult for base current to flow and it is difficult to function as an effective base. Therefore, the current increase rate h _FE of the NPN vertical transistor becomes larger.

In addition, in the case of FIGS. 3 and 4, the lead region 17 with high impurity concentration is provided in the region corresponding to the base of the inverter transistor, so the base resistance can be reduced even when there are a large number of multi-collectors. You can get used to it.

According to the manufacturing method of the present invention described above, the current amplification factor h _FE of the inverter transistor of the I ² L device is improved, and the area of the entire device is further reduced. It is possible to promote downsizing of the device.

[Brief explanation of the drawing]

1 and 2 are a sectional view and a plan view showing the basic structure of the I ² L device, FIGS. 3A to 3E are sectional views showing an example of the manufacturing method according to the present invention in the order of steps, and FIGS. 3A' to
E' is a cross-sectional view on the Y-Y line of FIGS. 3 A to E, respectively;
FIG. 4 is a plan view of FIG. 3D. 12 is a semiconductor substrate of the first conductivity type; 13 is an insulating film serving as a diffusion mask; 14, 15, 18A, 18
B, 18C is a diffusion window, 16 is an injection region, 17, 1
9 is a region corresponding to the base, and 20 is a region corresponding to the collector.

Claims (1)

[Claims] 1. A diffusion mask in which a diffusion region having a conductivity type opposite to that of the substrate and having a high impurity concentration and corresponding to the lead region of the base is formed in a semiconductor substrate corresponding to an emitter, and having a plurality of windows corresponding to the base on the surface of the semiconductor substrate. forming an impurity having a conductivity type opposite to that of the semiconductor substrate through the window, interconnecting the plurality of diffusion regions within the semiconductor substrate to form a region corresponding to the base, and connecting the plurality of diffusion regions to the above-mentioned one. It is also connected to a diffusion region with a high impurity concentration corresponding to the lead region of the base, and an impurity having the same conductivity type as the semiconductor substrate is diffused into the region corresponding to the base using substantially the same window as the above window. A method for manufacturing a semiconductor integrated circuit characterized by forming regions corresponding to a plurality of independent collectors.