JPS6360550B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a self-aligned emitter type bipolar transistor and a method for manufacturing the same.

In the following description, for convenience of explanation, an npn type transistor will be assumed, but a pnp type is essentially the same and is naturally included in the present invention. In a bipolar transistor in an integrated circuit, an n-type epitaxial layer grown on a p-type silicon substrate is used as a collector, and a base region and an emitter region are generally formed two-dimensionally on the surface of this epitaxial layer. Next, this general conventional structure and its manufacturing method will be briefly explained using FIG. 1. In Figure 1a, after forming a p-type region 4 for element isolation and a buried layer 2 for reducing collector resistance in an n-type epitaxial layer 3 on a p-type substrate 1, a deep base layer is formed using oxide films 5 and 6 as masks. 7 is shown formed by diffusion. FIG. 1b shows a state in which a shallow base region 8 is formed after the oxide film 6 is removed. FIG. 1e shows a state in which an emitter region 9 is further formed using the oxide film 12 as a mask, a contact hole is opened, a collector contact diffusion layer 10 is formed, and an aluminum electrode 11 is attached.

Now, although bipolar transistors originally require a shallow base region only directly below the emitter, when the manufacturing method described above is used, the deep base region 7 and the original deep base region directly below the emitter region 9 are required due to the need for alignment margin. Since the shallow base region is separated by several micrometers and it becomes necessary to electrically connect them, the shallow base region is formed as large as 8 to serve as the connecting portion. Therefore, the extrinsic base resistance r _b caused by the shallow base region 8 has a drawback that it takes a large value of about 100Ω in a general pattern. The importance of the size of the base resistance in digital circuits using bipolar transistors can be easily understood from the following simple consideration. Now, if we consider ECL (Emitter Coupled Logic) as an example, its propagation delay time is the base response τ _b and the collector response τ _c
It is expressed as the sum of Logic circuits that require speed, such as ECL, are designed with a current level that is as fast as possible, so the resistance added to the collector is small, and the collector response is sufficiently small. Therefore, the base response occupies a large proportion of the total delay time. The base response τ _b is approximately equal to the sum of the junction capacitance C _j and the diffusion capacitance C _d of the base multiplied by the base resistance r _b (τ _b =r _b (C _j +C _d )).
Therefore, the magnitude of the base resistance is directly related to the operation speed of the logic circuit, and there is a limit to the speed-up of bipolar transistors with conventional structures that have a large extrinsic base resistance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a bipolar transistor having a self-aligned emitter structure, which has a low base resistance and a high switching speed.

The manufacturing method according to the present invention provides a method for easily and reliably manufacturing the bipolar transistor having the structure according to the present invention. A deep impurity region to be formed as a deep base region is formed, and a mask layer with holes partially formed is formed on the deep impurity doped region, and etching is performed using this as a mask to cross over the bottom of the deep base region or forming a recess with a U- or V-shaped cross-section having a depth that reaches or approaches the bottom;
Thereafter, a shallow base region continuous to the deep base region is thermally diffused into the surface layer at the bottom of this recess while leaving the mask layer, and then ion implantation is performed using the mask layer as a mask to form a shallow base region at the bottom of this recess. The structure of the present invention is characterized by forming an emitter region on the surface layer, and exhibits an outstanding effect in that the structure of the present invention can be manufactured by a self-aligning method.

Hereinafter, the structure and manufacturing method of a typical embodiment of the present invention will be explained using a series of process diagrams shown in FIGS. 2a to 2d, and the present invention will be explained.

Figure 2a shows a p-type substrate 10 with an impurity concentration of 10 ¹⁵ /cm ²
1, an n-type epitaxial layer 103 (3 μm thick) with an impurity concentration of 2.5×10 ¹⁶ /cm ³ , a p-type region 104 for isolation, a buried layer 102 and an oxide film 105
A p-type region 107 is shown as a deep base region formed using the mask as a mask. This deep p-type region 107 has a thickness of approximately 1.2 _μm and a sheet resistance of 20Ω.
That's about it.

In FIG. 2b, the oxide film 105 in FIG. 1a is removed, a CDV oxide film is grown to a thickness of approximately 5000 Å, and then the oxide film in the area where the emitter will be formed is removed 106.
It was molded as shown in the figure below, and the silicon directly below it was etched to about 1.5 μm using an isotropic etching solution. At this time, silicon is etched directly under the CVD oxide film into a substantially cylindrical shape as shown in the figure. In Fig. 2c, a shallow base region 108 is first formed by thermal diffusion to a thickness of approximately X _j 0.4 μm, a window for collector contact diffusion is opened in the oxide film 106, and then an n-type impurity is implanted by ion implantation. Emitter region 109 and collector contact diffusion 11
0 is shown formed shallowly so that X _j is approximately 0.3 μm. Here the shallow base region 10
Since the layer 8 is formed by thermal diffusion, it also penetrates into the circular portion directly under the CVD oxide film mentioned in the explanation of FIG. 1B, and comes into contact with the deep base region 107. On the other hand, since the emitter region 109 is formed by ion implantation, it does not contact the deep base region. Figure 2 d shows that after the CVD oxide film 106 shown in Figure 2 c has been removed, a CVD oxide film is grown again on the entire surface, and contact holes are formed in the emitter 109, base 107, and collector 110. This is where aluminum wiring 111 for electrodes was later applied. This second
The state shown in FIG. d is a typical example of the structure of the present invention.

According to the structure of this embodiment described above, the length of the shallow base region 108 existing between the deep base region 107 and the emitter region 109 is about 0.5 μm, as shown in FIG. It can be reduced to about 1/5 to 1/10 compared to the conventional transistor structure described above. Therefore, since the extrinsic base resistance can also be reduced to 1/5 to 1/10, higher speed transistors can be easily achieved.

According to the manufacturing method of the present invention, a shallow base region 10 is formed in a groove-like depression having a U-shaped or V-shaped cross section.
By forming the emitter 8 by thermal diffusion and the emitter 109 by ion implantation, the structure of the present invention can be easily and reliably realized in self-alignment.

In the above description, only one typical and simple embodiment has been described for convenience of explanation, but the present invention is not limited to such an embodiment. For example, a method of forming a polysilicon layer on the silicon epitaxial layer 103 shown in FIG. 2 and controlling the amount of side etching under the CVD oxide film 106 is, of course, an important embodiment of the present invention. Furthermore, in the case of ordinary transistors whose main focus is on high speed or high output, it is desirable to have the emitter region in the form of a stripe, so the recesses are normally groove-like. If the main focus is on it, it is desirable to form it in a shape other than stripes, such as a square or a circle. Therefore, the shape of the "U-shaped or V-shaped depression in cross section" or "open hole in the form" described in the claims should naturally change with these deformations, and the present invention does not include these. It is also natural that variations of are included.

For example, increasing integration requires reducing the size and increasing the resistance of the load. In the case of conventional structure,
Assuming that the emitter size is 4 × 4 μm, the same
If a ×4 μm graft base (relatively deep xj high concentration region) is provided at a distance of about 4 μm from the emitter, the thin base region from the graft base to just below the emitter will have a length of about 4 μm. Therefore, if the thickness of this thin base region is 0.6 μm and the depth of the emitter is 0.2 μm, the extrinsic base resistance from the graft base to the emitter region is approximately 800 μm.
This results in a large value of Ω. However, if the present invention is implemented, the value of the extrinsic base resistance can be significantly reduced while the basic size of the transistor remains the same. In this case as well, the structure is similar to the embodiment shown in FIG. 2, but since high integration is assumed, it is preferable to provide the graft base only on one side of the emitter, unlike in FIG. The depth of the depression with a U-shaped or V-shaped cross section, which is the region where the emitter vines are formed, is approximately 1.5 μm, and after forming a thin base region with a thickness of 0.6 μm, the emitter region is formed with a depth of 0.2 μm. As a result, the distance from the graft base to the emitter is approximately
It becomes 0.7 μm. The reason is as follows.

In other words, as shown in Figure 3, deep base 1
Since the thickness of 07 is about 1.2 μm and the depth of the groove is 1.5 μm, the angle indicated by 205 is about 35 degrees, and the point 203
The distance between the point 202 and the point 202 is approximately 0.9 μm. However, since the emitter 109 protrudes to the left by approximately 0.2 μm from the point 202, the distance between the graft base and the emitter is approximately 0.7 μm. The extrinsic base resistance is therefore approximately 140Ω.

In this way, the extrinsic base resistance can be reduced to approximately 1/6 between the conventional structure and the structure of the present invention.

Next, using a transistor implementing the present invention,
Let's configure the ECL NOR gate. It has been mentioned above that the load resistance is increased in order to reduce power consumption, but here we will further consider omitting the output method using an emitter fan to reduce power.

Since the logic amplitude needs to be below the diffusion potential, it is set to 0.48V, for example. In this case, if 0.5
Considering the current consumption of about mA, it is recommended to attach a load resistance of about 980Ω to the NOR gate.
When the NOR gates configured in this manner are connected with one fan in and one fan out, the delay time per gate stage is about 520 psec. In the case of the conventional structure, it is about 860 psec, so the effect of the present invention is obvious.

[Brief explanation of drawings]

Figures 1a, b, and c are schematic sectional views showing the conventional structure c along with its steps, and Figures 2a, b, and c are
d shows an embodiment of the present invention in accordance with FIG. FIG. 3 is a conceptual diagram for calculating the distance between the emitter and the graft base. 1,101...Silicon substrate, 2,102...
Filling layer, 3,103... Silicon epitaxial layer, 4,104... P-type region for isolation, 5,1
05... Oxide film, 6,106... Oxide film, 7,1
07... Deep base region, 8,108... Shallow base region, 9,109... Emitter region, 10,
110... Diffusion for collector contact, 11,1
11... Aluminum electrode, 112... Oxide film.

Claims (1)

[Claims] 1. A deep impurity doped region with a relatively high concentration to be a deep base region is formed in a predetermined part of the surface of a silicon epitaxial layer provided on a silicon substrate, and a part of the region is opened on the deep impurity doped region. forming a holed mask layer, and using this as a mask, etching to form a recess with a U- or V-shaped cross-section having a depth that exceeds, reaches, or approaches the bottom of the deep base region; Thereafter, a shallow base region continuous to the deep base region is thermally diffused into the surface layer at the bottom of this recess while leaving the mask layer, and then ion implantation is performed using the mask layer as a mask to form a shallow base region at the bottom of this recess. A method for manufacturing a bipolar transistor, comprising forming an emitter region on the surface layer of the bipolar transistor.