JP3300530B2 - Method of manufacturing mesa-type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates to manufacturing <br/> method for producing a mesa semiconductor equipment, cost reduction due to miniaturization of the high-voltage semiconductor device having a mesa groove, to improve the performance Related.

[0002]

2. Description of the Related Art At present, high breakdown voltage semiconductor devices have been developed with a planar structure in order to increase miniaturization. Fig. 7 (a)
In the planar type bipolar transistor shown in (1), the degree of integration can be increased by reducing the size of the electrode opening.

In FIG. 7 (a), 9 is a base (B) electrode, 10 is an emitter (E) electrode, and 11 is a collector (C) electrode.

However, in order to realize a high breakdown voltage with the planar structure shown in FIG. 7A, it is necessary to achieve a high breakdown voltage with a floating limited ring (FLR) structure. The higher the breakdown voltage, the greater the proportion of the FLR structure in the area of the semiconductor substrate, and the rate of utilization of the semiconductor substrate in the operation region has been greatly reduced.

On the other hand, as another method for achieving high withstand voltage and low cost, there is a mesa bipolar transistor as shown in FIG. 7B.

In FIG. 7B, reference numeral 6 denotes a mesa groove, reference numeral 8 denotes a passivation film, and other reference numerals 9 to 11 are the same as those in FIG. 7A.

[0007]

However, in the case of FIG. 7B, the mesa type has not been adopted for miniaturization and high integration because of the following. In a high-voltage mesa-type bipolar transistor, a depth of 40 μm or more (1500
After forming a deep mesa groove 6 (to obtain high withstand voltage of V or more), a passivation film (glass protective film) 8 made of glass powder or the like as a high insulating film is selectively formed to a film thickness of 10 μm or more. It must be formed in the mesa groove. For this reason, there are various methods for forming the passivation film (glass protective film) 8, but a convex portion 6a having a large variation (approximately ± 5 μm) in the wafer surface necessarily generates 10 μm to 50 μm. Due to the convex portion 6a and the mesa groove 6 of the glass protective film, when performing fine processing on the wafer surface, a photoresist (negative type) is used.
Is applied to a thickness of about 5 μm to 20 μm (to obtain surface flatness to improve oxidation resistance and resist peeling during etching,
In order to protect the glass protective film having low etching resistance), it is difficult to control the exposure time, and the width of one side of the electrode forming opening cannot be reduced to 45 μm or less with the current technology. The photoresist film is also applied on the passivation film (glass protective film) 8 inside the mesa groove 6 using clay of about 300 to 400 cp, and the width of the change around the mesa groove 6 due to the mesa groove 6. Has a shape having irregularities of 50 μm or more.
Therefore, in particular, according to the conventional method, the width of one side of the electrode forming opening around the mesa groove 6 is 45 μm according to various experiments.
m or 2025 μm ² or less in total area. For this reason, there are adverse effects such as cost reduction and improvement of switching characteristics due to miniaturization.

The width of one side of the opening for forming an electrode is 45 μm.
Mesa-type semiconductor devices of m or less have not yet been commercialized.

The present invention enables a technique for ultra-fine electrode openings which could not be realized by the above-mentioned conventional mesa-type semiconductor device, and has a mesa-type structure and a high-integration high-breakdown-voltage mesa-type semiconductor device.
It is intended to provide a method of manufacturing the device.

[0010]

In order to achieve the above object, the present invention provides a method for manufacturing a mesa type semiconductor device, comprising the steps of:
Diffusion step for forming an active region in the semiconductor device, and a step of forming a protective film on the semiconductor substrate after the impurity diffusion step
And protects the opening for electrode formation for connection to the active area
Forming a film, to form the main support groove around the active region
That a step, a step of the glass protective film spin coating consisting of mixed <br/> if liquid of the glass powder and a photosensitive material on a semiconductor substrate, exposure
And development, leaving a glass protective film only in the mesa groove region.
Patterning process and burning the photosensitive material of the glass protective film
A first heat treatment step of firing and a higher temperature than the first heat treatment step
A second heat treatment step of firing the glass protective film,
Rana Ru.

A method for manufacturing a mesa-type semiconductor device according to the present invention comprises:
In order to realize the miniaturization of the electrode opening, the electrode opening is opened before forming the mesa groove protection film, and then the mesa groove and the mesa protection film are formed.

[0012]

[0013]

Method of manufacturing a mesa semiconductor device of the effects of the present invention, by kicking setting the glass protective film mixed sintering of a glass powder and a photosensitive material in a mesa groove, a high breakdown voltage mesa semiconductor element electrode opening Miniaturization can be realized, and the utilization rate of the semiconductor substrate can be greatly improved. In addition, performance improvement such as switching characteristics can be realized by miniaturization.

[0014]

[0015]

1 shows a chip plan view (a) showing the structure of a mesa-type NPN transistor according to a first embodiment of the present invention, and a sectional view taken along the line AA 'of FIG. Reference numeral 5 denotes an electrode opening, and each of the vertical and horizontal sides is 30 μm in the illustrated example. Then, the total area of these electrode openings 5 is set to 2025 μm ²
It is as follows. Others 6, 8 to 11 are the same as those in FIG.

In the first embodiment, the mesa groove 6 is provided around the emitter region 4 and the base region 3 which are the main active regions of the bipolar transistor shown in FIG.

In the first embodiment, a passivation film (glass protective film) 8 mixed and sintered with glass powder and a photosensitive material is used.
Since the opening for electrode formation can be formed before the formation of the mesa groove, the processing size is restricted by the unevenness of the passivation film (glass protective film) 8 (the width of one side of the opening for electrode formation is 45 μm). Free microfabrication that is not performed below or the total area of the opening could not be reduced to 2025 μm ² (45 × 45) or less) has become possible. Therefore, the width of one side of the electrode forming opening could be made 45 μm or less.

FIG. 2 is a cross-sectional view of a chip for each step of manufacturing the chip structure of FIG. 1, and 13 in FIG. 2 is a silicon dioxide film.
This will be described with reference to FIG.

First, phosphorus is diffused from one side of an N-type silicon substrate 1 having a specific resistance of 50 Ωcm and a thickness of 300 μm to a diffusion depth of 130 μm.
m, a collector region 2 having a surface concentration of 2 × 10 ²⁰ cm ³ is formed.
Thereafter, boron is diffused from the side opposite to the collector region 2 to form a base region 3 having a diffusion depth of 30 μm and a surface concentration of 1 × 10 ¹⁹ cm ³ . Then, phosphorus is selectively diffused to form an emitter region 4 having a diffusion depth of 15 μm and a surface concentration of 1 × 10 ²⁰ cm ³ . Then, a silicon dioxide film 13 is formed on the base region 3 and the emitter region 4 (FIG. 2A).

Thereafter, a window of the electrode opening 5 for forming an electrode is opened (FIG. 2B). The mesa groove 6 is formed by a chemical treatment (FIG. 2C). Thereafter, a mixed solution of a glass powder (64% by weight) and a photosensitive substance (36% by weight) as a mesa protective film 7 is formed on the N-type silicon substrate 1 by a spin-on method.
It is applied to 30 μm to form a coating film (FIG. 2 (d)). Thereafter, patterning is performed by exposure and development, and the coating film in the electrode forming portion is removed, leaving the coating film only in the mesa groove region (FIG. 2).
(e)). Thereafter, the photosensitive material is first burned in an oxidizing atmosphere at 500 ° C. for 30 minutes to leave a glass powder film in the mesa groove, and then a heat treatment for firing glass is performed at 870 ° C. for 10 minutes to form a passivation film 8. (FIG. 2 (f)). Finally, a metal film for an electrode is formed on the N-type silicon substrate 1 to obtain a high breakdown voltage mesa-type semiconductor device (FIG. 2 (g)).

FIG. 3A is a plan view showing the structure of a mesa NPN transistor (power transistor) according to a second embodiment of the present invention, and FIG. 3B is a sectional view taken along line AA 'of FIG. Are formed with a vertical and horizontal side of 30 μm and a U-shape with a width of 30 μm.

In FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals. FIG. 4 is a cross-sectional view of a chip for each step of manufacturing the chip structure of FIG. 3, and reference numeral 12 denotes a nitride film, which will be described with reference to FIG.

First, phosphorus is diffused from one side of an N-type silicon substrate 1 having a specific resistance of 50 Ωcm and a thickness of 300 μm to a diffusion depth of 130 μm.
m, a collector region 2 having a surface concentration of 2 × 10 ²⁰ cm ³ is formed.
Thereafter, boron is diffused from the side opposite to the collector region 2 to form a base region 3 having a diffusion depth of 30 μm and a surface concentration of 1 × 10 ¹⁹ cm ³ . Next, phosphorus is selectively diffused to form an emitter region 4 having a diffusion depth of 15 μm and a surface concentration of 1 × 10 ²⁰ cm ³ (FIG. 3A).

Thereafter, a window of the electrode opening 5 for forming an electrode is opened (FIG. 3B). Thereafter, a nitride film 12 is formed to a thickness of 100 nm on the mesa groove forming side by the CVD method (FIG. 3C).
Next, the nitride film 12 in the mesa groove forming region is selectively removed,
Thereafter, a mesa groove 6 is formed by a chemical treatment (FIG. 3).
(d)). A glass film is formed as a mesa groove protection film by an electrodeposition method, and then a heat treatment for baking glass is performed at 870 ° C. for 10 minutes to form a passivation film 8 (FIG. 3E). Thereafter, in order to open the electrode opening 5, the nitride film 12 is removed with hot phosphoric acid (150 ° C., 40 minutes) (FIG. 3F). Finally, a metal film for an electrode is formed on the N-type silicon substrate 1 to obtain a high breakdown voltage mesa semiconductor device (FIG. 3 (g)).

FIG. 5 shows a comparison of the characteristics of the high breakdown voltage mesa semiconductor device (Examples 1 and 2) manufactured by the method of the present invention as described above and the planar type (A) and the mesa type (B) of the conventional method. And FIG.
Shown in

FIG. 5A shows the reverse breakdown voltage of the collector (VCBO).
FIG. 5 (b) is a collector saturation voltage (VCE) characteristic diagram,
FIG. 6A is a switching fall time characteristic diagram (tf), and FIG.
Is a switching accumulation time characteristic diagram (ts).

As can be seen from FIG. 5A, the collector reverse breakdown voltage (VCBO) of the first and second embodiments according to the present invention is almost the same as that of the conventional mesa type (B). As can be seen from FIG. 5 (b), the collector saturation voltage VCE (SAT) of Examples 1 and 2 according to the method of the present invention is lower than that of the mesa type (B) of the conventional method, and FIGS. b) Switching characteristics (tf, t
It is possible to obtain a high-breakdown-voltage mesa-type semiconductor device having a high s).

In each embodiment of the present invention, a high breakdown voltage mesa NPN transistor has been described.
For the S, IGBT, thyristor, diode and the like, as shown in the above embodiment, in all the devices subjected to the diffusion heat treatment, the electrode opening is opened before forming the mesa groove protective film, and then the mesa groove and the mesa protection are formed. A method of forming a film, or forming a protective film having a different etching speed from a silicon dioxide film such as a nitride film after opening an electrode opening, and then forming a mesa groove and a mesa groove protective film, and then forming an electrode opening By performing the opening of the portion by utilizing the difference in the etching speed, the width of one side of the electrode opening or the area of the opening is reduced, and a high-voltage mesa-type semiconductor element with a high degree of integration can be obtained. Significant performance improvement and cost reduction can be achieved.

[0029]

As described above, according to the present invention,
By forming the glass protective film of the mesa groove as a mixed sintered body of a glass powder and a photosensitive substance, the width of one side of the electrode forming opening is set to 45 μm or less, or the total area of the opening is set to 2025
μm ² or less, and a highly integrated mesa semiconductor device having high withstand voltage can be obtained. Thereby, switching characteristics are improved.

By forming the electrode forming opening before forming the mesa groove and then forming the glass protective film, the minimum fine processing dimension of one side of the electrode forming opening is not restricted to 45 μm. Fine processing similar to that of a normal highly integrated semiconductor device can be performed.

The nitride film is used as a protective film for the opening for forming an electrode,
After that, by forming the mesa groove and the glass protective film, there is no need to mix the photosensitive material into the glass protective film, the yield is not reduced by impurities contained in the photosensitive material, and the electrical reliability is stable. Is obtained.

[Brief description of the drawings]

FIG. 1A is a plan view showing the structure of a mesa-type NPN transistor chip according to a first embodiment of the present invention, and FIG.
It is A 'sectional drawing (b).

FIG. 2 is a cross-sectional view of a chip in each step of FIG. 1;

FIG. 3A is a plan view showing a structure of a mesa-type NPN transistor chip according to a second embodiment of the present invention, and FIG.
It is A 'sectional drawing (b).

FIG. 4 is a cross-sectional view of the chip in each step of FIG. 3;

5A and 5B are a collector reverse breakdown voltage characteristic diagram (a) and a collector saturation voltage characteristic diagram (b) of the first and second embodiments of the present invention and a conventional example.

FIG. 6 is a switching characteristic diagram of the first and second embodiments of the present invention and a conventional example.

FIG. 7 shows a conventional planar bipolar transistor.
3A is a schematic cross-sectional view of a mesa bipolar transistor (b). FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Collector area, 3 ... Base area, 4 ... Emitter area, 5 ... Electrode opening, 6 ...
Mesa groove, 7: Mesa protective film, 8: Passivation film
(Glass protective film), 9: base electrode, 10: emitter electrode, 11: collector electrode, 12: nitride film, 13: silicon dioxide film.

Continuation of the front page (72) Inventor Masato Yokozawa 1-1, Sachimachi, Takatsuki City, Osaka Prefecture Inside Matsushita Electronics Corporation (56) References JP-A-53-36471 (JP, A) JP-A-56- 134800 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/762 H01L 21/316 H01L 21/331 H01L 21/76 H01L 29/73

Claims (1)

(57) [Claims] 1. A semiconductor substrate for forming an active region
An impurity diffusion step; and forming a protective film on the semiconductor substrate after the impurity diffusion step.
Forming an opening for forming an electrode for connecting to the active area.
A step of forming a mesa groove around the active region, a step of forming a mesa groove around the active region, and a step of forming a mixture of glass powder and a photosensitive substance on the semiconductor substrate.
A step of spin coating a Ranaru glass protective film, the glass retaining only in the region of the mesa groove by exposure and development
A patterning step of leaving a protective film, and a first heat treatment for burning a photosensitive substance of the glass protective film
And a glass protective film having a higher temperature than the first heat treatment step.
Production side of the mesa type semiconductor device comprising a second heat treatment step of firing, that it consists of
Law .