JPS6014512B2 - Insulated gate field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor substrate in which a drain region and a source region are formed from the main surface side of the semiconductor substrate, and a channel region is formed on the main surface side between the drain region and the source region. This invention relates to an improvement in an insulated gate field effect transistor in which a gate electrode is disposed opposite to a channel region with an insulating layer interposed therebetween, and a drain electrode and a source electrode are connected to a drain region and a source region, respectively.

First, in order to facilitate understanding of the present invention, a conventional insulated gate field effect transistor will be described with reference to FIGS. 1 and 2. In FIGS. 1 and 2, M indicates a line-gate field effect transistor as a whole, which is formed in a plate-shaped, for example, P-type semiconductor substrate 1 from its main surface 2 side, for example, by diffusion. N-type drain region 3
and a source region 4, and a drain region 3 of the substrate 1.
and a P-type channel region 5 formed on the main surface 2 side between the source region 4 and the source region 4 .

Further, an insulating layer 6 made of silicon nitride, silicon oxide, etc., attached on the king surface 2 of the semiconductor substrate 1;
It has a gate type electrode 7 disposed at a position facing the upper channel region 5. It extends over the insulating layer 6 and is ohmically coupled to the drain region 3 and source region 4, respectively, through windows 8 and 9, which are pre-drilled at positions opposite the drain region 3 and source region 4, respectively. The semiconductor substrate 1 has a drain electrode 10 and a source electrode 11 that are connected to each other, and a base 12 that is ohmically connected to the surface of the semiconductor substrate 1 that is opposite to the main surface 2 side. More than,
This is the configuration of a conventionally proposed insulated gate field effect transistor.

According to the conventional insulated gate field effect transistor having such a configuration, for example, a required bias power source with the drain electrode 10 side positive is connected between the drain electrode 10 and the ground, and the source electrode 11 is connected to the ground. And furthermore,
Connect another necessary bias power source between the base electrode 12 and the ground with the side of the base electrode 12 being negative, and furthermore, connect another required bias power source with the side of the gate electrode 7 positive between the gate electrode 7 and the ground. When a signal voltage is applied to the gate electrode 7 in the connected state, the conductivity type of the channel region 5 is reversed from P type to N type, and a current corresponding to the signal voltage passes from the drain region 3 through the channel region 5. Therefore, the function of flowing as a channel current to the source region 4 side is obtained.

However, looking at the breakdown voltage that represents one of the characteristics of the insulated gate field effect transistor M mentioned above, it is the breakdown voltage of the PN junctions 14A and 14C between the semiconductor substrate 1 and the channel region 5, respectively, and the drain region 3. It is determined by the lower of the breakdown voltages VB^ and VBc (generally referred to as VB), and the voltage V8 is:
Based on the voltage of the bias power supply connected between the drain electrode 10 and the base electrode 12, the PN junction 14A;
are formed on the outside and inside of C, respectively.

Depletion layers 15A and 15A shown with diagonal lines in FIG.
During the spread of C and 15C', X^ and X^'; and the sum of Xc and Xc'(X^+X^'); and (Xc+Xc')
The larger the value of the smaller one (generally referred to as (XBx.'), the larger it becomes. Also, it represents one of the other characteristics of the insulated gate field effect transistor M. Looking at the capacitance between the base electrode 12 and the drain electrode 10, it is the junction capacitance C of the PN junctions 14A and 14C.
The capacitance CB is determined by the larger of ^ and Cc (generally referred to as CB), and the larger the sum (XB + XB) of the depletion layer spread, the smaller the capacitance CB becomes.

By the way, during the expansion of the depletion layer 15B (this means the depletion layer 15A or 15C) ×8 (this means ×^ or ×c) and the depletion layer 156 (this means the depletion layer 15A' or 15C) ’ in a similar medium X8’
(This means X^' or Xc') is the impurity concentration N8 (this means the impurity concentration of the substrate 1 ^, when that of the channel region 5 is Nc, it means the higher impurity concentration in N^ and Nc) and the impurity concentration No of the inner drain region 3, and generally, XB The relationship is as follows: (Ten 1) - - - - -...

Outside the conventional insulated gate field effect transistor described above, the impurity concentration N^ of the semiconductor substrate 1 is 1 and 4 to 1.
The impurity concentration Nc of the channel region 5 is about Nc2NA, and the impurity concentration N of the drain region 3 and the source region 4 is about 6 atoms/skin-3.

and Ns is about 1 and 8 to 10 acm/skin -3.
Therefore, the impurity concentration N of the drain region 3. However, the maximum value of the impurity concentration No mentioned above is usually more than 1 times, and therefore, as is particularly clear in FIG. , depletion layer 1
The expansion of 5B' is significantly larger than that of XB', and it was normal for XB' to be so small that it could be ignored. Therefore, in the conventional insulated gate field effect transistor M mentioned above, the breakdown voltage VB mentioned above is increased and the capacitance C mentioned above is increased.

In order to improve the characteristics of the insulated gate field effect transistor M by reducing the
) is set to be large, the distance between the drain region 3 and the source region 4 is Therefore, the length of the channel region 5 has to be increased, which has the disadvantage that the insulated gate field effect transistor M becomes larger as a whole. Further, in the above description, the case where there is a single insulated gate type field effect transistor M is described, but in order to integrate a large number of insulated gate type field effect transistors M as described above, the insulated gate type field effect transistor M described above is For example, as shown in the figure, the effect transistor M is provided in the base 1 from the main surface 2 side, surrounding the drain region 3, the source region 4, and the channel region 5, and being connected to the drain region 3 and the source region 4. When the above-described insulated gate field effect transistor M is isolated from another insulated gate field effect transistor (not shown) by the P+ type isolation region 13 formed in the relationship, the drain region 3 Similarly to the above, depletion layers 16B and 166 are formed on both sides of the PN junction 14E between the isolation region 13 and the isolation region 13, but during their expansion, the sum of XBr and XB... ') becomes 4.multidot. because the impurity concentration in the region 13 is higher than the above-mentioned (X80x8').

Therefore, in this case, the breakdown voltage and capacitance of the PN junction 14E become problems. Therefore, the present invention aims to propose a novel insulated gate field effect transistor that eliminates the above-mentioned drawbacks and problems, and will become clear from the detailed description below.

FIG. 3 shows an embodiment of an insulated gate field effect transistor that is the basis of the present invention.

In FIG. 3, parts corresponding to those in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The insulated gate field effect transistor shown in FIG. 3, which is the basis of the present invention, has the same structure as that shown in FIGS. 1 and 2 except for the following points. It has a structure.

That is, the drain electrode layer 3 and the source electrode layer 24 having impurity concentrations higher than those of the drain region 3 and the source region, respectively, are formed in the drain region 3 and the source region 4 from the main surface 2 side, and The drain electrode 10 and the source electrode 11 are ohmically connected to the drain electrode layer 23 and the source electrode layer 24, respectively. Further, the impurity concentrations No and Ns of the drain region 3 and the source region 4 are within a range of 1 to 10 times higher than the higher one of the impurity concentrations N^ and Nc of the semiconductor substrate 1 and the channel region 5, N8. being done.

In practice, the drain region 3 and the source region 4 are formed simultaneously, for example by diffusion, so that No=Ns
, and if NB is 1 and 4 to 1 and 6 atoms/K-3, then No is selected within the range of 1 and 4 to 1 and 7 atoms/K-3, maintaining the relationship IONB>ND>NB. It is. Here, the reason why No is set in the range of 1 to 1, which is higher than N8, is that when the number is 1 or more, XB in the sum (XB + XB') during the expansion of the depletion layer mentioned above
' is less than about 10% of X8, and the existence of XB' is actually ineffective. In addition, if it is less than 1 times, the drain region 3 cannot be formed in the substrate 1 by a normal manufacturing method. For example, if P is applied to the N-type substrate that will become region 3
This is because it becomes necessary to form a mold region and use this as the base body 1 to form the base body 1 and the drain region 3, making it impossible to easily manufacture the insulated gate field effect transistor M.

The above is the configuration of the embodiment of the insulated gate field effect transistor M that is the basis of the present invention.

According to such a configuration, the same function as that of the insulated gate field effect transistor M described above in FIGS. 1 and 2 can be obtained, and the same function as that described above in FIGS. , a drain electrode 1 is placed on the outside and inside of the PN junction 14B.
It is clear that depletion layers 15B and 166 are formed based on the voltage of the bias power supply between 0 and base electrode 12.

However, in this case, since ND is in the range of 1 to 1 M tones of NB, XB
If the sum (XB+×B') of This is significantly larger than the cases shown in FIGS. 1 and 2, which also have the above characteristics. Therefore, since XB can be made smaller by this amount, the distance between the drain region 3 and the source region 4, and therefore the length of the channel region, can be made smaller than in the cases of FIGS. 1 and 2. Therefore,
An insulated gate field effect transistor M having the same characteristics as those shown in FIGS. 1 and 2 can be manufactured without increasing the size, and the length of the channel region can be reduced. The channel current can be increased by 50%.

Furthermore, when the length of the channel region 5 is made equal to that in the cases of FIGS. 1 and 2, the sum (
×80 The capacitance CB also becomes smaller. Therefore, an insulated gate field effect transistor M having good characteristics can be manufactured.

Note that, as a result, the impurity concentration N of the drain region and the source region. and Ns are 4.compared to the cases of FIGS. 1 and 2. Therefore, although it is difficult to directly connect the electrodes 10 and 11 to the drain region 3 and the source region 4, respectively, It has a drain electrode layer 23 and a source electrode layer 24 having an impurity concentration higher than that of the region 3 and the source region 4, and the drain electrode 10 and the drain electrode 11 are connected to them, respectively. 3 and source region 4,
There is no problem in deriving the voltage using the drain electrode 10 and source electrode 11. Furthermore, as described above with reference to FIGS. 1 and 2, when the insulated gate field effect transistor M is isolated from other insulated gate field effect transistors by the isolation region 13, the PN junction 14
The sum (XB''+XB''') of the expanding depletion layers 16 and 16B' formed on both sides of E results in No.
4 and the depletion layer 16 from the case of FIG.
Since XB'' during the expansion of B can be made larger than in the case of FIGS. 1 and 2, it can be made sufficiently larger than in the case of FIGS. 1 and 2.

Therefore, the breakdown voltage and capacitance of the PN junction 14E can be effectively avoided from becoming a problem.

The insulated gate field effect transistor that is the basis of the present invention has been clarified above, but the present invention is based on the insulated gate field effect transistor M described above in FIG.
The purpose of this invention is to propose a novel insulated gate field effect transistor having superior characteristics, which will become clear from the following description with reference to FIG. FIG. 4 shows an embodiment of an insulated gate field effect transistor according to the invention. In FIG. 4, parts corresponding to those in FIG. 3 are given the same reference numerals, and detailed description thereof will be omitted.

Outside the insulated gate field effect transistor according to the present invention shown in FIG. 4, in the insulated gate field effect transistor shown in FIG. N-type regions 33 and 3 having an impurity concentration higher than the concentration
The structure is similar to that of FIG. 3, except that 4 is formed.

The above is the structure of the first embodiment of the insulated gate field effect transistor according to the present invention.

According to the insulated gate field effect transistor according to the present invention having such a configuration, the regions 33 and 34 are provided at the center of the drain region 3 and the source region 4, respectively, and the conductivity type thereof is the region 3. and 4, it is clear that the same effect as in the case of FIG. 3 can be obtained.

However, in the center of the drain region 3, the region 33
exists, so the depletion layers 15A on both sides of the PN junction 14A
and 15A', the expansion of the outer one 15A is encouraged, but the expansion of the inner one 15A' is prevented.

Therefore, the depletion layers 15C and 15, which are connected to the depletion layer 15A' and have a relationship that intersects with the direction of expansion thereof, have an influence on the expansion of the depletion layer.
The expansion of that 15C' inside the circle is the depletion layer 15A'
spreads more than if it were not prevented from spreading. Therefore, in general, the breakdown voltage of the PN junction 14C is
Since the bond 14C reaches the insulating layer 6, it tends to become smaller on the main surface 2 side, but this is effectively compensated for, which is a feature that the case of FIG. 3 does not have. .

In the structure of the insulated gate field effect transistor according to the present invention shown in FIG. For example, a high impurity region is formed by ion implantation, and then thermal diffusion treatment is performed to diffuse impurities from the high impurity region into the substrate 1, thereby converting the high impurity region after the thermal diffusion treatment into the region 33. and 34, regions in which impurities are diffused in the substrate 1 can be formed as regions 3 and 4.

Note that in the above description, the drain region 3 and the source region 4 can be formed simultaneously in practice, and it is preferable to form the drain region 3 and the source region 4 simultaneously.
Although it has been described that the impurity concentration Ns of the drain region 3 is the same as that of the drain region 3, it is not necessarily necessary to do so.

However, if it is planned that the drain region 3 is used as a source region, and the source region 4 is also planned to be used as a drain region accordingly, then the source region 4
Regarding the drain region 3, the same procedure as described above may be applied. Further, in the above description, assuming that the base body 1 is of P type, the drain region 3 and the source
The case where the channel region 5 and the isolation region 13 are of the P type has been described, but the base body 1 is of the N type and the conductivity types of the regions 3, 4, 5 and 13 are accordingly changed as described above. The case may be reversed, and various other modifications and changes may be made.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are a schematic plan view and a cross-sectional view, respectively, showing a conventional insulated gate field effect transistor. FIG. 3 is a schematic cross-sectional view showing an embodiment of an insulated gate field effect transistor that is the basis of the present invention. FIG. 4 is a schematic cross-sectional view showing an embodiment of an insulated gate field effect transistor according to the present invention. M′...Insulated gate field effect transistor, 1...Semiconductor substrate, 3.
...Drain region, 4...Source region, 5...
...Channel region, 6...Insulating layer, 7...
...Gate electrode, 10...Drain electrode, 1
1... Source electrode, 12... Base electrode, 13... Isolation region, 14A, 14C, 14
B, 14E...PN junction, 15A, 15A',
15C, 150, 15B, 158, 16B, 166...
...Depletion layer. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A drain region and a source region are formed in the semiconductor substrate from the main surface side, and a channel region is formed on the main surface side between the drain region and the source region, and a channel region is formed in the channel region with an insulating layer interposed therebetween. , an insulated gate field effect transistor in which gate electrodes are arranged facing each other and a drain electrode and a source electrode are connected to the drain region and the source region, respectively; a drain electrode layer having an impurity concentration is formed from the main surface side, the drain electrode is ohmicly connected to the drain electrode layer, and the impurity concentration in the drain region is such that the impurity concentration in the semiconductor substrate and the channel region is The impurity concentration is within a range of 1 to 10 times higher than that of the higher one of the drain regions, and a region having an impurity concentration higher than the impurity concentration is formed in the central portion of the drain region. Insulated gate transistor.