JPH01123365U - - Google Patents
Info
- Publication number
- JPH01123365U JPH01123365U JP1968188U JP1968188U JPH01123365U JP H01123365 U JPH01123365 U JP H01123365U JP 1968188 U JP1968188 U JP 1968188U JP 1968188 U JP1968188 U JP 1968188U JP H01123365 U JPH01123365 U JP H01123365U
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- layer
- semiconductor layer
- gate
- formation region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 3
- 230000005669 field effect Effects 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
第１図は本考案の一実施例のＭＯＳＦＥＴの断
面図、第２図はゲートに抵抗が接続されていない
ときのターンオン時のゲート電圧波形図、第３図
は第１図のＭＯＳＦＥＴの等価回路図、第４図は
第１図のＭＯＳＦＥＴのターンオン時のゲート電
圧波形図である。
１：Ｎ形シリコン基板、３：ドレイン電極、４
：Ｐ層、５：ｓｉｏ２膜、６：チヤネル形成領域
、７：ソース領域、８：ソース電極、１１：ゲー
ト、１２：アノード層。
Fig. 1 is a cross-sectional view of a MOSFET according to an embodiment of the present invention, Fig. 2 is a gate voltage waveform diagram at turn-on when no resistor is connected to the gate, and Fig. 3 is an equivalent circuit of the MOSFET of Fig. 1. 4 is a gate voltage waveform diagram when the MOSFET shown in FIG. 1 is turned on. 1: N-type silicon substrate, 3: drain electrode, 4
: P layer, 5: sio 2 film, 6: channel formation region, 7: source region, 8: source electrode, 11: gate, 12: anode layer.
Claims (1)
トを一導電形の高不純物濃度半導体層で形成し、
該層に他導電形半導体層が隣接し、前記一導電形
層の基板内にチヤネル形成領域上より離れた個所
および前記他導電形層が導線によりゲート端子と
接続されたことを特徴とするＭＯＳ電界効果トラ
ンジスタ。 A gate provided on a semiconductor substrate via an insulating film is formed using a highly impurity concentration semiconductor layer of one conductivity type,
A MOS characterized in that a semiconductor layer of the other conductivity type is adjacent to the layer, and a portion of the substrate of the one conductivity type layer remote from above a channel formation region and the layer of the other conductivity type are connected to a gate terminal by a conductive wire. field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1968188U JPH01123365U (en) | 1988-02-17 | 1988-02-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1968188U JPH01123365U (en) | 1988-02-17 | 1988-02-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01123365U true JPH01123365U (en) | 1989-08-22 |
Family
ID=31235406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1968188U Pending JPH01123365U (en) | 1988-02-17 | 1988-02-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01123365U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09129764A (en) * | 1995-11-06 | 1997-05-16 | Nec Corp | Semiconductor device and manufacture thereof |
-
1988
- 1988-02-17 JP JP1968188U patent/JPH01123365U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09129764A (en) * | 1995-11-06 | 1997-05-16 | Nec Corp | Semiconductor device and manufacture thereof |
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