JPH0669508A - Double-diffused field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce a gate-drain capacitance, to enhance a switching speed and to reduce an ON voltage in a double-diffused field-effect transistor. CONSTITUTION:An impurity layer whose conductivity type is opposite to that of the upper part of a channel is formed in a part 6a other than the upper part of the channel for a polysilicone gate part 6, it is made to float, the part 6a which has been made to float is connected to a gate electrode 9 via a diode D. Consequently, when a voltage is applied to the gate electrode 9, an accumulation layer is formed on the surface part of a drain region between channels and an ON resistance can be reduced. When no voltage is applied to the gate electrode 9, the polysilicone gate part 6a on the drain region between the channels is made to float from the gate electrode 9, and a gate-drain capacitance is reduced. As a result, the switching speed of the transistor can be made fast.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double diffusion type field effect transistor, and more particularly to a technique for reducing its on-voltage.

[0002]

2. Description of the Related Art FIG. 2 shows a sectional structure of a conventional double diffusion type field effect transistor (DMOSFET). In this structure, the P-type semiconductor region 2 for forming a channel is diffused in the surface portion of the N-type semiconductor region for the drain region of the semiconductor substrate 1, and the N-type semiconductor region 3 for the source region is diffused inside the region 2. It has a structure. A surface portion of the P-type semiconductor region 2 sandwiched between the N-type semiconductor substrate 1 and the N-type semiconductor region 3 is a channel 4, and a polysilicon gate portion 6 has an insulating film 5 on the channel 4. It is provided through. Further, 7 is a source electrode, 8 is a drain electrode, and 9 is a gate electrode.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In order to improve the switching speed of, the gate-drain capacitance (Cgd) must be reduced. Generally, the polysilicon gate part on the drain region is removed, the gate insulating film on the drain region is thickened, and the polysilicon gate part on the drain region is of a conductivity type opposite to that of other parts. (JP-A-2-102578)
No.) etc. have been proposed. However, these methods have a problem that the storage layer is not formed in the drain region below the polysilicon gate portion between the channel regions, and the on-resistance increases.

The present invention has been made in view of the above points, and an object thereof is to improve the switching speed by reducing the gate-drain capacitance in a double diffusion type field effect transistor. It is also possible to reduce the on-voltage.

[0005]

In the double diffusion type field effect transistor of the present invention, the first region for the drain region is formed.
A second channel forming channel is formed on the surface of the conductive type semiconductor substrate 1.
A conductive type diffusion region 2 is formed, and a first conductive type diffusion region 3 for a source region is formed on the surface of the diffusion region 2.
A polysilicon gate portion 6 is formed via an insulating layer 5 on the surface region which becomes the channel 4 so that the channel 4 of the first conductivity type is formed on the surface of the diffusion region 2 of the second conductivity type. In a semiconductor device, an impurity layer having a conductivity type opposite to that on the channel is formed and floated in a portion 6a of the polysilicon gate portion 6 other than on the channel, and the floating portion 6a is gated through a diode D through a gate electrode. 9 on the channel 6 of the polysilicon gate 6
It is characterized in that b is connected to the gate electrode 9.

[0006]

In the structure of FIG. 1, an impurity layer having a conductivity type opposite to that of the portion 6b on the channel is formed in the central portion 6a of the polysilicon gate portion 6 other than on the channel to make the floating, and The portion 6a is connected to the gate electrode 9 via the diode D. By thus connecting the floating polysilicon portion 6a and the gate electrode 9 via the diode D, the gate electrode 9 is connected to the gate electrode 9. In the ON state where a voltage is applied, a voltage is applied to the floating polysilicon portion 6a via the diode D, and an accumulation layer is formed on the surface portion of the drain region between the two channels 4. Therefore, the on resistance can be reduced. Further, in the off state where no voltage is applied to the gate electrode 9,
The polysilicon portion 6a on the drain region between the two channels 4 is in a state of being floated from the gate electrode 9, and the area of this portion is the gate-drain capacitance (C
gd) will be reduced. Therefore, the switching speed is increased.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a DMOSF as an embodiment of the present invention.
It is sectional drawing of ET. In this structure, the P-type semiconductor region 2 for forming a channel is diffused in the surface portion of the N-type semiconductor region for the drain region of the silicon semiconductor substrate 1, and the N-type semiconductor region 3 for the source region is provided inside the region 2. It has a diffused structure. A surface portion of the P-type semiconductor region 2 sandwiched between the N-type semiconductor substrate 1 and the N-type semiconductor region 3 serves as an N-type channel 4, and a polysilicon gate portion 6 is provided on the channel 4. It is provided via the insulating film 5. An impurity layer having a conductivity type opposite to that of the portion 6b on the channel is formed and floated in the central portion 6a of the polysilicon gate portion 6 other than on the channel, and the floating portion 6a is passed through the diode D. It is connected to the gate electrode 9. Further, the portion 6b on the channel of the polysilicon gate portion 6 is connected to the gate electrode 9. A source electrode 7 is connected to the P-type semiconductor region 2 for channel formation and the N-type semiconductor region 3 for source region. Further, the drain electrode 8 is connected to the N-type semiconductor region for the drain region of the semiconductor substrate 1.

The operation of this embodiment will be described below.
In the present embodiment, the floating polysilicon portion 6a and the gate electrode 9 are connected via the diode D,
In the ON state in which a voltage is applied to the gate electrode 9, a voltage is applied to the floating polysilicon portion 6a via the diode D, and an accumulation layer is formed on the surface portion of the drain region between the two channels 4. Therefore, the on resistance can be reduced. Further, in the off state where no voltage is applied to the gate electrode 9, the polysilicon portion 6a on the drain region between the two channels 4 is in a state of being floated from the gate electrode 9, and the area of this portion is: The gate-drain capacitance (Cgd) is reduced. Therefore, the switching speed is increased.

[0009]

According to the present invention, in a double diffusion type field effect transistor, an impurity layer having a conductivity type opposite to that of the channel is formed and floated in a portion other than the channel of the polysilicon gate portion. , This floating part was connected to the gate electrode through the diode, and the part on the channel of the polysilicon gate part was connected to the gate electrode.Therefore, when applying voltage to the gate electrode, the surface part of the drain region between the channels An accumulation layer is formed on the
There is an effect that the on-resistance can be reduced. Also, when no voltage is applied to the gate electrode, the polysilicon gate part on the drain region between the channels is in a state of being floated from the gate electrode, and the area of this part reduces the gate-drain capacitance. Therefore, the switching speed is increased.

[Brief description of drawings]

FIG. 1 is a sectional view of a DMOSFET as an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional DMOSFET.

[Explanation of symbols]

 1 N-type semiconductor region (semiconductor substrate) 2 P-type semiconductor region 3 N-type semiconductor region 4 Channel 5 Insulating layer 6 Polysilicon gate part 6a Floating part 6b Channel part 7 Source electrode 8 Drain electrode 9 Gate electrode

Claims (1)

[Claims] 1. A diffusion region of a second conductivity type for forming a channel is formed on the surface of a semiconductor substrate of the first conductivity type for the drain region, and a diffusion region of the first conductivity type is formed on the surface of this diffusion region.
A diffusion region of a conductivity type is formed, and a polysilicon gate portion is formed on the surface region to be a channel of the first conductivity type through an insulating layer so that a channel of the first conductivity type is formed on the surface of the diffusion region of the second conductivity type. In the formed semiconductor device, an impurity layer having a conductivity type opposite to that of the channel is formed and floated on a portion other than the channel of the polysilicon gate portion, and the floating portion is gated through a diode to the gate electrode. A double-diffusion field-effect transistor, characterized in that the portion above the channel of the polysilicon gate portion is connected to the gate electrode.