JPS6361152U - - Google Patents

Info

Publication number
JPS6361152U
JPS6361152U JP15625686U JP15625686U JPS6361152U JP S6361152 U JPS6361152 U JP S6361152U JP 15625686 U JP15625686 U JP 15625686U JP 15625686 U JP15625686 U JP 15625686U JP S6361152 U JPS6361152 U JP S6361152U
Authority
JP
Japan
Prior art keywords
diffusion region
protection circuit
conductivity type
diffusion
input protection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15625686U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15625686U priority Critical patent/JPS6361152U/ja
Publication of JPS6361152U publication Critical patent/JPS6361152U/ja
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案による入力保護回路を説明する
上面図、第2図は第1図の−線断面図、第3
図は本考案の動作を説明するための特性図、第4
図は従来の入力保護回路を説明する上面図、第5
図は従来の入力保護回路の等価回路図である。 1は入力パツド、2は拡散抵抗、3は半導体基
板、4は拡散領域、5はイオン注入領域である。
Fig. 1 is a top view illustrating the input protection circuit according to the present invention, Fig. 2 is a sectional view taken along the - line in Fig. 1, and Fig. 3 is a sectional view taken along the line -
The figure is a characteristic diagram for explaining the operation of the present invention.
The figure is a top view explaining a conventional input protection circuit.
The figure is an equivalent circuit diagram of a conventional input protection circuit. 1 is an input pad, 2 is a diffusion resistor, 3 is a semiconductor substrate, 4 is a diffusion region, and 5 is an ion implantation region.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力パツドより拡散抵抗を介して保護されるM
ISトランジスタのゲート電極に接続される入力
保護回路において、前記拡散抵抗を形成する一導
電型の拡散領域に逆導電型のイオン注入領域を前
記拡散領域より深く形成し、前記拡散領域の接合
耐圧を低下させることを特徴とする入力保護回路
M protected from the input pad via a diffused resistor
In an input protection circuit connected to a gate electrode of an IS transistor, an ion implantation region of an opposite conductivity type is formed deeper than the diffusion region in the diffusion region of one conductivity type forming the diffusion resistor, and the junction breakdown voltage of the diffusion region is increased. An input protection circuit characterized by lowering the voltage.
JP15625686U 1986-10-13 1986-10-13 Pending JPS6361152U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15625686U JPS6361152U (en) 1986-10-13 1986-10-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15625686U JPS6361152U (en) 1986-10-13 1986-10-13

Publications (1)

Publication Number Publication Date
JPS6361152U true JPS6361152U (en) 1988-04-22

Family

ID=31077699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15625686U Pending JPS6361152U (en) 1986-10-13 1986-10-13

Country Status (1)

Country Link
JP (1) JPS6361152U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54127684A (en) * 1978-03-27 1979-10-03 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54127684A (en) * 1978-03-27 1979-10-03 Nec Corp Semiconductor device

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