JPH0262835U - - Google Patents

Info

Publication number
JPH0262835U
JPH0262835U JP14096688U JP14096688U JPH0262835U JP H0262835 U JPH0262835 U JP H0262835U JP 14096688 U JP14096688 U JP 14096688U JP 14096688 U JP14096688 U JP 14096688U JP H0262835 U JPH0262835 U JP H0262835U
Authority
JP
Japan
Prior art keywords
transistor
source
emitter
gate
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14096688U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14096688U priority Critical patent/JPH0262835U/ja
Publication of JPH0262835U publication Critical patent/JPH0262835U/ja
Pending legal-status Critical Current

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  • Electronic Switches (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の第1の実施例を示す回路構成
図、第2図は第2の実施例を示す回路構成図、第
3図、第4図は従来技術の回路図である。 1……正電源ライン、2……接地ライン、3…
…NチヤネルMOS電界効果トランジスタ、4,
8,13,14,15,16……抵抗、5……C
MOS NANDゲート、6……ソレノイド負荷
、7,17……NPNトランジスタ、9……定電
圧ダイオード、10……ダイオード、11……N
チヤネルMOS電界効果トランジスタ、12……
CMOSインバータ、18……PNPトランジス
タ。
FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment, and FIGS. 3 and 4 are circuit diagrams of the prior art. 1...Positive power line, 2...Ground line, 3...
...N-channel MOS field effect transistor, 4,
8, 13, 14, 15, 16...Resistance, 5...C
MOS NAND gate, 6... Solenoid load, 7, 17... NPN transistor, 9... Constant voltage diode, 10... Diode, 11... N
Channel MOS field effect transistor, 12...
CMOS inverter, 18...PNP transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] バイポーラトランジスタにあつてはエミツタ側
、MOS電界効果トランジスタにあつてはソース
側(以下、MOS電界効果トランジスタの電極を
括弧内に示す)に負荷を接続してなる半導体スイ
ツチ回路において、前記トランジスタのベース(
ゲート)を抵抗を介してデイジタル制御回路の出
力に接続し、ベース・エミツタ間(ゲート・ソー
ス間)には前記トランジスタと同極性の第2のト
ランジスタのコレクタ・エミツタ(ドレイン・ソ
ース)を接続し、該第2のトランジスタのベース
バイアス回路(ゲートバイアス回路)を前記負荷
の一端が接続されている電源に接続したことを特
徴とする半導体スイツチ回路。
In a semiconductor switch circuit in which a load is connected to the emitter side in the case of a bipolar transistor and the source side in the case of a MOS field effect transistor (hereinafter, the electrodes of the MOS field effect transistor are shown in parentheses), the base of the transistor is (
The gate) is connected to the output of the digital control circuit via a resistor, and the collector-emitter (drain-source) of a second transistor having the same polarity as the transistor is connected between the base and emitter (gate-source). , a semiconductor switch circuit characterized in that a base bias circuit (gate bias circuit) of the second transistor is connected to a power source to which one end of the load is connected.
JP14096688U 1988-10-28 1988-10-28 Pending JPH0262835U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14096688U JPH0262835U (en) 1988-10-28 1988-10-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14096688U JPH0262835U (en) 1988-10-28 1988-10-28

Publications (1)

Publication Number Publication Date
JPH0262835U true JPH0262835U (en) 1990-05-10

Family

ID=31405611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14096688U Pending JPH0262835U (en) 1988-10-28 1988-10-28

Country Status (1)

Country Link
JP (1) JPH0262835U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011199401A (en) * 2010-03-17 2011-10-06 Furukawa Electric Co Ltd:The Power supply device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011199401A (en) * 2010-03-17 2011-10-06 Furukawa Electric Co Ltd:The Power supply device

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