JPH0398524U - - Google Patents
Info
- Publication number
- JPH0398524U JPH0398524U JP829990U JP829990U JPH0398524U JP H0398524 U JPH0398524 U JP H0398524U JP 829990 U JP829990 U JP 829990U JP 829990 U JP829990 U JP 829990U JP H0398524 U JPH0398524 U JP H0398524U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- mos transistor
- back gate
- gate
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
- Manipulation Of Pulses (AREA)
Description
第１図乃至第３図は本考案の実施例を説明する
ためのもので、第１図は電圧クランプ回路の基本
構成を示す回路図、第２図は第１図のＭＯＳトラ
ンジスタでのバツクゲート電圧に対するゲートＯ
Ｎ電圧の関係を示す特性図、第３図は本考案の応
用例を示す回路図である。第４図は従来の電圧ク
ランプ回路を示す回路図である。
１２……抵抗、１３……ＭＯＳトランジスタ、
１４……バイアス電源。
1 to 3 are for explaining an embodiment of the present invention. FIG. 1 is a circuit diagram showing the basic configuration of a voltage clamp circuit, and FIG. 2 is a circuit diagram showing the back gate voltage of the MOS transistor shown in FIG. gate O for
A characteristic diagram showing the relationship between the N voltage and FIG. 3 is a circuit diagram showing an application example of the present invention. FIG. 4 is a circuit diagram showing a conventional voltage clamp circuit. 12...Resistor, 13...MOS transistor,
14...Bias power supply.
Claims (1)
びドレインを接続して抵抗及びＭＯＳダイオード
からなる直列回路を構成し、上記ＭＯＳトランジ
スタのバツクゲートにバツクゲートとソース間が
逆電圧となる可変のバイアス電源を接続したこと
を特徴とする電圧クランプ回路。 The gate and drain of a MOS transistor are connected to the output side of the resistor to form a series circuit consisting of a resistor and a MOS diode, and a variable bias power supply is connected to the back gate of the MOS transistor to create a reverse voltage between the back gate and the source. A voltage clamp circuit featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP829990U JPH0398524U (en) | 1990-01-30 | 1990-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP829990U JPH0398524U (en) | 1990-01-30 | 1990-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0398524U true JPH0398524U (en) | 1991-10-14 |
Family
ID=31511931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP829990U Pending JPH0398524U (en) | 1990-01-30 | 1990-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0398524U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58129813A (en) * | 1982-01-27 | 1983-08-03 | Hitachi Ltd | Amplifying circuit |
| JPS6211320A (en) * | 1985-07-09 | 1987-01-20 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1990
- 1990-01-30 JP JP829990U patent/JPH0398524U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58129813A (en) * | 1982-01-27 | 1983-08-03 | Hitachi Ltd | Amplifying circuit |
| JPS6211320A (en) * | 1985-07-09 | 1987-01-20 | Matsushita Electric Ind Co Ltd | Semiconductor device |