JPS61111231U - - Google Patents
Info
- Publication number
- JPS61111231U JPS61111231U JP19595684U JP19595684U JPS61111231U JP S61111231 U JPS61111231 U JP S61111231U JP 19595684 U JP19595684 U JP 19595684U JP 19595684 U JP19595684 U JP 19595684U JP S61111231 U JPS61111231 U JP S61111231U
- Authority
- JP
- Japan
- Prior art keywords
- input
- voltage
- terminal voltage
- gate
- high frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案に係る高周波ＦＥＴスイツチ駆
動回路の一実施例を示す回路図、第２図はこの駆
動回路の他の実施例を示す回路図、第３図は従来
の駆動回路を示す回路図である。
１……デユアルゲートＦＥＴ、１ａ……第１の
ゲート端子、１ｄ……第２のゲート端子、２……
エミツタホロワトランジスタ、９……ツエナダイ
オード、１１……制御信号入力端子、２４……Ｃ
ＭＯＳ集積回路、２４ｃ……入力端子、２４ｄ…
…出力端子。
FIG. 1 is a circuit diagram showing one embodiment of a high frequency FET switch drive circuit according to the present invention, FIG. 2 is a circuit diagram showing another embodiment of this drive circuit, and FIG. 3 is a circuit diagram showing a conventional drive circuit. It is a diagram. 1... Dual gate FET, 1a... First gate terminal, 1d... Second gate terminal, 2...
Emitsuta follower transistor, 9...Zena diode, 11...Control signal input terminal, 24...C
MOS integrated circuit, 24c...input terminal, 24d...
...Output terminal.
Claims (1)
力とするエミツタホロワトランジスタと、このエ
ミツタホロワトランジスタのエミツタ端子電圧を
低電源端子電圧としツエナダイオードを介して入
力されるスイツチ制御信号を入力端子電圧とする
ＣＭＯＳ集積回路と、このＣＭＯＳ集積回路の出
力端子電圧を第２のゲート電圧としこの第２のゲ
ート電圧が高レベルの時第１のゲートに入力され
る入力信号を増幅して出力する高周波ＦＥＴスイ
ツチとを備えた高周波ＦＥＴスイツチ駆動回路。 An emitter follower transistor whose base input is a reference voltage generated by dividing a negative voltage, and a switch control signal input via a Zener diode with the emitter terminal voltage of this emitter follower transistor as a low power supply terminal voltage. A CMOS integrated circuit whose input terminal voltage is taken as an input terminal voltage, and an output terminal voltage of this CMOS integrated circuit which is used as a second gate voltage, and when this second gate voltage is at a high level, the input signal that is input to the first gate is amplified. A high frequency FET switch drive circuit equipped with a high frequency FET switch that outputs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19595684U JPS61111231U (en) | 1984-12-26 | 1984-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19595684U JPS61111231U (en) | 1984-12-26 | 1984-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61111231U true JPS61111231U (en) | 1986-07-14 |
Family
ID=30753585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19595684U Pending JPS61111231U (en) | 1984-12-26 | 1984-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61111231U (en) |
-
1984
- 1984-12-26 JP JP19595684U patent/JPS61111231U/ja active Pending
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