JPH0472723U

JPH0472723U -

Info

Publication number: JPH0472723U
Application number: JP11737790U
Authority: JP
Priority date: 1990-11-07
Filing date: 1990-11-07
Publication date: 1992-06-26

Description

[Brief explanation of the drawing]

第１図は、本考案の一実施例を示すラツチ回路
の回路図、第２図は、第１図と異なる実施例を示
すラツチ回路の回路図、第３図は、従来のラツチ
回路の一例を示す回路図である。１……一方のＣＭＯＳトランジスタ、２……他
方のＣＭＯＳトランジスタ、１１……第１のＭＯ
Ｓトランジスタ、１２……第２のＭＯＳトランジ
スタ、Ｑ１〜Ｑ４……トランジスタ、Ｄ／……
入力信号、Ａ……第１のノード、Ｂ……第２のノ
ード。 Fig. 1 is a circuit diagram of a latch circuit showing an embodiment of the present invention, Fig. 2 is a circuit diagram of a latch circuit showing an embodiment different from Fig. 1, and Fig. 3 is an example of a conventional latch circuit. FIG. 1... One CMOS transistor, 2... Other CMOS transistor, 11... First MO
S transistor, 12... second MOS transistor, Q1 to Q4... transistor, D/...
Input signal, A...first node, B...second node.

Claims

[Claims for Utility Model Registration] In a latch circuit having one CMOS transistor and the other CMOS transistor arranged in parallel,
a first MOS transistor connected between the gate of the channel MOS transistor and the gate of the n-channel MOS transistor;
A latch circuit comprising a second MOS transistor connected between a gate of a channel MOS transistor and a gate of an n-channel MOS transistor.