JPH0334328U - - Google Patents

Info

Publication number
JPH0334328U
JPH0334328U JP9377589U JP9377589U JPH0334328U JP H0334328 U JPH0334328 U JP H0334328U JP 9377589 U JP9377589 U JP 9377589U JP 9377589 U JP9377589 U JP 9377589U JP H0334328 U JPH0334328 U JP H0334328U
Authority
JP
Japan
Prior art keywords
fet
terminal
source terminal
fets
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9377589U
Other languages
Japanese (ja)
Other versions
JPH0756515Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989093775U priority Critical patent/JPH0756515Y2/en
Publication of JPH0334328U publication Critical patent/JPH0334328U/ja
Application granted granted Critical
Publication of JPH0756515Y2 publication Critical patent/JPH0756515Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の２相信号発生回路の一実施例
を示す回路構成図、第２図〜第４図は従来例を示
す図である。 １……バツフア回路、２……第１のソースフオ
ロア回路、２ａ……第３のＦＥＴ、２ｂ……第４
のＦＥＴ、２ｃ……ダイオード、３……第２のソ
ースフオロア回路、３ａ……第５のＦＥＴ、３ｂ
……第６のＦＥＴ、５……第１のＢＦＬ回路、５
ａ……第１のＦＥＴ、６……第２のＢＦＬ回路、
６ａ……第２のＦＥＴ。 FIG. 1 is a circuit diagram showing an embodiment of the two-phase signal generating circuit of the present invention, and FIGS. 2 to 4 are diagrams showing conventional examples. 1... Buffer circuit, 2... First source follower circuit, 2a... Third FET, 2b... Fourth
FET, 2c...Diode, 3...Second source follower circuit, 3a...Fifth FET, 3b
...Sixth FET, 5...First BFL circuit, 5
a...first FET, 6...second BFL circuit,
6a...Second FET.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力に対応して反転信号を出力するソース端子
がコモン電位に接続された第１のＦＥＴを含む第
１のＢＦＬ回路と、前記入力に対応して非反転信
号を出力するゲート端子がコモン電位に接続され
た第２のＦＥＴを含む第２のＢＦＬ回路からなる
２相信号発生回路であつて、前記第１のＦＥＴの
ゲート端子には第３、第４のＦＥＴがダイオード
を介して接続された第１のソースフオロアからの
出力が接続され、前記第２のＦＥＴのソース端子
には第５、第６のＦＥＴのソースとドレインが接
続した第２のソースフオロアからの出力を入力す
るとともに前記第６のＦＥＴのゲート幅を前記第
２のＦＥＴのゲート幅の約２倍にした事を特徴と
する２相信号発生回路。 A first BFL circuit includes a first FET whose source terminal that outputs an inverted signal in response to an input is connected to a common potential, and a gate terminal that outputs a non-inverted signal in response to the input is connected to a common potential. A two-phase signal generation circuit consisting of a second BFL circuit including a connected second FET, wherein third and fourth FETs are connected to the gate terminal of the first FET via a diode. The output from the first source follower is connected to the source terminal of the second FET, and the output from the second source follower to which the sources and drains of the fifth and sixth FETs are connected is inputted to the source terminal of the second FET. A two-phase signal generation circuit characterized in that the gate width of the FET is approximately twice the gate width of the second FET.
JP1989093775U 1989-08-09 1989-08-09 2-phase signal generation circuit Expired - Lifetime JPH0756515Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989093775U JPH0756515Y2 (en) 1989-08-09 1989-08-09 2-phase signal generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989093775U JPH0756515Y2 (en) 1989-08-09 1989-08-09 2-phase signal generation circuit

Publications (2)

Publication Number Publication Date
JPH0334328U true JPH0334328U (en) 1991-04-04
JPH0756515Y2 JPH0756515Y2 (en) 1995-12-25

Family

ID=31643142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989093775U Expired - Lifetime JPH0756515Y2 (en) 1989-08-09 1989-08-09 2-phase signal generation circuit

Country Status (1)

Country Link
JP (1) JPH0756515Y2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53139456A (en) * 1977-05-11 1978-12-05 Nec Corp Clock driver circuit
JPS62195915A (en) * 1986-02-24 1987-08-29 Rohm Co Ltd Switching circuit
JPH01147916A (en) * 1987-12-03 1989-06-09 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53139456A (en) * 1977-05-11 1978-12-05 Nec Corp Clock driver circuit
JPS62195915A (en) * 1986-02-24 1987-08-29 Rohm Co Ltd Switching circuit
JPH01147916A (en) * 1987-12-03 1989-06-09 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit

Also Published As

Publication number Publication date
JPH0756515Y2 (en) 1995-12-25

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