JPH0480050U - - Google Patents

Info

Publication number
JPH0480050U
JPH0480050U JP12555690U JP12555690U JPH0480050U JP H0480050 U JPH0480050 U JP H0480050U JP 12555690 U JP12555690 U JP 12555690U JP 12555690 U JP12555690 U JP 12555690U JP H0480050 U JPH0480050 U JP H0480050U
Authority
JP
Japan
Prior art keywords
terminal
inverting input
input terminal
path
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12555690U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12555690U priority Critical patent/JPH0480050U/ja
Publication of JPH0480050U publication Critical patent/JPH0480050U/ja
Pending legal-status Critical Current

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Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案実施例の構成を示す図。第2図
は従来例の構成を示す図。第3図は第1図のスイ
ツチ回路の具体例を示す図。 A……増幅器、B……入力回路、C……スイツ
チ回路、R……抵抗、E,F,G……外部端子、
Q1……トランジスタ。
FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a diagram showing the configuration of a conventional example. FIG. 3 is a diagram showing a specific example of the switch circuit shown in FIG. 1. A...Amplifier, B...Input circuit, C...Switch circuit, R...Resistor, E, F, G...External terminal,
Q1...transistor.

Claims (1)

【実用新案登録請求の範囲】 入力回路が非反転入力端子に接続され、出力端
子と反転入力端子との間の経路に抵抗が挿入され
、この出力端子とこの反転入力端子とが外部端子
に接続された増幅器をもつ半導体集積回路におい
て、 上記反転入力端子とこの端子に接続された外部
端子との間の経路を開閉するスイツチング手段 を備えたことを特徴とする半導体集積回路。
[Claims for Utility Model Registration] An input circuit is connected to a non-inverting input terminal, a resistor is inserted in a path between an output terminal and an inverting input terminal, and this output terminal and this inverting input terminal are connected to an external terminal. 1. A semiconductor integrated circuit having an amplifier comprising: a switching means for opening/closing a path between the inverting input terminal and an external terminal connected to the terminal;
JP12555690U 1990-11-27 1990-11-27 Pending JPH0480050U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12555690U JPH0480050U (en) 1990-11-27 1990-11-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12555690U JPH0480050U (en) 1990-11-27 1990-11-27

Publications (1)

Publication Number Publication Date
JPH0480050U true JPH0480050U (en) 1992-07-13

Family

ID=31873150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12555690U Pending JPH0480050U (en) 1990-11-27 1990-11-27

Country Status (1)

Country Link
JP (1) JPH0480050U (en)

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