JPS6025318A - Pseudo static flip-flop - Google Patents

Abstract

PURPOSE:To decrease the power consumption at stand-by state by constituting a latch circuit for an output side only of a clocked inverter turned off at the stand-by state in a flip-flop using the clocked inverter. CONSTITUTION:The latch circuit is constituted by an inverter 36 and an inverter 38 controlled with a control signal CNTL and provided to an output side of the clocked inverter 35 turned off at the stand-by state in a CMOS dynamic D flip- flop comprising the clocked inverters 32, 25 and the inverters 32, 36. The inverter 38 is turned off at the operating state and the FF acts like the dynamic type FF and the inverter 38 is turned on at the stand-by state and the FF latches a signal. Since the input potential of the inverter 36 at the stand-by state does not reach the intermediate level, no through-current flows.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a circuit system for reducing the cell size of a flip-flip circuit in a CM 0.5 circuit and reducing current consumption in a standby state. .

[Background of the invention]

FIG. 1 is an internal circuit diagram of a clocked inverter.

FIG. 2 is a symbol diagram of a built-in inverter, FIG. 6 is a conventional static flip-flop circuit, and FIG. 4 is a diagram showing operating waveforms of various parts. In Figure 1, 1
is a clock signal input, 2 is a clock signal input with the opposite polarity to 1, 3 is a data signal input, 4 and 5 are PMOS transistors, 6.7 is an NMOS transistor, 8 is an output terminal, and in Fig. 2, 9 is an output terminal. Data signal terminal, 10 is a symbol diagram of a clocked inverter.

11 is an output terminal, 12 is a data input signal g input terminal, 15.18 is a clocked inverter that is turned on when the clock φ is at a low level, 15, 1 (S is turned on when the clock φ is at a high level) clocked inverter,
14, 17.21 is an inverter.

19 and 20 are output terminals.

As shown in FIG. 4, it is clear that the flip-flop of FIG. 3 operates as a DJJl static flip-flop that outputs data at the rising edge of the clock φ.

However, in a single circuit, clocked inverters 15, 1
8 operates with the clock φ, so the transistor size is large.

The cell size is large, and when a large number of them are used as an LSi circuit, the LSi chip size becomes large.

FIG. 5 shows an example of another conventional circuit, which is a dynamic D-type flip-flop, and FIG. 6 shows operating waveforms of each part.

In FIG. 5, 22 is a data 4W input terminal, 23 is a closed inverter that is turned on when the a clock input signal φ is at a low level, 24 and 26 are inverters, and 25 is an inverter that is turned on when the clock input signal φ is at a high level. Clocked inverter to turn on.

28 and 29 are stray capacitances, 30 is an inverter, and 27 is an output terminal.

In Figure 6, when the control signal is at high level,
When the clock φ is input, the circuit operates 1. When the clock φ is at the a-level, the clocked inverter 23 is turned on, inverts the state of the data input signal, and holds the state in the stray capacitor 28.

This clocked inverter 25 is off. Next, when φ becomes high level, clocked inverter 2
3 turns off and 25 turns on.

The state held by the capacitor 28 is held by the storage 29 and output to the output terminal 27 through the inverter 26. This circuit thus operates as a dynamic D-type flip-frog.

Next, the control signal (?
At this point, the reverse lock φ stops at the a- level, so the reverse locked inverter 23 turns on, the locked inverter 25 turns off, and the charge held in the capacitor 29 is reduced.

It gradually discharges, and the potential of Q becomes an intermediate level as shown in Q in FIG. Therefore, a direct current flows through the power supply current of the inverter 26 as indicated by inn in FIG. 6, and the current consumption in the standby state increases.

In this way, the dynamic flip-frog shown in FIG. 5 has the drawbacks that it has fewer elements and smaller cell size than the static flip-flop 70 block shown in FIG. .

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and provide a flip-flop with a small cell size.

[Summary of the invention]

In the operating state, the present invention has a dynamic flip 7
In the standby state BRTC, a feedback circuit is provided so that a latch is configured by control No. We aim to
Moreover, the current consumption in the standby state is minimized.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained with reference to FIGS. 7 and 8. FIG. 7 shows a specific embodiment of the present invention, and FIGS. It is something that

In FIG. 7, 61 is a data input terminal, 62 is a clock (a clocked inverter that is turned on when the N signal φ is at a low level, 35 is a gated inverter that is turned on when a clock φ is at a high level, and 38 is a control signal CNTL). A clocked inverter that turns on when %54 is at a low level,
56. 40 and 41 are inverters; 33. and 37 is stray capacitance.

39 is an output terminal, and 42 is a control signal input terminal.

As shown in FIG. 8, when the control signal CNTL is at high level, the clock (iW signal φ) is input.

Since the squared inverter 38 is turned off and turned on, one circuit operates as a dynamic D-type fringe lobe as in FIG. Next, control (call signal C
, 'V T L becomes low level, the clock signal stops at the low level, and enters the standby state, the left inverter 38 turns on, the inverter 66 and the clocked inverter 38 form a latch, and the clock signal stops at the low level. The inverter 35 is turned off, but the inverter 360 maintains its human power level. Sunda, clocked, f converter 3
2 is in the on state, the input potential of the inverter 964 is maintained at 0.degree. C., and the current consumption does not increase even in the standby state.

Moreover, the clocked inverter 68 is -fttlNIl1
1 signal CN T J, and operates in accordance with a clock signal φ. The operating speed is slower than that of the clocked inverters 15 and 18 in FIG. 6, and the transistor size may be the smallest.

〔Effect of the invention〕

According to the present invention, by minimizing the current consumption during standby state and reducing the cell size of the flip-flop N-way, it is possible to reduce the chip size when used in Mo5tsi.

[Brief explanation of the drawing]

FIG. 1 is an internal circuit diagram of a beam-mounted inverter. Figure 2 is a symbol diagram of a clocked inverter. Figure 3 is a circuit diagram of a conventional static 7)4 flip-flop, Figure 4 is an operating waveform diagram of each part, Figure 5 is a circuit diagram of a conventional dynamic Dm flip-flop, Figure 6 is an operating waveform diagram of each part, and Figure 6 is a circuit diagram of a conventional dynamic Dm flip-flop. FIG. 7 is a circuit diagram of a pseudo-static flip-frog according to an embodiment of the present invention, and FIG. 8 is an operation waveform diagram of each part. 1... Clock signal input 2... Clock signal input terminal 5... Data 4] input terminal 4.5... PMOS transistor 6.7... NMOS transistor 8... Output terminal 39...・Output terminal 42...Control number input terminal 11 Figure 3 15 Illustrated Q4 Yo° ゛

Claims (1)

[Scope of Claims] t. A first gated inverter having a data signal input, a clock signal input, a control No. 46 input, and a data signal output in a CMO5 circuit and inputting the data No. 8;
a second inverter inputting the output of the first clocked inverter; a third clocked inverter inputting the output of the second inverter; and a third clocked inverter inputting the output of the second clocked inverter. a fourth inverter inputting an output; and an 81!5 clocked inverter inputting an output of the fourth inverter, the output of the fifth clocked inverter being input to the fourth inverter. The first clocked inverter is turned on when the a clock signal is at a low level. The third clocked inverter is turned on when the clock signal is at a high level, and the fifth clocked inverter is turned on only when the control input signal is in a standby state, and the data signal output is turned on. A pseudo-static flip-frog, characterized in that it is taken out from the fourth inverter.