JPH0262797A - Dynamic type shift register - Google Patents

Abstract

PURPOSE:To attain low power consumption by constituting 2-input NAND circuit and transfer gate. CONSTITUTION:A first 2-input NAND circuit 15 making a data input signal 11 and a clock signal 12 into an input and a first transfer gate 16 making the output (a) of the first 2-input NAND circuit into a data input and making a clock signal 12 into a clock input are provided. Further, a second 2-input NAND circuit 15 making the output(b) of the first 2-input NAND circuit and the negative-phase signal of the clock signal into the input and a second transfer gate 16 making the output (a) of the second 2-input NAND circuit 15 into a data input and making the negative-phase signal into the clock input are provided. Thus, a period when through current flows is shortened and the power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a dynamic shift register applied to logic circuits.

2. Description of the Related Art A conventional dynamic shift register will be explained below.

FIG. 3 is a block diagram of a conventional dynamic shift register, in which numeral 31 is an inverter and numeral 16 is a transfer gate. FIG. 4 is a specific circuit diagram of a conventional example.
1 is a data input terminal, 12 is a clock input terminal, 13 is a negative phase clock input terminal, 14 is a data output terminal, 21 is a power supply terminal, 22 is a ground terminal, 23 is a depletion type MOS transistor, and 24 is an enhancement type MOS transistor.
It is a transistor.

As shown in the timing chart of FIG. 5, when a clock input, a reverse phase clock input, and a data input are applied, the node d changes from a high level to a low level when the data input changes from a low level to a high level. Thereafter, when the clock input goes high, the node e goes low and the node f goes high. When the reverse phase clock input signal goes high, the data output goes high. On the other hand, when the data input becomes high level or θ low level, the node d becomes high level, and then when the clock input becomes high level, the node e becomes high level and the node f becomes low level. When the reverse phase clock input goes high, the data output goes low. In this way, the data output is delayed by one clock input cycle from the data input.

Problems to be Solved by the Invention However, in the above conventional configuration, when the input of the inverter is at a high level, a through current flows through the inverter.
Therefore, there was a problem that power consumption was large.

The present invention solves the above problems and aims to provide a dynamic shift register with low power consumption.

Means for Solving the Problems To achieve this object, the dynamic shift register of the present invention is composed of a two-input NAND circuit and a transfer gate.

Effect: This configuration shortens the period during which the through current flows,
Thereby, low power consumption can be achieved.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of the present invention. In FIG. 1, 11 is a data input terminal, 12 is a clock input terminal,
13 is a reverse phase clock input terminal, 14 is a data output terminal,
15 is a two-input NAND circuit, and 16 is a transfer gate. FIG. 2 is a specific circuit diagram of an embodiment of the present invention, in which 11 is a data input terminal, 12 is a clock input terminal, 13 is an anti-phase clock input terminal, 14 is a data output terminal, 21 is a power supply terminal, 22 is a ground terminal, 23 is a depletion type MOS transistor, and 24 is an enhancement type MOS transistor.

The operation of the specific circuit of this embodiment will be explained.

As shown in the timing chart of Fig. 6, when the clock input, reverse phase clock input, and data input are applied, the node a becomes 1, the data input changes from low level to high level, and the ref-lock input changes to high level. When the signal changes from high level to low level.

At the same time, since the clock input is at high level, node b also changes from high level to low level. Thereafter, when the reverse phase clock signal becomes high level, node C becomes high level because node b is low level, and the data output becomes high level. At this time, node a is at a high level regardless of data input. On the other hand, when the data input goes from high level to low level and the clock input goes to high level, node a remains at high level and node b also goes to high level. After that, when the reverse phase clock signal becomes high level, the node C becomes low level, and the data output also becomes low level. Therefore, as in the conventional example, the data output is delayed from the data input by one cycle of the clock input. According to this embodiment, the through current flowing to node a occurs only when the clock input is at high level and the data input is at high level, and the through current flowing to node C occurs only when the reverse phase clock signal is at high level and node b is at high level. Only at level.

As described above, according to this embodiment, by arranging the enhancement type MOS transistor whose gate is the clock input in series with the enhancement type MOS transistor whose gate is the data input, the period during which the through current flows can be shortened. can.

In the above embodiment, the load of the two-input NAND circuit is a depletion type MOS transistor, but the load may be a resistor.

Effects of the Invention According to the present invention, a first 2-input NAND circuit receives a data input signal and a clock signal as input, the output of the first 2-input NAND circuit is used as a data input, and the clock signal is used as a clock input. and a second two-input NAN whose inputs are the output of the first transfer gate and an opposite phase signal of the clock signal.
By providing a D circuit and a second transfer gate that uses the output of the second two-input NAND circuit as a data input and the reverse phase signal as a clock input, the period during which a through current flows can be shortened and power consumption can be reduced. (This makes it possible to realize a dynamic shift register.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a dynamic shift register according to an embodiment of the present invention, FIG. 2 is a specific circuit diagram thereof, FIG. 3 is a block diagram of a conventional dynamic shift register, and FIG. 4 is a specific diagram thereof. FIG. 5 is a timing chart of a conventional dynamic shift register, and FIG. 6 is a timing chart of a dynamic shift register according to an embodiment of the present invention. 11...Data input, 12...Clock input, 13...Reverse phase clock input, 14...
...Data output, I5...2 input NAND
Circuit, 16...Transfer gate, 21.
...Power supply, 22...Grounding, 23...
・・Depression type MOS transistor, 24・・
...Enhancement type MOS transistor, 31
...Inverter. Name of agent: Patent attorney Shigetaka Awano and 1 other person #-11 Deke, Heka f+---Data output l4---Data output Figure 2 Figure 4ゝ22 Figure Figure

Claims (1)

[Claims] A first input signal receiving a data input signal and a clock input signal.
a 2-input NAND circuit; a first transfer gate having the output of the first 2-input NAND circuit as a data input and the clock input signal as an input; the output of the first transfer gate and the clock input signal; a second 2-input NAND circuit which receives as input the negative phase signal of , and the output of the second 2-input NAND circuit as data input;
A dynamic shift register comprising a second transfer gate whose clock input is a signal with the opposite phase of the clock input signal.