JPS63155822A - Mos logic circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a through current at a time other than acting time and to facilitate the timing of a clock signal by using a circuit consisted of a MOS transistor for load and a logic circuit part connecting to the former in series connection. CONSTITUTION:The PMOS 20 for load controlled of its turning on/off by means of a synchronizing clock signal phi and the logic circuit part 21 and that takes the logic of plural input signals 10-12 that shift at a time when the PMOS 20 is in ON-status, are connected between a power supply +VCC terminal and the ground in series connection through an output terminal N20. A signal whose output level is determined by the proportion between the resistances of the PMOS 20 and the circuit part 21 at a time when they are in ON-status, is outputted to the terminal N20. With this constitution, the circuit operates when the signal phi of pulse width (t) is in a low level, the PMOS 20 comes in the ON-status letting the signals 10-12 inputted, and the result of the logical operation of the circuit part 21 is outputted to the terminal N20. Thereafter, if the signal phi comes in a high level, the PMOS 20 turns off, coming in a waiting status, and the output is held.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an IO3 logic circuit (consisting of MOS transistors (metal gate field effect transistors)).

(Prior art) Conventionally, as a technology in this field, Japanese Patent Application Laid-Open No. 59-9
There were those described in JP-A No. 9823, JP-A-59-125125, and JP-A-59-186425. The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing a configuration example of a conventional ratio-type asynchronous MO8 logic circuit.

This IO8 logic circuit has a P-channel) IO3 transistor (hereinafter referred to as PMOS) 1 for load, and its PM
The source of O61 is connected to the power supply VCC, the drain is connected to the output terminal N1, and the gate is connected to the ground, so that it is always on. A logic circuit section 2 is connected between the output terminal N1 and the ground. Logic circuit section 2 is an N-channel MO
3 consisting of S transistors (hereinafter referred to as N)IO8)
This circuit is composed of a human-powered NOR circuit (hereinafter referred to as a NOR circuit), and has terminals T1... for input signals IO and 11°I2.
Ding 2. It has terminals 3 and 4 and 5 terminals for circuit connection,
The terminal T4 is connected to the output terminal old, and the terminal T4 is connected to the ground.

FIG. 3 is a circuit diagram showing an example of the configuration of the logic circuit section 2 in FIG. 2. This logic circuit section 2 has three NHO33, 4, 5
are connected in parallel between terminals 4 and 15.

FIG. 4 is an operational waveform diagram of FIG. 2. At the output terminal N1 in FIG. 2, both PH081 and the logic circuit 2 are in the on state when the low level is output, and the resistance (hereinafter referred to as on resistance) when in the on state with the logic circuit section 2 such as PMOS1.
The output level is determined by the ratio. Therefore, the on-resistance of PMOS1 is made higher than the on-resistance of N)IQs3, 4, and 5, and is designed to have an output level sufficiently lower than the threshold voltage of the next stage. P) When IQs 1 is on and any of NHO33, 4, and 5 is on, a through current flows from the power supply VCC to the ground. On the other hand, at high level output, NHO33,
4 and 5 are in the off state, the output level is approximately the power supply voltage level, and no through current occurs.

FIG. 5 is a circuit diagram showing an example of the configuration of a conventional synchronous logic circuit. This logic circuit is PMOS10 for precharging.
, 880311 for inhibiting operation during precharging, and NH
It has a logic circuit section 12 made up of a three-way NOR circuit made up of O3. pHosio is connected between the power supply +VCC and the output terminal N2, and is controlled on and off by the synchronizing clock signal φ, and NHO311 is connected between the terminal T5 of the interrogation circuit section 12 and the ground, and is controlled by the synchronizing clock signal φ.
Controlled on and off. The logic circuit section 12 has terminals 11 to
5, whose end f''5 is connected to said NHO3I 1, whose terminal 4 is connected to the output terminal N2, and whose terminal T
I, T2.13: Input signal 10. II
, 12 and outputs a corresponding signal from the output terminal N2.

FIG. 6 is an operational waveform diagram of FIG. 5. In the circuit of FIG. 5, when the synchronization clock signal φ is at a low level of logic 1g00, the circuit of FIG. 5 enters the precharge state PR,
Charge up the output terminal N2.

At this time, NHO 311 is in an off state to prevent the generation of through current. Next 1 clock signal φ is logic 411
When It goes high, the circuit of FIG. 5 is activated and the input signal 10. The logical operation results for II and I2 are output from output terminal N2. In the circuit shown in FIG. 5, almost no through current occurs.

FIG. 7 is a circuit diagram when the synchronous type HO3 logic circuit shown in FIG. 5 is connected in two stages. This circuit is PH08IO-1,N
)fO31m-1 and logic circuit section 12-1 and P)103
10-2, NHO311-2, and a logic circuit section 12-2, and the output terminal old 1 of the previous stage is connected to the logic circuit section 12-2 of the subsequent stage.
2, and the output signal is taken out from the output terminal N12 of the subsequent stage. Here, PH08IO-1 and NHO311-1 in the previous stage are L for synchronization.
"ON/OFF-controlled by the switch signal φ1, and the subsequent stage PH0
510-2 and N) 10311-2 are controlled to turn off the synchronization clock signal φ2. In addition, the logic circuit section 12
-1.12-2 is composed of a three-person NOR circuit consisting of an OS, and the terminal TI of the logic circuit section 12-1 in the previous stage,
T2. Three human power signals IO, II, I2 are applied to T3, and terminals TI, T2. The output signal from the previous stage and the two-manpower signal T3. I4 are respectively input.

FIG. 8 is an operational waveform diagram of FIG. 7. The circuit in Figure 7 is
Clock signal φ1. Output terminal old 1 due to falling of φ2
, N12 is precharged. After time 10 has elapsed, clock signal φ1 goes high and P)! 0310
-1 goes into the off state, the logic circuit section 12-1 at the previous stage goes into the operating state, and the input signal 10. The signal at the output terminal N11 changes depending on the states of II and I2, but at this point, the output terminal 812 at the subsequent stage is still in the precharged state. After the elapse of time (tO+tl), the clock signal φ
2 becomes high level, the subsequent logic circuit section 12-2
becomes operational, and the signal at its output terminal 812 changes. Then, when the time (tO+tl+t2> has elapsed), the clock signals φ1 and φ2 rise, and the same operation as described above is repeated. In FIG. 8, ta is the falling time of the output terminal Nil level, and tb is the falling time of the output terminal N12. The falling time of each level is shown.

However, the t1os logic circuit with the above configuration had the following problems.

(i) In the ratio-type asynchronous MOS logic circuit as shown in FIG. 2, a through current always flows when the output terminal N1 is at a low level. Therefore, especially in the case of a CMO8 (complementary type 803) circuit, the low power consumption characteristic that is a feature of CHO3 is lost, and there is also the problem that it is not possible to realize a standby state in which the operation is stopped, output data is retained, and the through current is stopped. There was a point.

(ii) The synchronous 808 logic circuit shown in Figure 5 must be designed to prevent malfunction by adjusting the timing of the synchronizing clock signal when multiple stages are connected as shown in Figure 7. Must be. That is, to explain with reference to FIGS. 7 and 8, when setting the time difference t1 between the clock signals φ1 and φ2, if the time t1 is shortened, the logic circuit section 1 at the subsequent stage is
2-2 enters the operating state, and the precharged charges at the subsequent stage are discharged, causing a malfunction. On the other hand, if the time t1 is increased, the malfunction will disappear, but this 803
The operation delay of the logic circuit becomes longer. Therefore, there was a problem in that it was difficult to set the time difference t1 between the clock signals φ1 and φ2.

The present invention solves the problems that the prior art had, in that a standby state cannot be realized due to the constant flow of through current in the ratio type asynchronous MO8 logic circuit, and in the synchronous type MO8 logic circuit.
The present invention provides an 803 logic circuit which solves the problem of difficulty in timing design of synchronizing clock signals in the 03 logic circuit.

(Means for Solving the Problems) In order to solve the above problems, the present invention has an output level of 2.
In the HO3 logic circuit, which is determined by the on-resistance ratio of the MOS transistors connected in series in more than one stage, it is turned on by the synchronization clock signal.

A load HO3 transistor that is controlled off and a plurality of M
Six rows of logic circuit units configured of OS transistors and which take the logic of a plurality of input signals that change when the load HOS transistor is in the on state are connected between the power supply and the ground via output terminals, and the load A signal having an output level determined by the ratio of resistance in the ON state of the HO3 transistor and the logic circuit section is outputted from the output terminal.

(Function) According to the present invention, since the MO8 logic circuit is configured as described above, the load HO3 transistor is controlled on and off by the synchronization clock signal, and the logic circuit section is operated in the on state. work.

This makes it possible to prevent the generation of through current except during operation and to facilitate the timing of the clock signal. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of an HO3 logic circuit showing a first embodiment of the present invention.

This HO3 logic circuit has a load P)fO820 that is controlled on and off by the synchronization clock signal φ, and its PM
The source of the OS 20 is connected to the power supply +vCC, and the drain is connected to the logic circuit section 21 via the output terminal N20.

The logic circuit section 21 is a circuit composed of a three-way NOR circuit consisting of N) fO3, and has terminals for input signals IO, 11, and 12 and terminals 4 and 4 for circuit connection. T5, its terminal T4 is connected to the output terminal N20, and its terminal 5 is connected to the ground. This logic circuit section 21 is composed of, for example, three circuits O8 connected in parallel as in the conventional case shown in FIG. Here, the output low level of the output terminal N20 is determined by the on-resistance of the PMOS 2G and the NHO in the logic circuit section 21.
The on-resistance ratio is set at a ratio of 3 to the on-resistance, and is designed to have a sufficient margin for the threshold voltage of the next stage logic circuit. In addition, input signals IO, II,
I2 is designed to change when the synchronizing clock signal φ is at a low level.

FIG. 9 is an operational waveform diagram of FIG. 1. When the synchronization clock signal φ with a pulse width t is at a low level, it becomes active, and P
When the MOS 20 is turned on, the logic operation result of the logic circuit section 21 is output to the output terminal N depending on the state of the input signal l0-I2.
20. Thereafter, when the clock signal φ becomes high level, the PMOS 20 is turned off and enters a standby state, and the output is held.

In this embodiment, although it is a ratio type HO3 logic circuit, a standby state is provided, so that no through current flows except during operation, and power consumption can be reduced. Moreover, since difficult timing design unlike the synchronous type 803 logic circuit is not required, the design becomes easy. In particular, PLA (programmable logic array), which is widely used in microprocessors, etc.
When applied to multi-input logic circuits, such as those in It is possible to reduce this and improve performance (function). Furthermore, due to its low power consumption, it can be used in battery-powered microprocessor systems, etc.

In the HO3 logic circuit shown in Figure 1, the output holding in the standby state is dynamic and is performed only by the capacitance of the output terminal N20, so if static output holding is required, an output holding circuit is connected to the output terminal 820. I think it is necessary to add it.

FIG. 10 is a diagram showing a modification of FIG. 1 in which an output holding circuit is added to the output terminal N20 of the HO3 logic circuit in FIG. 1. The output holding circuit includes an inverter consisting of PMOS22 and N10323 connected in series between power supply VCC and the ground, PMOS24 connected between power supply VCC and output terminal N20, and PMOS22 and NHO32.
3 is connected to the output terminal 820, and its PM
Each drain of OS22 and NHO323 is P)1082
Connected to gate 4. This output holding circuit holds the high level or low level of the output terminal N20 as a logic 141 u
Or it latches and holds in the form of 0''.Such an output holding circuit needs to be added even in conventional synchronous 10S logic circuits when static holding is required. be.

FIG. 11 is a circuit diagram of an 803 logic circuit showing a second embodiment of the present invention. This [08 logic circuit replaces the load P140S20 in Fig. 1 with two PH0820-1, 20
- It is divided into two parts. Here, two PMO62
0-1゜20-2 is connected in series between the power supply element vCC and the output terminal N20, and one of them, PMOS20-1, has a small on-resistance value and is turned on and off by the synchronization clock signal φ to reduce the through current. The other PMOS20
-2 has a large on-resistance value for ratio, and its gate is grounded and is always on. Even in this configuration, operation waveforms similar to those shown in FIG. 9 are shown, and advantages similar to those of the first embodiment are obtained. If static output holding is required, an output holding circuit as shown in FIG. 10 may be connected to the output terminal N20.

FIG. 12 is a circuit diagram of a MOS logic circuit showing a third embodiment of the present invention, and FIG. 13 is a circuit diagram of its logic circuit section.

The IO8 logic circuit in FIG. 12 includes an NHO 330 connected between the output terminal N30 and the ground, and a logic circuit section 31 connected between the output terminal N30 and the power supply +VCC. N) The IO 530 is controlled on and off by an inverted clock signal T for synchronization. The logic circuit section 31 is composed of a three-way NOR circuit consisting of PMO5, and its terminals 11 to 5 are
Among them, terminal TI, terminal 22, terminal 3 has 3 human power signals 110.

Ill, 112 is input, terminal 4 is output terminal N
30, terminals T5 are connected to the power supply VCC, respectively.

As shown in FIG. 13, this logic circuit section 31 has three P
H0332, 33, and 34 are connected in series.

In the above configuration, when the inverted clock signal T is at a high level, N) 10330 is turned on and becomes operational, and the logic circuit unit 31 calculates the NOR of the input signals 110, 111, and 112 that change at that time, and outputs the result. It is output from terminal N30. In this circuit as well, the output high level is determined by the ratio of the on-resistances of PH0332, 33, 34 and NHO330, as in the above embodiment.

Although the above first to third embodiments have explained the CHO3 logic circuit, the application of the present invention is not limited to CMO8.
It is also applicable to NHO3 logic circuits and P)108 logic circuits.

FIGS. 14 and 15 show the fourth example when applied to the N140S logic circuit. FIG. 7 is a circuit diagram showing a fifth example.

In the fourth embodiment shown in FIG. A circuit section 41 is connected. In the fifth embodiment shown in FIG. 15, a depression type load N10350 is connected between the power supply VCC and the output terminal N50,
A logic circuit section 51 of a three-man power NOR circuit consisting of an enhancement type NOR circuit 103 is connected between the NOR circuit 50 and the ground.

Even in the circuits shown in FIGS. 14 and 15, the same functions and effects as in the above embodiment can be obtained.

Further, the present invention can be similarly applied to PMOS logic circuits. Roughly speaking, in the above embodiment, the logic circuit section 21.31°41
, 51 are configured with three-man NOR circuits, the number of inputs may be other numbers, and the logical configuration may be other circuits such as AND circuits and OR circuits.

(Effects of the Invention) As described above in detail, according to the present invention, the HO3 logic circuit is turned on by the synchronization clock signal.

Since it is composed of a load transistor 803 that is turned off and a logic circuit section connected in series with it, even though it is a ratio type logic circuit, no through current flows except during operation.
In addition to reducing power consumption, it also eliminates the need for difficult timing design, unlike synchronous logic circuits, and can be expected to have the effect of simplifying design.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an 803 logic circuit showing a first embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional asynchronous type 803 logic circuit, and Fig. 3 is a circuit diagram of the logic circuit section of Fig. 2. , Fig. 4 is an operating waveform diagram of Fig. 2, Fig. 5 is a circuit diagram of a conventional synchronous type 803 logic circuit, Fig. 6 is an operating waveform diagram of Fig. 5, and Fig. 7 is a two-stage diagram of Fig. 5. Circuit diagram of connection 803 logic circuit, FIG.
Figure 9 is the operation waveform diagram of Figure 1, Figure 10 is the operation waveform diagram of Figure 1.
The figure is a circuit diagram showing a modified example of Figure 1, Figures 11 and 12.
The figure is part 2 of the present invention. A circuit diagram of a MOS logic circuit showing the third embodiment, FIG. 13 is a circuit diagram of the logic circuit section of FIG. 12,
FIGS. 14 and 15 show the fourth embodiment of the present invention. 103 is a circuit diagram of a 103 logic circuit showing a fifth embodiment; FIG. 20, 20-1.20-2...PMOS, 21
, 31, 41, 51... logic circuit section, 30.4
0.50...NHO2, IO, II, 12°110, Ill, 112...Input signal, 820, 830. 840, N50...Output terminal, +VCC
...Power supply, φ...Clock signal, T.
...Inverted clock signal. Applicant's agent: Sei I Kakimoto
≧ Operation waveform in Fig. 7 Fig. 8 Fig. 1 Machimena form in Fig. 9 Fig. 1; β N50: Output terminal

Claims (1)

[Claims] A load MOS transistor that is controlled on and off by a synchronization clock signal, and the load MOS transistor that is composed of a plurality of MOS transistors.
A logic circuit section that takes the logic of a plurality of input signals that change when the transistor is in the on state is connected in series between the power supply and the ground via the output terminal, and the on state of the load MOS transistor and the logic circuit section is connected in series between the power supply and the ground through the output terminal. MO, characterized in that a signal of an output level determined by the ratio of resistance at the time is outputted from the output terminal.
S logic circuit.