JP2002026697A - Flip-flop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of a conventional flip-flop circuit that has in creased the circuit area because number of required transistors (TRs) is larger in a conventional configuration having been proposed and consisting of an input section employing a dynamic circuit and of an output section employing a static circuit and adopting a latch circuit that latches data by using a strobe signal whose pulse width is shorter than a clock period. SOLUTION: In the flip-flop circuit of this invention, a PMOS transistor (TR) P2 only controlled by an output result Q of a flip-flop latches an output node X1 of a dynamic circuit in an input section employing the dynamic circuit and a control signal generating circuit controlling an output data shut-off TR N2 is replaced with simple inverting delay circuits INV3-INV5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a flip-flop circuit used in a synchronous logic circuit.

[0002]

2. Description of the Related Art In a logic circuit, data is retained.
A flip-flop circuit that captures and holds data in synchronization with the edge of a clock signal is used. Recently, as a configuration example of a flip-flop circuit, a latch circuit that captures data using a strobe signal having a pulse width shorter than a clock cycle has been proposed. A conventional example of a flip-flop circuit constituted by a pulse latch will be described below.

FIG. 10 shows a configuration example of a conventional CMOS flip-flop circuit (US Pat. No. 5,917,355).
N5, PMOS transistors P1 to P2, inverter circuits INV1 to IN
V6, including NAND circuit NAND1, input data D, input control signal
This is a circuit that inputs CK and outputs output data Q. INV1
~ INV2 is for delaying the CK signal, and INV3 ~
INV4 is a circuit for holding the value of node X1, INV5 to INV6
Is a circuit for holding the value of Q.

In FIG. 10, when CK is at L level, P
The node X1 is charged to the H level by the MOS transistor P1. At this time, the NMOS transistor N4 and the PMOS transistor
Since P2 is cut off, Q maintains the previous value due to INV5-INV6. Subsequently, when CK transitions to the H level, the node CKD does not immediately transition to the H level, but transitions to the H level with a delay of a delay time generated by INV1 to INV2. CK
Is high level and CKD is low level (hereinafter referred to as an evaluation period), since the NMOS transistor N1 is turned on, if D is high level during this period, X1 is discharged and P2 causes Q
Changes to the H level. X if D is L level during evaluation period
1 remains at the H level, and the NMOS transistors N4 to N5 cause Q to transition to the L level. Then CK is at H level and CKD
Transitions to the H level state (hereinafter referred to as the holding period). At this time, if X1 is at the H level, N1 is cut off by NAND1 and is not affected by D, so that INV3 to INV4 are not affected.
As a result, X1 maintains the H level. When X1 enters the holding period at the L level, X1 is maintained at the L level by INV3 to INV4 regardless of the value of D because P1 is cut off.

In FIG. 10, P1, N1 to N3, INV1 to INV
4. NAND1 is an input section (dynamic circuit) that evaluates the input data signal and captures and holds the result, P2, N4 to N
5. It can be considered that INV5 to INV6 are output units (static circuits) that output and hold data in response to the output result of the input unit. Further, in the input section, N2 evaluates the input data signal, and the input data signal evaluation circuit N1, INV1 ~
INV2 and NAND1 can be regarded as output data shut-off circuits that control the result output of the input data signal evaluation circuit (output to X1 only during the evaluation period). During the period when CK is at the L level, the input section is precharged to the H level by the precharge PMOS transistor P1, and the output section is set to INV5.
ININV6 holds the value of the previous output result Q. During the period in which CK is at H level and CKD is at L level (evaluation period), both N1 and N3 are in the ON state and the output data is not shut off. The circuit N2 is turned on and X1 is discharged by N1 to N3. If D is at L level, X1 remains at H level because the input data signal evaluation circuit N2 is cut off. During the evaluation period, since N4 is in the ON state, P2 and N5 form an inverter circuit, and the inverted value of the value of X1 is Q.
Output to During the period when CK is at the H level and CKD is at the H level (holding period), the input section is connected to the inverter circuits INV3 to INV3.
The value of X1 is held by V4, and the output unit outputs an inverted value of X1 continuously from the evaluation period. That is, the input unit evaluates the input data signal D only during the evaluation period, outputs the evaluation result X1 to the output unit, performs the holding operation of the output node X1 during the holding period, and pre-charges X1 during the period when CK is L. This constitutes a dynamic circuit for charging. On the other hand, the output section operates as an inverter circuit while CK is at the H level and outputs the inverted value of the input X1 to Q. This constitutes a static circuit that performs the holding operation of Q. The evaluation period is a period during which CK is at the H level and CKD is at the L level, and is equal to the delay time generated when the CK signal passes through INV1 to INV2 and NAND1.

[0006]

In the case of the example shown in FIG. 10, there is a problem that the circuit scale (area) becomes large because the number of transistors constituting the flip-flop circuit is large.
Use the NAND circuit NAND1 with a large number of transistors for the control signal to cut off N1 during the holding period, or use the node X1
Inverter circuits INV3 to INV4
This is because they use. Assuming that the NAND circuit NAND1 has four transistors and the inverters INV1 to INV6 each have two transistors, the total number of transistors of the flip-flop circuit in FIG. 10 is 23.

It is therefore an object of the present invention to provide a flip-flop circuit having a small circuit scale by reducing the number of transistors constituting the flip-flop circuit.

[0008]

According to a first aspect of the present invention, a flip-flop circuit includes at least one input data signal terminal, a first input control signal terminal, an output data signal terminal, and an input data signal terminal. An input data signal to be input, a first input control signal to be input to a first input control signal terminal, and a second input control signal obtained by logically inverting the first input control signal and delaying it by a predetermined delay value And an output unit for receiving a first output signal, outputting a first output signal, a first input control signal and a second input control signal, and outputting an output data signal to an output data signal terminal. In the first stage, the value of the first input control signal is L level,
In the second stage, the values of the first input control signal and the second input control signal are both at the H level, and in the third stage, the value of the first input control signal is at the H level and the value of the second input control signal is at the H level. Value is L
An input data signal evaluation circuit for outputting a result depending on the value of the input data signal, and an output result of the input data signal evaluation circuit, the input unit being provided only in a second stage. A first output data shut-off circuit for performing an output, outputting a predetermined value independent of an input data signal in a first stage, outputting an output result of the input data signal evaluation circuit in a second stage, The output unit outputs a value dependent on the output data signal in three stages, and the output unit includes a second output data shut-off circuit that receives the first output signal and outputs only in the second stage. In the first stage and the third stage, the contents of the output data signal are maintained, and in the second stage, a value depending on the first output signal is output.

According to the flip-flop circuit of the first aspect, the output node of the dynamic circuit is held by one PMOS transistor controlled by the output result of the flip-flop in the input section using the dynamic circuit, and the output data is output. The number of transistors can be reduced by replacing the control signal generation circuit for controlling the shut-off circuit with a simple delay circuit. By reducing the number of elements, a flip-flop circuit having a small circuit scale can be obtained.

The flip-flop circuit according to claim 2 is
At least one or more input data signal terminals, a first input control signal terminal, an output data signal terminal, an input data signal input to the input data signal terminal, and a second input control signal signal input to the first input control signal terminal. A first input control signal, an input section for inputting a second input control signal obtained by logically inverting the first input control signal and delaying the input control signal by a predetermined delay value, and outputting a first output signal; An output section for inputting a signal and a first input control signal and outputting an output data signal to an output data signal terminal; in a first stage, the value of the first input control signal is L
Level, and in the second stage, the first input control signal and the second
A flip-flop circuit in which the values of the input control signals are both at the H level, and in the third stage, the value of the first input control signal is at the H level and the value of the second input control signal is at the L level, The input unit includes an input data signal evaluation circuit that outputs a result depending on the value of the input data signal, and a first output data shut-off that receives an output result of the input data signal evaluation circuit and outputs the result only in a second stage. Having a circuit, the first
In the stage, a predetermined value independent of the input data signal is output, in the second stage, the output result of the input data signal evaluation circuit is output, and in the third stage, a value dependent on the output data signal is output. The unit maintains the content of the output data signal in the first stage and the first and second stages in the second and third stages.
And outputs a value depending on the output signal of

According to the flip-flop circuit of the second aspect, the same effect as that of the first aspect is obtained.

The flip-flop circuit according to claim 3 is
At least one or more input data signal terminals, a first input control signal terminal, an output data signal terminal, an input data signal input to the input data signal terminal, and a second input control signal signal input to the first input control signal terminal. A first input control signal, an input section for inputting a second input control signal obtained by logically inverting the first input control signal and delaying the input control signal by a predetermined delay value, and outputting a first output signal; A first input control signal and a second input control signal, and an output unit for outputting an output data signal to an output data signal terminal. In the first stage, the value of the first input control signal is L level. Yes, the second stage is the first
Are both at the H level, and at the third stage, the value of the first input control signal is at the H level and the value of the second input control signal is at the L level. An input data signal evaluation circuit that outputs a result depending on a value of an input data signal, and an input unit that receives an output result of the input data signal evaluation circuit and outputs only in a second stage A first output data shut-off circuit for outputting a predetermined value independent of the input data signal in the first stage, outputting the output result of the input data signal evaluation circuit in the second stage, and outputting the output result of the input data signal evaluation circuit in the third stage; And outputting a value dependent on the second input control signal.
A second output signal is input and output is performed only in the second stage.
Characterized in that the output data shut-off circuit is maintained in the first and third stages, and outputs a value dependent on the first output signal in the second stage. It is.

According to the flip-flop circuit of the third aspect, the same effect as that of the first aspect is obtained.

According to a fourth aspect of the present invention, there is provided a flip-flop circuit comprising:
An input data signal terminal, a first input control signal terminal, an output data signal terminal, an input data signal of the input data signal terminal, a first input control signal of the first input control signal terminal, and a first input control An input unit for receiving a third input control signal, which is an inverted signal of the signal, and outputting a first output signal and a second output signal; a first output signal, a second output signal, and a first output signal;
And a fourth input control signal which is an inverted signal of the second input control signal and a second input control signal having only a phase different from that of the second input control signal, and outputs an output data signal. In the stage, the value of the first input control signal is L level, in the second stage, the values of both the first input control signal and the second input control signal are H level, and in the third stage, the first input control signal is at the L level. A flip-flop circuit in which the value of the control signal is H level and the value of the second input control signal is L level,
The input unit has an input data signal evaluation circuit for outputting a result depending on a value of the input data signal, and in a first stage, a predetermined value independent of the input data signal is supplied to the first output signal and the second output signal. And outputs the output result of the input data signal evaluation circuit as a first output signal and a second output signal in the second and third stages, and the output section outputs the first output signal and the second output signal. An output data shut-off circuit for receiving an output signal of the second input signal and outputting a value dependent on the first output signal and the second output signal only during a period when the second input control signal is H; Input control signal
In the period of L, the content of the output data signal is maintained.

According to the flip-flop circuit of the fourth aspect, the same effect as that of the first aspect is obtained.

The flip-flop circuit according to claim 5 is
A first PMOS having an input and an output, wherein the input has a source connected to the first power supply, a drain connected to the first node, and a gate connected to the first input control signal terminal; A transistor, a second PMOS transistor having a source connected to the first power supply, a drain connected to the first node, a gate connected to the output data signal terminal, and a source connected to the second node; A first NM having a drain connected to the first node and a gate connected to the input data signal terminal;
An OS transistor, a source connected to a third node, a drain connected to a second node, and a gate logically inverting the signal of the first input control signal terminal and delaying the signal by a predetermined delay value. 2 connected to the terminal of the second input control signal.
And a third NMOS transistor having a source connected to the second power supply, a drain connected to the third node, a gate connected to the first input control signal terminal, and an output unit. , The source is connected to the first power supply, the drain is connected to the output data signal terminal, and the gate is connected to the first power supply.
And a fourth PMOS transistor having a source connected to the fourth node, a drain connected to the output data signal terminal, and a gate connected to the first node.
An NMOS transistor and a source connected to the fourth node,
A fifth NMOS transistor having a drain connected to the second node and a gate connected to the fourth node, a first inverter receiving an output data signal terminal signal and outputting an inverted signal, It has a second inverter which inputs an output signal of the inverter and feeds back an inverted signal output to an input of the first inverter.

According to the flip-flop circuit of the fifth aspect, the same effect as that of the first aspect is obtained.

The flip-flop circuit according to claim 6 is
A first PMOS having an input and an output, wherein the input has a source connected to the first power supply, a drain connected to the first node, and a gate connected to the first input control signal terminal; A transistor, a second PMOS transistor having a source connected to the first power supply, a drain connected to the first node, a gate connected to the output data signal terminal, and a source connected to the second node; A first NMOS connected to a second input control signal terminal of a circuit having a drain connected to the first node and a gate logically inverting the signal of the first input control terminal and delaying the signal by a predetermined delay value; A second transistor having a transistor connected to the source at the third node, a drain connected to the second node, and a gate connected to the input data signal terminal;
An OS transistor, a third NMOS transistor having a source connected to the second power supply, a drain connected to the third node, and a gate connected to the first input control signal terminal; A third PMOS transistor having a source connected to the first power supply, a drain connected to the output data signal terminal, a gate connected to the first node, a source connected to the fourth node, and a drain connected to the output node; A fourth NMOS connected to the data signal terminal and having a gate connected to the first node
A fifth NMOS transistor having a transistor connected to a second power supply at a source, a drain connected to a fourth node, and a gate connected to a first input control signal terminal; It has a first inverter that outputs a signal, and a second inverter that inputs an output signal of the first inverter and feeds an inverted signal that is output back to an input of the first inverter.

According to the flip-flop circuit of the sixth aspect, the same effect as that of the first aspect is obtained.

The flip-flop circuit according to claim 7 is
A first PMOS having an input and an output, wherein the input has a source connected to the first power supply, a drain connected to the first node, and a gate connected to the first input control signal terminal; A transistor and a second source are connected to the first power supply, the drain is connected to the first node, and the gate is logically inverted from the signal at the first input control terminal and delayed by a predetermined delay value. A second PMOS transistor connected to the input control signal terminal; a first NMOS transistor having a source connected to the second node, a drain connected to the first node, and a gate connected to the input data signal terminal A transistor having a source connected to the third node, a drain connected to the second node, and a gate connected to the second input control signal terminal;
And a third NMOS transistor having a source connected to the second power supply, a drain connected to the third node, a gate connected to the first input control signal terminal, and an output unit. , The source is connected to the first power supply, the drain is connected to the output data signal terminal, and the gate is connected to the first power supply.
And a fourth PMOS transistor having a source connected to the fourth node, a drain connected to the output data signal terminal, and a gate connected to the first node.
An NMOS transistor and a source connected to the fifth node,
A fifth NMOS transistor having a drain connected to the fourth node and a gate connected to the second input control signal terminal;
A sixth NMOS transistor having a source connected to the second power supply, a drain connected to the fifth node, and a gate connected to the first input control signal terminal; inputting an output data signal and outputting an inverted signal; And a second inverter that inputs an output signal of the first inverter and feeds back an inverted signal output from the first inverter to an input of the first inverter.

According to the flip-flop circuit of the seventh aspect, the same effect as that of the first aspect is obtained.

The flip-flop circuit according to claim 8 is
A first unit having an input unit and an output unit, wherein the input unit has a source connected to the input data signal terminal, a drain connected to the first node, and a gate connected to the first input control signal terminal.
The NMOS transistor has a source connected to the input data signal terminal, a drain connected to the second node, and a gate connected to the third input control signal terminal which is an inverted signal of the signal of the first input control signal terminal. A first PMOS transistor, a source connected to a first power supply, a drain connected to a first node, a gate connected to a first input control signal terminal, and a source. Is connected to a second power supply, a drain is connected to a second node, a gate is connected to a third input control signal terminal, a second NMOS transistor is provided, and an output section has a source connected to the first node. A second input terminal connected to a power supply, a drain connected to the third node, and a gate connected to the second node having a phase different from that of the signal of the first input control signal terminal only.
A third PMOS transistor connected to a fourth input control signal terminal which is an inverted signal of the input control signal, a source connected to the third node, a drain connected to the output data signal terminal, and a gate connected to the Fourth PMOS connected to one node
A third NMOS transistor having a transistor and a source connected to the fourth node, a drain connected to the output data signal terminal, a gate connected to the second node, and a source connected to the second power supply; A fourth NMOS transistor having a drain connected to the fourth node and a gate connected to the terminal of the second input control signal, a first inverter receiving an output data signal and outputting an inverted signal, And a second inverter for inputting the output signal of the inverter and outputting the inverted signal to the input of the first inverter.

According to the flip-flop circuit of the eighth aspect, the same effect as that of the first aspect is obtained.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a flip-flop circuit according to the first embodiment of the present invention. In FIG. 1, N1 to N5 are NMOS transistors, P1 to P3 are PMOS transistors, INV1 to INV5 are inverter circuits, and input data D is input to an input data signal terminal, and an input control signal CK is input to a first input control signal terminal. To output the output data Q to the output data signal terminal. INV1 and INV2 are circuits for holding the value of Q. INV3 to INV5 are for inverting the logic of CK and generating a second input control signal CKDB whose timing is further delayed by a predetermined delay value. FIG. 2 is a time chart showing the operation of the flip-flop circuit of FIG.

Next, the operation of the flip-flop circuit of FIG. 1 will be described with reference to FIG. In FIG. 1, CK is L
During the level period (corresponding to Φ1 in FIG. 2), the node X1 serving as the first output signal is charged to the H level by the PMOS transistor P1. At this time, since the NMOS transistor N3 and the PMOS transistor P3 are cut off, Q maintains the previous value by INV1 to INV2. Then CK is at H level and CKDB
Is high level (corresponding to Φ2 in FIG. 2), the NMOS transistors N2 to N3 are turned on. If D is high level during this period, X1 is discharged and transits to low level, and P3 sets Q
Changes to the H level. If D is at L level during the period of Φ2, X1 remains at H level and the NMOS transistors N2 to N5
Are all turned on and Q changes to the L level. continue
CKDB transitions to L level while CK remains at H level (Φ in FIG. 2).
However, if X1 is at the H level at this time, Q holds the value of the L level, so that P1 keeps the X1 at the H level. When X1 is at the L level during the period of Φ3, Q holds the value of the H level, so that P1 to P2 and N2 to N3 are cut off, and X1 maintains the L level. N5 also has a rectifying effect, and suppresses the fluctuation of X1 due to the change of D during the period Φ3.

The features of the present invention are as follows. In FIG. 1, P1 to P2, N1 to N3, and INV3 to INV5 are input units for evaluating an input data signal and taking in and holding a result.
N4, N5, INV1, and INV2 can be regarded as output units that receive and output data from the input unit and output and hold data. Further, in the input section, N1 is an input data signal evaluation circuit that evaluates an input data signal, and N2 to N3 and INV3 to INV5 control the result output of the input data signal evaluation circuit (only during the Φ2 period).
It can be regarded as an output data shut-off circuit that performs output to X1). The output data shut-off circuit is also included in the output section, and is common to the output data shut-off circuit of the input section. As a first stage, during the period when CK is at the L level (corresponding to Φ1 in FIG. 2), the input unit is precharged to the H level by the precharge PMOS transistor P1, and the output unit is set to the previous level by INV1 to INV2. Holds the value of output result Q. In the second stage, during the period when CK is at the H level and CKDB is at the H level (corresponding to Φ2 in FIG. 2), since both N2 and N3 are in the ON state and the output data is not shut off, If D is at H level, the input data signal evaluation circuit N1 is turned on and X1 is discharged by N1 to N3.If D is at L level, X1 remains at H level because the input data signal evaluation circuit N1 is cut off. It is.
During the Φ2 period, since both N2 and N3 are turned on and the output data of the input data signal evaluation circuit is not shut off, P3 and N4 form an inverter circuit, and the inverted value of the value of X1 is calculated. Output to Q. As a third stage, during the period when CK is at the H level and CKDB is at the L level (corresponding to Φ3 in FIG. 2), the Q of the input section is at the L level (X1 is at the H level at this time).
Level), X1 is held at H level by P2, and Q is H
If the level (X1 is L level at this time), all paths (P1, P2, and N1 to N3) for outputting to X1 are cut off, so that X1 maintains L level. During the Φ3 period, N2 is cut off and the output data is shut off, so the output does not output the inverted value of X1 and the value before Q is INV.
1 to INV2. That is, the input unit evaluates the input data signal D only during the Φ2 period, outputs the evaluation result X1 to the output unit, performs the holding operation of the output node X1 during the Φ3 period, and precharges X1 during the Φ1 period. This constitutes a dynamic circuit. On the other hand, the output section operates as an inverter circuit only during the Φ2 period and outputs the inverted value of the input X1 to Q, and during the other periods, the data holding inverter circuit IN
A static circuit for holding the output data signal Q is constituted by V1 and INV2. The period Φ2 is a period in which both CK and CKDB are at the H level, and the CK signal is INV3 to INV.
Equal to the delay time caused by passing through 5. In the example of FIG. 10, the output data shut-off circuit is present at only one place on the input side, but in the present invention, it is present on both the input section and the output section, and two output shutdown circuits are provided by the rectifying NMOS transistor N5. The increase in the number of transistors is suppressed by sharing the OFF circuit and using the inverter circuit INV5 instead of the NAND circuit NAND1 for generating the data cutoff signal. In FIG. 10, INV3 to INV4 are connected to X1 and X1 can be held over the entire period. In the present invention, X1 needs to be held during the Φ3 period and when X1 is at the H level. Just take advantage of that, P
The only difference is that the MOS transistor P2 is connected for holding X1. Compared to the example of FIG. 10, in FIG.
Although a PMOS transistor P2, a rectifying NMOS transistor N5, and an inverter circuit INV5 are newly required, FIG.
Thus, the inverter pair for holding X1 and the NAND circuit for generating the data cutoff signal, which were required in the above, can be omitted. In FIG. 10, the NMOS transistors N3 and N5 are independent.
However, in FIG. 1, since the NMOS transistors N3 can be integrated into one, the number of transistors constituting the flip-flop circuit is reduced from 23 in FIG. 10 to 18 in FIG. 1, and the circuit scale is reduced. Also, compared to the example of FIG.
Since the number of transistors connected to CK is one less,
The load capacity of the K signal is reduced, and the power consumption of the part driving the control signal is reduced.

FIG. 3 is a configuration diagram of a flip-flop circuit according to the second embodiment of the present invention. In FIG. 3, N1 to N5 are NMOS transistors, P1 to P3 are PMOS transistors, and INV1 to INV5 are inverter circuits.
D, inputs the input control signal CK and outputs the output data Q.
INV1 and INV2 are circuits for holding the value of Q. INV3
.About.INV5 is for inverting the logic of CK and generating a signal CKDB whose timing is further delayed by a predetermined delay value. FIG. 4 is a time chart showing the operation of the flip-flop circuit of FIG.

Next, the operation of the flip-flop circuit shown in FIG. 3 will be described with reference to FIG. In FIG. 3, CK is L
During the level period (corresponding to Φ1 in FIG. 4), the node X1 is charged to the H level by the PMOS transistor P1. At this time NMO
Since the S transistor N5 and the PMOS transistor P3 are cut off, Q maintains the previous value by INV1 to INV2. Next, the period when CK is at H level and CKDB is at H level (Fig. 4
Since the NMOS transistors N1 and N3 are turned on during this period, if D is at H level during this period, X1 is discharged and transits to L level, and P3 transits to Q level.
If D is at the L level during the period of Φ2, X1 remains at the H level, and all the NMOS transistors N4 to N5 are turned on.
Q transitions to L level. Then CKDB while CK is at H level
Transitions to the L level (corresponding to Φ3 in FIG. 4).
If 1 is at the H level, Q holds the value at the L level, so that P1 keeps X1 at the H level. X1 in the period of Φ3
Is at the L level, Q holds the value of the H level, so that P1 to P2 and N1 are cut off, and X1 maintains the L level.

The features of the present invention are as follows. In FIG. 3, P1 to P2, N1 to N3, and INV3 to INV5 are input units for evaluating an input data signal and taking in and holding a result.
N4 to N5 and INV1 to INV2 can be regarded as output units that receive and output data from the input unit and output and hold data. In the input section, N2 is an input data signal evaluation circuit that evaluates an input data signal, and N1, N3, and INV3 to INV5 control the result output of the input data signal evaluation circuit (only during the Φ2 period).
It can be regarded as an output data shut-off circuit that performs output to X1). Unlike the example of FIG. 1, the output data shut-off circuit is not included in the output section.
During the period when CK is at the L level (corresponding to Φ1 in FIG. 4), the input section is connected to the node by the precharge PMOS transistor P1.
X1 is precharged to H level, and the output section is INV1 to INV2.
Holds the value of the previous output result Q. During the period when CK is at H level and CKDB is at H level (corresponding to Φ2 in FIG. 4), if D is at H level, since both N1 and N3 are on and the output data is not shut off, The input data signal evaluation circuit N2 is turned on and X1 is discharged by N1 to N3. If D is at L level, X1 remains at H level because the input data signal evaluation circuit N2 is cut off.
During the Φ2 period, the output section N5 turns on and the output data X1 of the input data signal evaluation circuit is not shut off, so that P3 and N4 form an inverter circuit, and the inverted value of the value of X1 is output to Q I do. CK is at H level and CKDB
Is L level (corresponding to Φ3 in FIG. 4), the input section is Q
Is L level (X1 is H level at this time).
Hold at H level, and if Q is at H level (X1 is L level at this time), all paths (P1, P2, and N1) that output to X1
~ N3) is cut off, so that X1 maintains the L level. The output unit in the Φ3 period outputs the inverted value of X1 to Q continuously from the Φ3 period. That is, the input unit evaluates the input data signal D only during the Φ2 period, outputs the evaluation result X1 to the output unit, and performs the holding operation of the output node X1 during the Φ3 period.
During the period of Φ1, a dynamic circuit for precharging X1 is formed. On the other hand, the output section operates as an inverter circuit only during the period when CK is at the H level and outputs the inverted value of the input X1 to Q. During the other periods, the output data signal Q is held by the data holding inverter circuits INV1 to INV2. This constitutes a static circuit to be performed. Φ2 period
During the period when CK and CKDB are both at H level, the CK signal
3 to the delay time generated by passing through INV5. Compared to the example of FIG. 10, although a PMOS transistor P2 for charging X1 and an inverter circuit INV5 are newly required in FIG. 3, an inverter pair for holding X1 and a NAND circuit for generating a data cutoff signal required in FIG. Can be omitted.
Therefore, the number of transistors constituting the flip-flop circuit is reduced from 23 in FIG. 10 to 18 in FIG. 3, and it can be seen that the circuit scale is reduced.

FIG. 5 is a configuration diagram of a flip-flop circuit according to the third embodiment of the present invention. In FIG. 5, N1 to N6 are NMOS transistors, P1 to P3 are PMOS transistors, and INV1 to INV5 are inverter circuits.
D, inputs the input control signal CK and outputs the output data Q.
INV1 and INV2 are circuits for holding the value of Q. INV3
.About.INV5 is for inverting the logic of CK and generating a signal CKDB whose timing is further delayed by a predetermined delay value. FIG. 6 is a time chart showing the operation of the flip-flop circuit of FIG.

Next, the operation of the flip-flop circuit of FIG. 5 will be described with reference to FIG. In FIG. 5, CK is L
During the level period (corresponding to φ1 in FIG. 6), the node X1 is charged to the H level by the PMOS transistor P1. At this time NMO
S transistors N3 and N6 are cut off and PMOS
Since transistors P2 and P3 are also cut off, Q becomes INV1
The previous value is maintained by ~ INV2. Subsequently, while CK is at the H level and CKDB is at the H level (corresponding to Φ2 in FIG. 6), the NMOS is used.
Since the transistors N2 to N3 and N5 to N6 are turned on, if D is at H level during this period, X1 is discharged and changes to L level, and Q changes to H level by P3. If D is at L level during Φ2, X1 remains at H level and N
All the MOS transistors N4 to N6 are turned on, and Q changes to the L level. Subsequently, when CKDB transitions to L level while CK remains at H level (corresponding to Φ3 in FIG. 6), X1 is charged by P2 and transitions to H level, and P3 and N5 are cut off. The previous value is maintained by INV1 and INV2.

The features of the present invention are as follows. In FIG. 5, P1 to P2, N1 to N3, and INV3 to INV5 are input units for evaluating an input data signal and capturing and holding a result.
N4 to N6 and INV1 to INV2 can be regarded as output units that receive and output data from the input unit and output and hold data. Further, in the input section, N1 is an input data signal evaluation circuit that evaluates an input data signal, and N2 to N3 and INV3 to INV5 control the result output of the input data signal evaluation circuit (only during the Φ2 period).
It can be regarded as an output data shut-off circuit that performs output to X1). The output data shut-off circuit is also included in the output section, but is independent of the output data shut-off circuit of the input section unlike the case of the example of FIG. CK
In the L level period (corresponding to Φ1 in FIG. 6), the input section is connected to the node X1 by the precharge PMOS transistor P1.
The output unit is precharged to the H level, and the output unit holds the value of the previous output result Q by INV1 to INV2. CK is H level and CK
During the period when DB is at the H level (corresponding to Φ2 in FIG. 6), the input section is N
Since both 2 and N3 are turned on and the output data is not shut off, if D is H level, the input data signal evaluation circuit N1 is turned on and X1 is discharged by N1 to N3, and if D is L level. Since the input data signal evaluation circuit N1 is cut off, X1 remains at the H level. In the output section during the Φ2 period, since both N5 and N6 are turned on and the output data X1 of the input data signal evaluation circuit is not shut off, P3 and N4 form an inverter circuit and the inverted value of the value of X1 Is output to Q. Also, during the period when CK is at the H level and CKDB is at the L level (corresponding to Φ3 in FIG. 6), unlike the case of the examples of FIGS.
Is fixed at the H level (it does not depend on the content of Q). Φ3
During the period, the output section does not output the inverted value of X1 because N5 is cut off and the output data is shut off.
Are held by INV1 and INV2. That is, the input unit evaluates the input data signal D only during the Φ2 period, outputs the evaluation result X1 to the output unit, performs the holding operation of the output node X1 during the Φ3 period, and precharges X1 during the Φ1 period. This constitutes a dynamic circuit. On the other hand, the output unit operates as an inverter circuit only during the Φ2 period and outputs the inverted value of the input X1 to Q, and during the other periods, a static circuit that holds the output data signal Q by the data holding inverter circuits INV1 to INV2. Will be configured. Φ2
The period is a period during which both CK and CKDB are at the H level, and is equal to the delay time generated when the CK signal passes through INV3 to INV5. Compared to the example of FIG. 10, in FIG.
Although a PMOS transistor P2, an NMOS transistor N5, and an inverter circuit INV5 are newly required, an inverter pair holding X1 and a NAND circuit for generating a data cutoff signal, which are required in FIG. 10, can be omitted. For this reason, the number of transistors constituting the flip-flop circuit is reduced from 23 in FIG. 10 to 19 in FIG. 5, and it can be seen that the circuit scale is reduced.

FIG. 7 is a configuration diagram of a flip-flop circuit according to the fourth embodiment of the present invention. In FIG. 7, N1 to N4 are NMOS transistors, P1 to P4 are PMOS transistors, INV1 to INV7 are inverter circuits, and input input data D of an input data signal terminal and input control signal CK of a first input control signal terminal. And output the output data QB. INV1
ININV2 is a circuit for holding the value of QB. INV3 ~ IN
V5 is for inverting the logic of the second input control signal having only a phase different from that of the first input control signal, that is, CK, and generating a signal CKDB whose timing is further delayed by a predetermined delay value. INV6 is a third input control signal which is an inverted signal of the first input control signal, that is, an inverted signal of CK,
V7 is a circuit for generating a fourth input control signal, which is an inverted signal of the second input control signal, that is, a reverse phase signal of CKDB. FIG. 8 is a time chart showing the operation of the flip-flop circuit of FIG.

Next, the operation of the flip-flop circuit shown in FIG. 7 will be described with reference to FIG. In FIG. 7, CK is L
During the level period (corresponding to Φ1 in FIG. 8), the node X1 which becomes the first output signal is charged to the H level by the PMOS transistor P2, and the node X2 which becomes the second output signal is the L level by the NMOS transistor N2. Is discharged. At this time the NMOS
Since transistor N3 and PMOS transistor P4 are cut off, QB maintains its previous value due to INV1-INV2. Subsequently, the period when CK is at the H level and CKDB is at the H level (see FIG. 8)
Since the NMOS transistor N1 and the PMOS transistor P1 are both in the ON state, if D is at the H level during this period, X2 transitions to the H level, and X1 maintains the H level. At this time, P4 is cut off, and both N3 and N4 are turned on, so that QB transitions to L level. If D is at L level during Φ2, X1 transitions to L level, X2 maintains L level, N3 is cut off, P3 and P4 are both on, and QB transitions to H level I do. Then C
When K changes to the H level and CKDB changes to the L level (corresponding to Φ3 in FIG. 8), P3 and N4 are cut off, so that QB maintains the previous value by INV1 to INV2.

The features of the present invention are as follows. In FIG. 7, P1 to P2, N1 to N2, and INV6 are input units for evaluating an input data signal and capturing and holding a result, and P3 to P4, N3.
N4, INV1 to INV5, and INV7 can be regarded as output units that receive and output data from the input unit and output and hold data. Further, in the input section, N1 and P1 can be regarded as an input data signal evaluation circuit for evaluating the input data signal. Unlike the examples of FIGS. 1, 3 and 5, the result output of the input data signal evaluation circuit is not limited to the Φ2 period,
While the CK is at the H level, the result of the input data signal evaluation circuit is continuously output. In the period when CK is at the L level (corresponding to Φ1 in FIG. 8), in the input section, the node X1 is precharged to the H level by P2, and the node X2 is predischarged by N2. During the period when CKDB is at the L level, the output parts are INV1 to IV
The value of the previous output result Q is held by NV2. During the period when CK is at the H level (corresponding to Φ2 and Φ3 in FIG. 8), the input section is connected to P2
And N2 are cut off, and the contents of D are output to X1 and X2 by input data signal evaluation circuits N1 and P1. During the period when CKDB is at the H level, both P3 and N4 are turned on, P4 and N3 form an inverter circuit, and receive the values of X1 and X2 to output the inverted value of D to QB I do. In other words, the input unit evaluates the input data signal D only during the period when CK is at the H level and outputs the evaluation results X1 and X2 to the output unit.When the CK is at the L level, precharge X1 and predischarge X2 Thus, a dynamic circuit is constructed. On the other hand, the output section operates as an inverter circuit only when CKDB is at the H level, and forms a static circuit that holds the output data signal QB by the data holding inverter circuits INV1 to INV2 while the CKDB is at the L level. Therefore, the input data D is evaluated only during the period Φ2 in FIG. 8 and the inverted value QB is output, and the value before the QB is held during the other periods. CK and CKDB during Φ2 period
Are both at the H level, which is equal to the delay time generated when the CK signal passes through INV3 to INV5. Compared to the example of FIG. 10, in FIG. 7, the X1 charging PMOS transistor P4
, X2 discharge NMOS transistor N2, data input PMOS
Although the transistor P1 and the inverter circuits INV5 to INV7 are newly required, the inverters INV3 and INV4 holding X1 required in the input unit in FIG. 10 and the NAND circuit required in the output data shutoff circuit can be omitted. Therefore, the number of transistors constituting the flip-flop circuit is
It can be seen that the circuit scale is reduced from 23 in FIG. 7 to 22 in FIG.

In the flip-flop circuits according to the first to third embodiments, even if the configuration of the input data signal evaluation circuit is not composed of one NMOS transistor as shown in FIGS. 1, 3 and 5, The present invention is effective. By using an evaluation circuit including a plurality of input data signals and a plurality of NMOS transistors, a flip-flop circuit with a logical operation function of the input data signal can be realized with a small number of transistors. FIG. 9A is a configuration example of an AND circuit of two input data signals A and B, and FIG.
Configuration example of OR circuit of two input data signals A and B, FIG.
(3) shows a configuration example of the two-input selection circuit (SA · A + SB · B). 9 (1) to 9 (3) are connected to N1 in FIG.
9 (1) by using N2 instead of N1) in FIG.
In the case of FIG. 9, a flip-flop circuit with an AND, in the case of FIG. 9 (2), a flip-flop circuit with an OR, and in FIG. 9 (3), a flip-flop circuit with a two-input selection circuit can be realized.

The transistor is not limited to the MOS type.

[0039]

According to the flip-flop circuit of the first aspect, in the input section using the dynamic circuit, the output node of the dynamic circuit is held by one PMOS transistor controlled by the output result of the flip-flop, and The number of transistors can be reduced by replacing the control signal generation circuit that controls the output data shut-off circuit with a simple delay circuit. By reducing the number of elements, a flip-flop circuit having a small circuit scale can be obtained.

According to the flip-flop circuit of the second aspect, the same effect as that of the first aspect is obtained.

According to the flip-flop circuit of the third aspect, the same effect as that of the first aspect is obtained.

According to the flip-flop circuit of the fourth aspect, the same effect as that of the first aspect is obtained.

According to the flip-flop circuit of the fifth aspect, the same effect as that of the first aspect is obtained.

According to the flip-flop circuit of the sixth aspect, the same effect as that of the first aspect is obtained.

According to the flip-flop circuit of the seventh aspect, the same effect as that of the first aspect is obtained.

According to the flip-flop circuit of the eighth aspect, the same effect as that of the first aspect is obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a flip-flop circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the flip-flop circuit of FIG. 1;

FIG. 3 is a configuration diagram of a flip-flop circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart illustrating an operation of the flip-flop circuit of FIG. 3;

FIG. 5 is a configuration diagram of a flip-flop circuit according to a third embodiment of the present invention.

FIG. 6 is a time chart illustrating an operation of the flip-flop circuit of FIG. 5;

FIG. 7 is a configuration diagram of a flip-flop circuit according to a fourth embodiment of the present invention.

FIG. 8 is a time chart illustrating an operation of the flip-flop circuit of FIG. 7;

9 is a configuration example of an input data evaluation circuit in the flip-flop circuit of FIG.

FIG. 10 is a configuration diagram of a conventional flip-flop circuit.

[Explanation of symbols]

 D, A, B, SA, SB input data signal CK input control signal Q, QB output data signal N1 to N6 NMOS transistor P1 to P4 PMOS transistor INV1 to INV7 Inverter circuit NAND1 NAND circuit VDD First power supply VSS Second power supply

Claims (8)

[Claims] At least one or more input data signal terminals, a first input control signal terminal, an output data signal terminal, an input data signal input to the input data signal terminal, and the first input control A first input control signal input to a signal terminal and an input for inputting a second input control signal obtained by logically inverting the first input control signal and delaying the first input control signal by a predetermined delay value to output a first output signal And an output unit that receives the first output signal, the first input control signal, and the second input control signal, and outputs the output data signal to the output data signal terminal. The value of the first input control signal is at L level, and the second
And the value of the second input control signal is H
A flip-flop circuit in which the value of the first input control signal is H level and the value of the second input control signal is L level in a third stage; An input data signal evaluation circuit that outputs a result depending on the value of the data signal; and a first output data shut-off circuit that receives an output result of the input data signal evaluation circuit and outputs the result only in the second stage. hand,
The first stage outputs a predetermined value independent of the input data signal, the second stage outputs an output result of the input data signal evaluation circuit, and the third stage outputs a value dependent on the output data signal. The output unit has a second output data shut-off circuit that receives the first output signal and outputs only at the second stage, and outputs the first output signal and the second output data. A flip-flop circuit comprising: maintaining the contents of the output data signal in three stages; and outputting a value dependent on the first output signal in the second stage. 2. An at least one input data signal terminal, a first input control signal terminal, an output data signal terminal, an input data signal input to the input data signal terminal, and the first input control A first input control signal input to a signal terminal and an input for inputting a second input control signal obtained by logically inverting the first input control signal and delaying the first input control signal by a predetermined delay value to output a first output signal And an output unit that inputs the first output signal and the first input control signal and outputs an output data signal to the output data signal terminal.
In the step, the value of the first input control signal is L level, in the second step, the values of the first input control signal and the second input control signal are both H level, and in the third step, When the value of the first input control signal is at the H level and the second
A flip-flop circuit in which the value of the input control signal is at the L level, wherein the input unit includes: an input data signal evaluation circuit that outputs a result depending on the value of the input data signal; and A first output data shut-off circuit for inputting an output result and outputting only in the second stage;
The first stage outputs a predetermined value independent of the input data signal, the second stage outputs an output result of the input data signal evaluation circuit, and the third stage outputs a value dependent on the output data signal. The output unit maintains the content of the output data signal in a first stage, and outputs a value dependent on the first output signal in the second stage and the third stage. A flip-flop circuit. 3. At least one or more input data signal terminals, a first input control signal terminal, an output data signal terminal, an input data signal input to the input data signal terminal, and the first input control A first input control signal input to a signal terminal and an input for inputting a second input control signal obtained by logically inverting the first input control signal and delaying the first input control signal by a predetermined delay value to output a first output signal And an output unit that receives the first output signal, the first input control signal, and the second input control signal, and outputs the output data signal to the output data signal terminal. The value of the first input control signal is at L level, and the second
And the value of the second input control signal is H
A flip-flop circuit in which the value of the first input control signal is H level and the value of the second input control signal is L level in a third stage; An input data signal evaluation circuit that outputs a result depending on the value of the data signal; and a first output data shut-off circuit that receives an output result of the input data signal evaluation circuit and outputs the result only in the second stage. hand,
The first stage outputs a predetermined value independent of the input data signal, the second stage outputs an output result of the input data signal evaluation circuit, and the third stage depends on the second input control signal. A second output data shut-off circuit for receiving the first output signal and outputting only at the second stage, wherein the output unit includes a first output signal and a second output data shut-off circuit. A flip-flop circuit for maintaining a content of the output data signal in a third stage and outputting a value dependent on the first output signal in a second stage. 4. An input data signal terminal, a first input control signal terminal, an output data signal terminal, an input data signal of the input data signal terminal, and a first input control of the first input control signal terminal. An input unit for inputting a signal and a third input control signal which is an inverted signal of the first input control signal, and outputting a first output signal and a second output signal; 2 is different from the first input control signal only in phase with the second input control signal and the second input control signal.
An output unit that inputs a fourth input control signal, which is an inverted signal of the input control signal, and outputs the output data signal. In the first stage, the value of the first input control signal is L level, In the second stage, the values of the first input control signal and the second input control signal are both at the H level, and in the third stage, the value of the first input control signal is at the H level and the second
Wherein the input unit has an input data signal evaluation circuit that outputs a result that depends on the value of the input data signal. A predetermined value that does not depend on the input data signal is output as the first output signal and the second output signal. In the second and third stages, the output result of the input data signal evaluation circuit is output by the first and second output signals. The output section receives the first output signal and the second output signal, and outputs the second input control signal during a period when the second input control signal is H. An output data shut-off circuit for outputting a value dependent on the first output signal and the second output signal only, and the content of the output data signal during a period when the second input control signal is L Maintain Flip-flop circuit according to claim Rukoto. 5. An input unit, comprising: an input unit, a source connected to a first power supply, a drain connected to a first node, and a gate connected to a first input control signal terminal. And a second PMOS transistor having a source connected to the first power supply, a drain connected to the first node, and a gate connected to the output data signal terminal.
A PMOS transistor and a source connected to the second node;
A first NMOS transistor having a drain connected to the first node and a gate connected to an input data signal terminal;
A second terminal of a circuit in which a source is connected to a third node, a drain is connected to the second node, and a gate logically inverts the signal of the first input control signal terminal and delays the signal by a predetermined delay value. A second NMOS transistor connected to a terminal of the input control signal, a source connected to the second power supply, a drain connected to the third node, and a gate connected to the first input control signal terminal A third NMOS transistor, wherein the output unit has a source connected to a first power supply, a drain connected to an output data signal terminal, and a gate connected to the first data source.
And a fourth NMOS transistor having a source connected to the fourth node, a drain connected to the output data signal terminal, and a gate connected to the first node. A fifth NMOS transistor having a source connected to the fourth node, a drain connected to the second node, and a gate connected to the fourth node, and a signal from the output data signal terminal. A first inverter for inputting and outputting an inverted signal; and a second inverter for inputting and outputting the output signal of the first inverter and feeding back the inverted signal output to the input of the first inverter. Flip-flop circuit. 6. An input unit, comprising: an input unit, a source connected to a first power supply, a drain connected to a first node, and a gate connected to a first input control signal terminal. And a second PMOS transistor having a source connected to the first power supply, a drain connected to the first node, and a gate connected to the output data signal terminal.
A PMOS transistor and a source connected to the second node;
A drain is connected to the first node, and a gate is connected to a second input control signal terminal of a circuit in which the signal of the first input control terminal is logically inverted and delayed by a predetermined delay value. A second NMOS transistor having a source connected to the third node, a drain connected to the second node, a gate connected to the input data signal terminal, and a source connected to the second power supply. A third NMOS transistor having a drain connected to the third node, a gate connected to the first input control signal terminal, and the output unit having a source connected to the first power supply. A third PMOS transistor having a drain connected to the output data signal terminal, a gate connected to the first node, a source connected to the fourth node, and a drain connected to the output data signal terminal Is A fourth NMOS transistor having a gate connected to the first node; a source connected to a second power supply; a drain connected to the fourth node; and a gate connected to the first input control signal terminal. Fifth connected
An NMOS transistor, a first inverter that inputs the output data signal and outputs an inverted signal, and a second that inputs the output signal of the first inverter and outputs the inverted signal to the input of the first inverter. A flip-flop circuit comprising: 7. An input unit, comprising: an input unit, a source connected to a first power supply, a drain connected to a first node, and a gate connected to a first input control signal terminal. A first PMOS transistor, a source connected to a first power supply, a drain connected to a first node, and a gate logically inverting the signal of the first input control terminal to delay by a predetermined delay value A second PMOS transistor connected to a second input control signal terminal of the circuit, a source connected to the second node, a drain connected to the first node, and a gate connected to the input data signal terminal. And a second NMOS transistor having a source connected to the third node, a drain connected to the second node, and a gate connected to the second input control signal terminal.
A third NMOS transistor having a transistor connected to a second power source, a drain connected to the third node, and a gate connected to the first input control signal terminal; A third PMOS transistor having a source connected to the first power supply, a drain connected to the output data signal terminal, a gate connected to the first node, a source connected to the fourth node, and a drain connected to the third node. Is connected to the output data signal terminal, and a fourth gate is connected to the first node.
An NMOS transistor and a source connected to the fifth node,
A fifth NMOS transistor having a drain connected to the fourth node, a gate connected to the second input control signal terminal, a source connected to a second power supply, and a drain connected to the fifth node; A sixth NMOS transistor having a gate connected to the first input control signal terminal, a first inverter receiving the output data signal and outputting an inverted signal, and an output signal of the first inverter. A flip-flop circuit comprising: a second inverter that inputs and outputs the inverted signal to an input of the first inverter. 8. An input unit, comprising: an input unit, an input unit, a source connected to an input data signal terminal, a drain connected to a first node, and a gate connected to a first input control signal terminal. A third NMOS transistor having a source connected to the input data signal terminal, a drain connected to the second node, and a gate connected to an inverted signal of the signal of the first input control signal terminal. A first PMOS transistor connected to the input control signal terminal; a first PMOS transistor having a source connected to the first power supply, a drain connected to the first node, and a gate connected to the first input control signal terminal; A second NMOS transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the third input control signal terminal.
A second transistor having a source connected to the first power supply, a drain connected to the third node, and a gate having a phase different from that of the signal of the first input control signal terminal only; A third PMOS transistor connected to the fourth input control signal terminal, which is an inverted signal of the input control signal of
, The drain is connected to the output data signal terminal, and the gate is connected to the first node.
An OS transistor, a third NMOS transistor having a source connected to the fourth node, a drain connected to the output data signal terminal, a gate connected to the second node, and a source connected to the second power supply A fourth NMOS transistor having a drain connected to the fourth node and a gate connected to a terminal of the second input control signal, and a first NMOS for receiving the output data signal and outputting an inverted signal. A flip-flop circuit comprising: an inverter; and a second inverter which receives an output signal of the first inverter and outputs an inverted signal to an input of the first inverter.