JPH06204813A - Field effect transistor logic circuit - Google Patents

Abstract

PURPOSE:To provide a D-type flip flop (FF) capable of reducing the influence of noise and preventing high spied performance from being lost even at the time of driving it at a low voltage. CONSTITUTION:A master latch 2 consisting of two-input NOR circuits 21, 22 for fetching data input D, the inverse of D, enhancement type FETs 25 to 28 and inverters 23, 24 mutually connecting their input and output terminals in order to maintain an output potential level and a slave latch 3 having similar constitution are cascade-connected and clock signals phi, the inverse of 4 having the relation of mutually inversed phases are applied to the two-input NOR circuits in respective latch circuits to constitute the D-type FF.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor logic circuit, and more particularly to a field effect transistor logic circuit which constitutes a D flip-flop which operates in synchronization with a clock.

[0002]

2. Description of the Related Art FIG. 2 shows a circuit of an 8 NOR circuit type flip-flop as a typical example of a conventional D type flip-flop used in a logic LSI. In this circuit, 4 2
A configuration is used in which a master latch 2 and a slave latch 3 which are input NOR circuits are used.

In this circuit, the input data D from the data input terminal 11 and the opposite phase data D (bar) from the data input terminal 12 (the bar is a substitute for the upper bar meaning inversion. The same applies hereinafter) are clock input. When the clock signal φ from the terminal 13 is at low level, it is taken into the master latch 2 and held at high level. The slave latch 3 takes in the data of the master latch 2 when the negative phase signal φ (bar) of the clock from the clock input terminal 14 is low level, and stores it when it is high level.

In the master latch 2, the output of the NOR circuit 41 which takes in the data D is the NOR circuit 43 of the next stage.
Entered in. The output of the NOR circuit 43 becomes the output of this latch and also the input of the NOR circuit 44. The output of the NOR circuit 42 that takes in the data D (bar) is input to the NOR circuit 44 of the next stage. NOR circuit 4
The output of 4 becomes the output of this latch, and N
It becomes an input to the OR circuit 43. That is, the NOR circuit 43 receives the outputs of both the NOR circuit 41 and the NOR circuit 44 as input, and the NOR circuit 44 receives the NOR circuit 42 and the NOR circuit 43.
Both outputs are input. NOR circuit 43 and NO
The R circuits 44 mutually use one output as the other input. The slave latch 3 including the NOR circuits 45, 46, 47 and 48 also operates in the same manner as the master latch 2,
The clocks input to the NOR circuits 41 and 42 of the master latch 2 and the NOR circuits 45 and 46 of the slave latch 3
A clock having a phase opposite to that of the clock input from the clock input terminal 14 is input. Data Q is output from the data output terminal 15 and data Q (bar) is output from the data output terminal 16 of the slave latch 3.

As another conventional D-type flip-flop, there is a circuit having the configuration shown in FIG. In this circuit,
Two transfer gates 51, 52, 61, 62 and 4
A configuration is used in which a master latch 2 and a slave latch 3 composed of individual inverters 53 to 56 and 63 to 66 are used. This circuit has a feature that it has a simple structure and operates at high speed. Inverters 55, 56, 65, 66 in the figure
Has a smaller load drive capability than the inverters 53, 54, 63, 64. This is because the driving capability of the circuit (not shown) in the preceding stage for supplying the input data is the inverter 55,
This is to prevent data contention when the driving capability of 56 is about the same. This is because, for example, when the output level of the circuit in the previous stage and the output level of the inverter are different, the input of the inverter 53 or the inverter 54 may be at an intermediate potential and the input data may not be latched.

In this circuit, the input data D and the opposite phase data D (bar) are taken into the master latch 2 when the clock signal φ is at the high level, and held when it is at the low level. The slave latch 3 takes in the data of the master latch 2 when the negative phase signal φ (bar) of the clock is at high level and holds it when it is at low level.

[0007]

In the D-type flip-flop shown in FIG. 2, data passes through the NOR circuit of three stages from entering the latch to exiting it, and as the flip-flop, NOR of six stages is used. It will be output through the circuit. Therefore, the operation speed of this flip-flop is reduced accordingly.

In the D-type flip-flop shown in FIG. 3, since the input impedance of the next stage seen from the transfer gate is high, the potential at the output end of the transfer gate easily fluctuates, and this output end and the clock input end. Due to the capacity of and, clock noise is likely to occur. Therefore, when driven at a low voltage, noise causes malfunction.

It is an object of the present invention to provide a field effect transistor logic circuit which is less affected by noise even when driven at a low voltage and in which high speed performance is not lost.

[0010]

A field effect transistor logic circuit according to the present invention comprises a first NOR circuit to which a first data signal and a clock signal are input, and a second data signal having a phase opposite to that of the data signal. And the clock signal is input second
First enhancement circuit having a NOR circuit, a drain electrode connected to a first power supply terminal, a gate electrode connected to the output of the first NOR circuit, and a source electrode connected to a first output terminal. Type FET and drain electrode are first
Of the second NOR connected to the output terminal of the gate electrode.
A second enhancement type FET having a circuit output connected to the source electrode connected to the second power supply terminal, a drain electrode connected to the first power supply terminal, and a gate electrode output of the second NOR circuit. Is connected and the source electrode is the second
Enhancement-type FE connected to the output terminal of the
T, a drain electrode connected to a second output terminal, a gate electrode connected to the output of the first NOR circuit, and a fourth enhancement type FET having a source electrode connected to a second power supply terminal, The input is connected to the first output terminal,
A first inverter circuit whose output is connected to the second output terminal, and a second inverter circuit whose input is connected to the second output terminal and whose output is connected to the first output terminal. There is.

Further, the D-type flip-flop of the present invention is
The field effect transistor logic circuits are connected in two stages in series, and clock signals having a phase opposite to each other are provided to each of them.

[0012]

The preferred embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
Referring to FIG. 1, this embodiment has a configuration in which a master latch 2 and a slave latch 3 are connected in series. The present embodiment differs from the conventional D-type flip-flop shown in FIGS. 2 and 3 in the configuration of each latch circuit.

In the master latch 2 of this embodiment,
The input of the 2-input NOR circuit 21 is the data input terminal 11
And a clock input terminal 13. 2-input N
The input of the OR circuit 22 is connected to the data input terminal 21 and the clock input terminal 13. Enhancement type F
The ET 25 has a drain electrode as a power supply terminal 71, a gate electrode as an output of the NOR circuit 21, and a source electrode as an output terminal 81.
Connected to. The enhancement type FET 26 has a drain electrode at the output end 81 and a gate electrode at the NOR circuit 2
The source electrode is connected to the power supply terminal 72 at the output of 2. The enhancement type FET 27 has a drain electrode connected to the power supply terminal 71, a gate electrode connected to the output of the NOR circuit 22, and a source electrode connected to the output end 82. The enhancement type FET 28 has a drain electrode at the output end 82.
In addition, the gate electrode is connected to the output of the NOR circuit 21, and the source electrode is connected to the power supply terminal 72. In addition, the inverter 23
Are connected with the output end 81 as an input and the output end 82 as an output. The inverter 24 is connected with the output end 82 as an input and the output end 81 as an output.

In this master latch 2, when a low-level signal φ is input to the clock input terminal 13, the data D applied to the data input terminal 11 is transferred to the NOR circuit 21.
The data D (bar) applied to the data input terminal 12
Are taken into the NOR circuit 22, respectively. Data D
Is low level (data D (bar) is high level), the enhancement type FETs 25 and 28 are turned on, the potential of the power supply terminal 71 is output to the output end 81, and the power supply terminal 72 is output to the output end 82. The electric potential is output. Also,
When the data D is high level (data D (bar) is low level), the enhancement type FETs 26 and 27 are turned on, the potential of the power supply terminal 72 is output to the output end 81, and the power supply terminal is output to the output end 82. The potential of 71 is output.
On the other hand, when a high level signal φ is input to the clock input terminal 13, both outputs of the NOR circuits 21 and 22 become low level, the potential levels of the output terminals 81 and 82 are maintained by the inverters 23 and 24, and the latch circuit Holds the previous data.

Also in the slave latch 3, N of two inputs is input.
OR circuits 31, 32 and enhancement type FET 35,
36, 37, 38 and the inverters 33, 34 are connected in the same manner as in the master latch 2 to form a latch circuit.

In this embodiment, a D-type flip-flop is constructed by using the master latch 2 and the slave latch 3 as described above. The output terminal 81 of the master latch 2 is connected as an input of the 2-input NOR circuit 31 of the slave latch 3, and the output terminal 82 is a 2-input NOR circuit of the slave latch 3.
Connected as input to circuit 32. The output terminal of the slave latch 3 is the output terminals 15 and 16 of the D-type flip-flop. 2 inputs N of master latch 2
A positive phase clock signal φ is input to the OR circuits 21 and 22, and a negative phase clock signal φ (bar) is input to the two-input NOR circuits 31 and 32 of the slave latch 3. It has been entered. That is, clock signals having opposite phases are input to the 2-input NOR circuit of the master latch 2 and the 2-input NOR circuit of the slave latch 3. The present embodiment operates as follows.

When the low-level clock signal φ is input to the clock input terminal 13, the data input terminal 1
Data D and D (bar) applied to 1 and 12 have 2 inputs N
The data is held by the inverters 23 and 24 maintaining the output levels taken in by the OR circuits 21 and 22 and determined by the enhancement type FETs 25, 26, 27 and 28. At this time, since the clock input signal φ (bar) is at the high level, the input data is not transmitted to the slave latch 3 in the next stage. Next, when the clock signal φ (bar) becomes low level, the output of the master latch 2 in the first stage is written in the slave latch 3 in the next stage. On the other hand, since the clock input signal φ is at the high level, the master latch 2 at the first stage holds the data so far.

In the conventional D-type flip-flop shown in FIG. 2, six NOR circuits are passed from the input of data to the output of the data, but in the present embodiment, the data is input and then output. Two NOR before being done
Since it only passes through the circuit and two enhancement type FETs, it has the advantage of operating at high speed. In addition, unlike the conventional D-type flip-flop shown in FIG. 3, since a transfer gate is not used for taking in data, it is difficult for noise to be included in the data signal, so that there is an advantage that the driving voltage can be lowered. As a result, the power consumption of the LSI can be reduced.

[0020]

As described above, in the field effect transistor logic circuit of the present invention, the noise due to the clock is less likely to occur by using the NOR circuit circuit for controlling the fetching of the data signal forming the latch circuit. Has become. In addition, since the number of gate stages through which the data signal passes is small, it operates at high speed.

As a result, according to the present invention, the driving voltage of the LSI can be set low while maintaining the high speed performance of the circuit. Therefore, the power consumption of the LSI can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of a conventional D-type flip-flop.

FIG. 3 is a circuit diagram of an example of a conventional D-type flip-flop.

[Explanation of symbols]

2 master latch 3 slave latch 11,12 data input terminal 13,14 clock input terminal 15,16 output terminal 21,22,31,32,41,42,43,44,4
5, 46, 47, 48 NOR circuit 23, 24, 33, 34, 53, 54, 55, 56, 6
3,64,65,66 Inverter 25,26,27,28,35,36,37,38 Enhancement type FET 51,52,61,62 Transfer gate 71,72 Power supply terminal 81,82 Output terminal

Claims (5)

[Claims] 1. A NOR circuit group for fetching first data and second data having a phase opposite to that of the first data in synchronization with a timing of a clock signal, and the NOR circuit group according to an output of the NOR circuit group. An enhancement-type FET group that outputs a potential corresponding to the first data and the second data, and an inverter circuit group that maintains the output of the enhancement-type FET group at the timing of the clock signal. Field effect transistor logic circuit. 2. A first NOR circuit to which a first data signal and a clock signal are input, and a second NOR circuit to which a second data signal and a clock signal having a phase opposite to that of the first data signal are input. A circuit, a drain electrode is connected to a first power supply terminal, a gate electrode is connected to the output of the first NOR circuit, and a source electrode is connected to a first output terminal; A drain electrode is connected to the first output terminal, a gate electrode is connected to the output of the second NOR circuit, and a source electrode is connected to a second power supply terminal. A third enhancement-type FET connected to the first power supply terminal, the gate electrode of which is connected to the output of the second NOR circuit, and the source electrode of which is connected to the second output terminal; Is connected to the second output terminal, the gate electrode is connected to the output of the first NOR circuit, and the source electrode is connected to the second power supply terminal. A first inverter circuit connected to the output terminal and having an output connected to the second output terminal; and a second inverter circuit having an input connected to the second output terminal and an output connected to the first output terminal And a field effect transistor logic circuit. 3. A first NOR circuit to which a first data signal and a clock signal are input, and a second NOR circuit to which a second data signal and a clock signal having a phase opposite to that of the first data signal are input. A first enhancement-type F circuit in which a drain electrode is connected to a first power supply terminal, a gate electrode is connected to the output of the first NOR circuit, and a source electrode is connected to a first contact.
A second enhancement type F in which ET and the drain electrode are connected to the first contact, the gate electrode is connected to the output of the second NOR circuit, and the source electrode is connected to the second power supply terminal.
ET and a drain electrode are connected to a first power supply terminal, a gate electrode is connected to an output of the second NOR circuit, and a source electrode is connected to a second contact.
A fourth enhancement type F in which ET and the drain electrode are connected to the second contact, the gate electrode is connected to the output of the first NOR circuit, and the source electrode is connected to the second power supply terminal.
ET, a first inverter circuit having an input connected to the first contact and an output connected to the second contact, and an input connected to the second contact and an output connected to the first contact A second inverter circuit, a third NOR circuit to which a signal from the first contact and a clock signal having a phase opposite to that of the clock signal are input, and a signal from the second contact and the clock signal are opposite to each other. A fourth NOR circuit to which a phase clock signal is input, a drain electrode connected to the first power supply terminal, a gate electrode connected to the output of the third NOR circuit, and a source electrode connected to the first output terminal And a drain electrode connected to the first output terminal, a gate electrode connected to the output of the fourth NOR circuit, and a source electrode connected to the second power supply terminal. 6th Enha And a drain electrode connected to the first power supply terminal, a gate electrode connected to the output of the fourth NOR circuit, and a source electrode connected to the second output terminal. An eighth enhancement type FET having a drain electrode connected to the second output terminal, a gate electrode connected to the output of the third NOR circuit, and a source electrode connected to the second power supply terminal; Is connected to the first output terminal, the output is connected to the second output terminal, and the third inverter circuit, the input is connected to the second output terminal, and the output is connected to the first output terminal A field-effect transistor logic circuit comprising: a fourth inverter circuit. 4. A D-type flip-flop, characterized in that the field-effect transistor logic circuits according to claim 1 are connected in two stages in tandem, and clock signals having mutually opposite phases are applied to them. 5. A D-type flip-flop, characterized in that the field-effect transistor logic circuits according to claim 2 are connected in two stages in tandem, and clock signals having mutually opposite phases are applied to each.