JPH05110392A - Integrated circuit provided with state latch circuit - Google Patents

Abstract

PURPOSE:To provide the integrated circuit provided with the hardware standby mode in which high speed operation is available and the circuit is in operation with a sufficiently small power consumption. CONSTITUTION:The integrated circuit is provided with a state latch circuit comprising a capacitor 108 and a switch 107, and the charge of the capacitor 108 is kept by interrupting the switch 107 with a control signal when a main power supply is failed. The state latch circuit has CMOS circuits 102-106 and a threshold voltage of the MOS transistor(TR) being a component of the switch 107 is set higher than a threshold voltage of the MOS TR of the CMOS circuit. Since the threshold voltage of the CMOS circuits 102-106 is set to a low voltage, the high speed circuit operation is attained. On the other hand, the threshold voltage of the MOS TR of the switch element 107 is set to a high voltage, resulting in decreasing the leak current and the state latch characteristic is improved and the power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit including a state holding circuit including a capacitor and a switch element, the state holding circuit including a CMOS circuit.

[0002]

2. Description of the Prior Art Regarding CMOS circuits, "Design of CMOS VLSI" published by Baifukan in 1989, edited by Takuo Sugano, edited by Tetsuya Iizuka, pp. 8 to 21, "Section 2.2 Characteristics of MOS Transistors". To "Section 2.5 Static type circuit and dynamic circuit".

Currently, highly integrated semiconductor logic ICs (integrated circuits) mainly use CMOS circuits and BiCMOS circuits. The BiCMOS circuit is a circuit that uses both a MOS transistor and a bipolar transistor, but a typical usage of the BiCMOS circuit is a CMOS.
This is a form in which a bipolar transistor is added as a buffer in order to enhance the load drive capability of the signal of the circuit. Less than,
Discuss CMOS circuits.

It has been well known that the characteristic of the CMOS circuit is low power consumption. The reason why the CMOS logic circuit is suitable for low power consumption operation will be described below by taking the CMOS inverter as an example.

FIG. 2A is a circuit diagram of a known CMOS inverter. The CMOS inverter circuit 201 has a P
It is composed of a channel type MOS transistor (hereinafter referred to as a PMOS transistor, or simply PMOS) 202 and an N channel type MOS transistor (hereinafter referred to as an NMOS transistor, or simply NMOS) 203.

The MOS transistor has a parameter called a threshold voltage. The threshold voltage is a voltage related to the boundary point between the operation in the ON state and the operation in the OFF state, and its value can be controlled by the semiconductor manufacturing process. Current MOS
In the transistor, PMOS202 and NMOS20
The standard threshold voltage _{Vth of 3} is 0.8V (volt). Reference numeral 211 is an input signal, and 212 is an output signal. The function of the inverter 201 is to output the logical negation of the input signal 211 to the output signal 212.

The operation of the PMOS is briefly shown. When the gate (G in the figure) terminal is at a high potential (hereinafter referred to as the potential H), the drain (D in the figure) and the source (S in the figure) terminals are connected. The gate terminal is in a substantially insulating state called an OFF state, and when the gate terminal has a low potential (hereinafter referred to as a potential L), the drain terminal and the source terminal are in a substantially conducting state called an ON state. Next, when the operation of the NMOS is briefly shown, when the gate is at the potential H, the drain and the source are in the ON state, and when the gate is at the potential L, the drain and the source are in the OFF state.

Further, both the PMOS and NMOS are in a sufficiently insulated state between the gate and the drain and between the gate and the source.

The threshold voltage of the PMOS is typical PM
In many cases, the sign is set to be negative in the OS, but in the present application, a sign opposite to the one described above is used, and a typical PMOS threshold voltage is used. This is because the discussion on the threshold value is common to the NMOS and the PMOS.

The CMOS inverter 201 is shown in FIG.
A gate is written as in (b).

FIG. 3 shows the relationship between the input signal potential of the CMOS inverter 201 and the current consumption of the inverter 201.
The current consumption is logarithmically displayed as a graph. However, as a condition, it is assumed that no load is connected to the output terminal 212 of the inverter 201. The power supply voltage is 2.5
It is V.

In FIG. 3, reference numeral 303 is a point equal to the NMOS threshold voltage 0.8V, and 304 is a point equal to 1.7V which is obtained by subtracting the PMOS threshold voltage 0.8V from the power supply voltage 2.5V. Left side of graph 303, 304
In the area on the right side of, the current consumption is low.

At point 301, the current consumption is 10 ^ (-11)
A little less than about A (ampere) (note that in the present application, x ^
Read y as "x to the power y"). The reason is NMOS 203
It is because the drain terminal and the source of are turned off. Similarly, at point 302, the current consumption is 10 ^ (-11) A.
The reason is that the reason is that the drain terminal and the source terminal of the PMOS 202 are in the OFF state, although the number is rather small.

In the CMOS logic circuit, most signals take either a complete potential H or a complete potential L except for the signal transition period, and CM during the signal value transition period.
The current consumption of the OS inverter is extremely small as shown in FIG. In addition, the property that the current consumption is extremely small except during the signal value transition period is not limited to the CMOS inverter and the N-value.
The same holds for multi-input logic circuits such as AND and NOR.

The above is the reason why the CMOS logic circuit is suitable for low power consumption operation.

Regarding the relationship between the delay time of the CMOS circuit and the threshold voltage V _th of the MOS transistor, pages 111 to 1 in the above-mentioned "Design of CMOS VLSI".
The explanation is given in the section "4.3 Delay time of CMOS circuit" on page 31. According to this, when the size of the MOS transistor, the power supply voltage Vcc, and the load capacitance C are kept constant, the signal transmission delay time per CMOS inverter stage is theoretically calculated and is inversely proportional to the square of (Vcc- _Vth ). It is said that. As a result, CMOS
In order to reduce the delay time of the circuit, it is better to reduce the threshold voltage V _th .

FIG. 4 shows an example of the structure of a conventional state holding circuit of a CMOS logic circuit. FIG. 4 is called a static latch. 401-404 are PMOS transistors and 405-408 are NMOS transistors. Circuit 41 formed by MOS transistors
Reference numerals 1 and 412 are called clocked inverters (hereinafter abbreviated as CIV). The circuit 409 is a CMOS inverter.

The operation of this latch is shown below. 423
Both (CKN) and 424 (CK) are clock control signals, which are controlled while being held in a logical inversion relationship. 42
When 3 (CKN) = potential L and 424 (CK) = potential H, the CIV 411 functions as an inverter for the data input signal 421 (IN), and the output of the CIV 412 is in a high impedance state. As a result, the data output signal 422 ( OUT) is equal to the logic level of 421 (IN).

423 (CKN) = potential H, 424
When (CK) = potential L, the output of the CIV411 is in a high impedance state, and the CIV412 outputs 422 (O
Since it works as an inverter of UT), CIV412
A positive feedback circuit is formed by the inverter 409 and holds a 1-bit state value permanently. The state corresponds to the potential of 422 (OUT) or the potential of the node 427.

The gate notation of CIV is shown in FIG.
The CIV 411 in FIG. 5A is represented by a gate as in FIG. 5B.

FIG. 6 shows another example of the configuration of a conventional state holding circuit of a CMOS logic circuit. FIG. 6 is called a dynamic latch. 601 is CIV, 602 is C
A MOS inverter, 603 is a capacitor. The capacitance of the capacitor 603 is, for example, 10 ^ (-14) F.
(Farad).

The operation of this latch is shown below. 613
(CKN) and 614 (CK) are both control signals,
It is controlled while maintaining a logical inversion relationship. 613 (CK
When N) = potential L and 614 (CK) = potential H, CI
Since the V601 acts as an inverter for the data input signal 611 (IN), as a result, the data output signal 612
(OUT) is equal to 611 (IN).

613 (CKN) = potential H, 614 (: C
When K) = potential L, the CIV 601 is in a high impedance state, and at that time, the output signal 612 (OU
T) outputs the negation of the potential value stored in the capacitor 603. That is, the magnitude of the electric charge accumulated in the capacitor 603 corresponds to the state value.

Since the electric charge accumulated in the capacitor is gradually discharged by the leak resistance, the state holding time is limited. For example, when the leak resistance is R = 10 ^ 11Ω (ohm), the capacitance of the capacitor is C as described above.
= 10 ^ (-14) F (Farad), and the state retention limit time t is approximately t = CR = 10 ^ (-3) seconds, that is, 1 millisecond. However, in most applications, the control signals 613 (CKN) and 614 (CK) are clock signals of a microcomputer or the like, and the required state holding time is not longer than 1 millisecond. For example, when the clock frequency is 10 MHz, it is sufficient to hold the state for half of one clock, that is, 5.0 × 10 ^ (− 8) seconds.

As another conventional technique, a method of operating with lower power consumption than during normal operation while maintaining the internal state of the logic integrated circuit is "Nikkei Microdevice" 199.
October 0, pp. 90-91. According to the above document, 16-bit MPU (Micro Processing U
It is stated that the lower limit of the operable clock frequency is lowered to 0 (that is, clock stop) by using a CMOS static circuit for (nit). The graph also shows the relationship between the operating clock frequency and the current consumption. Also, under the condition of power supply voltage = 3V, the current consumption at clock stop and at 8MHz (megahertz) operation is 5.0 x 10 ^ (-5) A, 3.5 x 10 ^ (-), respectively.
2) A, which is about 1/1000 of the latter.

Since the graph of the relationship between the operating clock frequency and the consumption current shown in the above-mentioned document is a continuous function, the 16-bit MPU operates at a very low clock frequency that can be read from the graph. Moreover, it can be inferred that the state in which the clock frequency reduction is recommended to the maximum is the clock stop. In that case, the 16-bit MP
It is considered that U keeps the internal state necessary for control even when its clock is stopped. The reason why the power consumption is low when the clock is stopped is considered to be the main reason that the current consumption of the CMOS circuit is low because no transition of the internal signal value occurs when the clock is stopped as described in FIG. Be done.

The operation mode in which the power consumption is reduced while keeping the internal state in this way is referred to as a hardware standby mode in the present application. Setting the clock frequency to zero or lowering it is an excellent way to realize the hardware standby mode. Further, since most of the current CMOS logic integrated circuits consume less power when the clock frequency is lowered below the standard value, all of them can be considered to potentially have the hardware standby mode referred to in the present application. ..

In the low power consumption operation using the hardware standby mode, software sets the internal state to LS.
Compared to the power reduction method that saves the internal hardware power after saving to the I external memory and restores the saved information when restarting, there is no need for state saving and recovery procedures, and there is an advantage that it can be realized simply. ..

[0029]

[Problems to be Solved by the Invention] The above-mentioned "prior art"
As described by taking the CMOS inverter as an example in the section of C,
The MOS circuit has a threshold voltage V _th of its MOS transistor.
The smaller the value, the faster the operation. However, it has been clarified by the study of the present inventors that lowering V _th causes another problem. This will be described below.

FIG. 7 shows a C using a MOS transistor having a threshold voltage V _th = 0.2 V lower than the current standard value.
The relationship between the potential of the input signal of the MOS inverter and the consumption current of the inverter is shown as a graph in which the consumption current is logarithmically displayed. However, as in the case of FIG. 3, it is assumed that no load is connected to the output terminal 212 of the inverter.
The power supply voltage is 2.5V.

In FIG. 7, 703 is a point equal to the NMOS threshold voltage of 0.2V, and 704 is a point equal to 2.3V obtained by subtracting the PMOS threshold voltage of 0.2V from the power supply voltage of 2.5V.

In FIG. 7, when the input signal is at the complete potential L or the potential H, the consumption current is 10 ^ from the points 701 and 702.
It can be seen that it is (-6) A. This current value is 10 ^ 5, that is, 100,000 times larger than 10 ^ (-11) A which is the value under the same conditions in FIG. The reason is V
_{This is because if th} is lowered, the degree of isolation in the OFF state of the NMOS at the input potential = 0 and the degree of isolation in the OFF state of the PMOS at the input potential = Vcc are weakened.

This fact indicates that the integrated circuit using the MOS transistor of FIG. 7 consumes power other than during the signal value transition period.
Compared with the case of using the MOS transistor of FIG. 5, 1
It is shown to be about 0 to 5 times larger.

In the above-mentioned "Nikkei Microdevice" example, C
In the MOS circuit, the current consumption is sufficiently small except during the signal transition period, which leads to reduction in power consumption in the hardware standby mode. However, even if an integrated circuit using a MOS transistor having a low threshold voltage is required from the demand for high-speed operation, the effect of reducing power consumption will be obtained if the hardware standby state described in the above-mentioned "Prior Art" is implemented. There is a problem that you can not get enough.

As described above, when the threshold voltage of the MOS transistor is lowered in order to improve the operation speed, the problem that the current consumption increases except the signal transition period becomes a remarkable problem especially when the power supply voltage is low.

In view of the above, an object of the present invention is to provide an integrated circuit having a hardware standby mode which can operate at high speed while operating with sufficiently small power consumption.

[0037]

According to a typical embodiment of the present invention for solving the above-mentioned problems, a state holding circuit comprising a capacitor and a switch element is provided, and when a main power supply is cut off, A semiconductor integrated circuit configured to hold an electric charge in the capacitor by cutting off the switch element by a control signal held at a predetermined potential, wherein the input or output of the state holding circuit and the switch element or It has a CMOS circuit connected between the capacitor and the capacitor, and the threshold voltage of the MOS transistor forming the switch element is set higher than the threshold voltage of the MOS transistor of the CMOS circuit. Characterize.

[0038]

Since the threshold voltage of the MOS transistor of the CMOS circuit of the state holding circuit is set to a low voltage, this CMOS circuit can operate at high speed. On the other hand, the threshold voltage of the MOS transistor forming the switch element is set to a high voltage, and the leak current is reduced, so that the state holding characteristic is improved and the power consumption can be further reduced.

Specific embodiments of the present invention will be described below.

That is, a capacitor is held at each state value to be held in the semiconductor integrated circuit, and is connected to the capacitor by a control signal set to a predetermined potential when the main power supply of the integrated circuit is cut off. Control the switch element. When the main power supply of the integrated circuit is cut off, the control signal is appropriately set to turn off the switch element.
It can be in the F state. At that time, the electric charge accumulated in the capacitor continues to be retained. The method of implementing the switch element is arbitrary, but in terms of high integration and certainty of operation, M
Using OS transistors is the preferred choice. In some cases, there may be a plurality of switch elements connected to the capacitor, and the electric charge may be held reliably only when all of them are turned off. Further, in some cases, when the switching elements are connected in series as seen in the connection method of the NMOS transistors of the CMOS NAND circuit, it is possible to reduce the charge by turning off one of the switching elements connected in series. In some cases, the holding is surely performed.

The above is unified and organized using the concept of a cut MOS set. Controlled by the control signal,
When it becomes possible to retain the charge of the capacitor by turning off some MOS transistors,
A set of S transistors is called a cut MOS set. This concept will be understood through the following examples.

Further, there are provided means for storing the state value of the circuit in the capacitor, and means for amplifying the value stored in each of the capacitors and rewriting the amplified value in the capacitor. In the preferred embodiment of the present invention, the cut MO
As the MOS belonging to the S set, a MOS transistor having a higher threshold voltage V _th than other MOS transistors is used.

In the integrated logic circuit using the present invention, the hardware standby mode for cutting off the main power supply is possible. In the hardware standby mode, the logic value is first held on the capacitor. Then cut MOS
The MOS transistors belonging to the set are turned off.
Then, the main power source of the integrated circuit is turned off. The value of the capacitor is less likely to leak because the cut MOS set is in the OFF state, and is held for a certain period of time. While the main power is off, the value is rewritten at a certain cycle. This operation is called refresh, and its cycle is called a refresh cycle. The refresh period is set sufficiently so that the state value to be held in the integrated circuit is not lost. During the refresh process, the value stored in each of the capacitors is amplified, and the amplified value is written again in the capacitor. Although power is consumed for each refresh cycle due to the refresh process, the refresh process is very short in the whole.

When this state holding circuit is used, the main power supply of the integrated circuit is cut off for most of the time, and the hardware standby operation for holding the state value can be performed. Therefore, as seen in the conventional logic integrated circuit, when the threshold voltage V _th of the MOS transistor is lowered to improve the operation speed, the effect of reducing the power consumption in the hardware standby mode becomes small. It can be effectively reduced by using it. In addition, only cut MOS is MOS
When the threshold voltage _{Vth of the} transistor is increased, the refresh cycle in the hardware standby mode can be lengthened.

[0045]

FIG. 1 shows an example of a state holding circuit according to an embodiment of the present invention. 101 is the entire state holding circuit. Circuit 1
01 has three CIVs 102, 103, 104, two inverters 105, 106, one NMOS transistor 107, and one capacitor 108.

The circuit 101 has nine terminals. 11
1 (IN) is a data input signal, 112 (OUT) is a data output signal, 113 (CK1N), 114 (CK
1) is a clock control signal of the CIV 102, which is controlled while being held in a logical inversion relationship. 115 (STR) is a control signal for state saving (store). 116 (RC
LN) and 117 (RCL) are control signals for state recovery (recall) and are controlled while being held in a logical inversion relationship. 118 (CK2N) and 119 (CK2) are CIV1
03 clock control signal, which is controlled while being held in a logically inverted relationship. The charge on capacitor 108 is node 1
21 (D2). The accumulation of electric charge in the capacitor 108 is controlled by the NMOS 107.

Throughout the present embodiment, MOSs not specified
The standard threshold voltage of the transistor is 0.2V. NM
OS107 has a threshold voltage of 0.
8V is used. A wavy line is shown in the NMOS 107 in the figure. This is not a general notation, but in the present application other N
It shows that V _th is higher than that of MOS. Standard threshold voltage 0.2V NMOS is CIV102, 103,
105, inverters 105, 106, etc. constitute a CMOS, and the threshold voltage of the PMOS of these CMOSs is also the standard threshold voltage of 0.2V.

CIV 104 is 116 (RCLN), 11
7 (RCL). Circuit 101 normally acts as a static latch. Then CI
The Vs 102 and 103 and the inverter 105 function. Normally, the state is stored by positive feedback of 103 and 105, and the state value is 112 (OUT) and node 12
It corresponds to the potential of 0 (D1).

In the standby mode, the node 12
The electric charge is accumulated in 1 and the state is held by the amount of electric charge.

The state is saved by setting the potential of 120 (D1) to NM.
This is achieved by notifying 121 (D2) via OS107. Further, the state recovery is achieved by transmitting the signal from 121 (D2) to 120 (D1) via the inverter 106 and the CIV 104. In addition, the refresh of the state is transmitted while being amplified from 121 (D2) to 120 (D1) via the inverter 106 and the CIV 104, and then 120.
The potential of (D1) is applied to the node 121 via the NMOS 107.
It is achieved by communicating to (D2).

All the power supplies of the circuit 101 are supplied from the main power supply.

The other detailed description will be described below by using the operation timing. In all timing diagrams below, the horizontal axis represents time and the right side represents the positive direction of time.

FIG. 8 shows the timing of the state saving operation of the circuit 101.

During the period of 801, the circuit 101 operates as a normal clocked static latch. 8
During the period 01, 113 (CK1N), 114 (CK1),
A clock is input to 118 (CK2N) and 119 (CK2). In addition, 115 (STR), 117 (RC
L) is kept at the potential L, and 116 (RCLN) is kept at the potential H. Therefore, the value of 120 (D1) is not transmitted to 121 (D2). The output of CIV 104 is in a high impedance state, and the value of 121 (D2) is 120 (D
Does not affect 1).

In the period of 802, the circuit 101 is performing the state saving operation. During 802, the control signals 113, 11
CI by setting 4, 118, 119, 116, 117
Only 103 of V102, 103 and 104 operates as an inverter, and the positive feedback of 103 and 105 holds the state value 120 (D1). First, the clocks 113, 114, 118 and 119 are stopped. Next, at time 804, 115 (STR) becomes the potential H, and at that time the NMOS 107 is turned on, so 120 (D)
The value of 1) is transmitted to 121 (D2) via the NMOS 107. The value 121 (D2) of the transmitted result is described as follows. When 120 (D1) is at the potential L, 121 (D2) is also at the potential L. When 120 (D1) is the potential H, 121 (D2) is the potential H from the potential H
The potential is obtained by subtracting Vth of 7. Then time 805
115 (STR) becomes potential L, and then NMOS
Since 107 is in the OFF state, holding of the value stored in 121 (D2) starts. At time 806, the main power is turned off. Signals 111-114, 116 after the main power is cut off
The value of -120 cannot be guaranteed. But 115 (ST
It is externally guaranteed that the value of R) is the potential L. As a result, the state value stored in 121 (D2) is held even in the period 803.

FIG. 9 shows the timing of the state refresh operation of the circuit 101. During the period 901, the main power supply is off. A period 902 is refresh processing. The power is turned on at time 904. During 902, control signal 11
Depending on the setting of 3, 114, 118, 119, 116, 117, only 104 of the CIVs 102, 103, 104 operates as an inverter, and the value held in 121 (D2) is 120 (D) via the inverter 106, CIV104.
Given in 1). The signal value on 121 (D2) is weakened due to leakage while the main power supply is cut off (to be precise, the potential slightly shifts from the value at the start of holding to the H side or the L side). , Inverter 106, CIV10
4 has a voltage amplifying action, and the value given to 120 (D1) is a perfect potential H or a perfect potential L.

Next, at time 905, 115 (STR) becomes the potential H, and at that time the NMOS 107 is turned on, so the value of 120 (D1) is 121 via the NMOS 107.
It is rewritten to (D2). Then at time 906, 11
5 (STR) becomes the potential L, at which time the NMOS 107
Becomes OFF, so that the value re-accumulated in 121 (D2) starts to be held. The main power is turned off at time 907, and the period 903 is a main power-off period similar to the period 803.

Refresh is achieved by the above procedure. Since the electric charge is rewritten to 121 (D2), the state value can be held indefinitely by performing refreshing at an appropriate cycle.

FIG. 10 shows the timing of the state recovery operation of the circuit 101.

During period 1001, the main power supply is off.

During the period 1002, the state recovery operation is performed. The power is turned on at time 1004. During 1002, the control signals 113, 114, 118, 119, 116, 11
1 of CIVs 102, 103, 104 depending on the setting of 7
Only 04 operates as an inverter, and the value held in 121 (D2) is given to 120 (D1) via the inverter 106 and the CIV 104. 118 at time 1005
(CK2N) = potential L, 119 (CK2) = potential H, 1
16 (RCLN) = potential H, 117 (RCL) = potential L
Switch to. At this point, the state value and the value of the control signal are also equal to those on the verge of time 804.

The period 1003 is in a normal state. The clock again enters the signals 113, 114, 118, and 119, and the logic circuit performs the operation subsequent to the period 801.

An example of another state holding circuit using the present invention is shown in FIG. Reference numeral 1101 is the entire state holding circuit. The circuit 1101 has two CIVs 1102, 1103, one inverter 1104, one NMOS 1105 transistor, and one capacitor 1106.

The circuit 1101 has seven external terminals. 1111 (IN) is a data input signal. 111
2 (OUT) is a data output signal. 1113 (CK
1N) and 1114 (CK1) are CIV1102 clock control signals, which are controlled while being held in a logically inverted relationship. Reference numeral 1115 (ST-RC) is a control signal for state saving and restoration. 1116 (CK2N), 1117
(CK2) is a CIV1103 clock control signal, which is controlled while being held in a logically inverted relationship.

The charge on capacitor 1106 is at node 112.
1 (D2). The accumulation of electric charge in the capacitor 1106 is controlled by the NMOS 1105. N
The threshold voltage of the MOS1105 is the other N in the circuit 1101.
Higher than the threshold voltage of MOS.

The capacitance of the capacitor 1106 has a capacitance value three times the sum of the capacitances of the element and wiring added to the node 1120 (D1).

All power supplies for the circuit 1101 are provided by the main power supply.

The state of the circuit 1101 is saved, refreshed,
The recovery method is similar to that of circuit 101, but there are some differences.

The first difference is that node 11 is used for state recovery.
21 (D2) via NMOS 1105 to node 112
It is achieved by transmitting to 0 (D1).

The second difference is the state refresh method. Refresh the state at node 1121 (D2)
Of the electric charge of 1 is transferred to 1120 (D1) via the NMOS 1105, and then the potential obtained by the action of the electric charge is set to 1
It is amplified by the feedback loop formed by 103 and 1104, and finally the potential of 1120 (D1) is NMOS.
This is achieved by communicating to 1121 (D2) via 1105.

Details of the operation of the circuit 1101 will be described below.

The procedure of the state saving operation of the circuit 1101 is the same as in FIG.

That is, the control signal 1113 (CK1N),
1114 (CK1), 1116 (CK2N), 1117
(CK2) is a signal 11 having the same name in FIG.
3 (CK1N), 114 (CK1), 118 (CK2
N) is controlled in exactly the same way that 119 (CK2) was controlled. Control signal 1115 (ST-RC)
Is controlled in the same manner as 115 (STR) was controlled in FIG. 1115 (ST-RC) is the potential H
Then, the electric charge is accumulated in 1121 (D2), and then 1
115 (ST-RC) becomes the potential L.

FIG. 12 shows the procedure of the state refresh operation of the circuit 1101.

In period 1201, the main power supply is off.

The refresh operation is performed in the period 1202. First, at time 1205, the main power is turned on. At this time, the CIVs 1102 and 1103 are all in a high impedance state due to the setting of the control signals 1113, 1114, 1116 and 1117. The potential of 1120 (D1) at this point has no particular meaning. 1115 at time 1206 (ST
-RC) becomes the potential H. Therefore, the NMOS 1105 is turned on and the charge accumulated in the 1121 (D2) becomes 1
The charge of 120 (D1) is in the charge sharing state. Since the capacitance of the capacitor 1106 is larger than the capacitance added to 1120 (D1), the potential close to the potential accumulated in 1121 (D2) is 1120 (D1), 1121 (D2).
Given to both.

At time 1207, 1116 (CK2N) becomes the potential L and 1117 (CK2) becomes the potential H. This allows the CIV1103 to act as an inverter, 110
3, 1104 forms a positive feedback.
This feedback mechanism amplifies the potential of 1120 (D1). That is, if 1120 (D1) is at weak potential H, it is pulled up to full potential H, and if it is at weak potential L, it is pulled down to full potential L. At the same time as this amplification operation, the amplified value is NMOS1.
It is transmitted to 1121 (D2) via 105.

At time 1208, the potential 1115 (ST-RC) becomes the potential L. NMOS 1105 is turned off and 1
Retention of the electric charge of 121 (D2) starts.

The procedure of the state recovery operation of the circuit 1101 will be described. As described in FIG. 12, 1121 (D2)
The value held in 1120 (D
1) can be transmitted. 1208 in FIG.
At the point of
It is clear from the similarities to the description given with reference to FIGS. 9 and 10 for the circuit 101 that the operation after the state is saved can be performed by applying it to the circuit 16 and 1117.

Through the above description, 1115 (ST-RC)
Is kept at the potential L during the main power-off with state maintenance.

FIG. 13 shows an example of still another state holding circuit using the present invention. 1301 is the entire state holding circuit. The circuit 1301 has two CIVs 1302, 1303,
One inverter 1304, four NMOS 1305,
It has 1307, 1308, 1309 and one capacitor 1306.

The gate widths of the NMOSs 1307 and 1308 are both 20 times the gate width of the NMOS 1309.

The circuit 1301 has seven external terminals. The external terminals are 1311 (IN), 1312 (OU
T), 1313 (CK1N), 1314 (CK1), 1
315 (ST-RC), 1316 (CK2N), 131
Although it is 7 (CK2), the meaning of the signal is the same as the signal having the same name of the seven external terminals in FIG.

The charge on capacitor 1306 is at node 132
1 (D2). The accumulation of electric charge in the capacitor 1306 is controlled by the NMOS 1305. N
The threshold voltage of the MOS 1305 is the other N in the circuit 1301.
Higher than the MOS threshold voltage.

The capacitance of the capacitor 1306 is one tenth of the total capacitance of the element and wiring added to the node 1320 (D1).

All power supplies for the circuit 1301 are supplied from the main power supply.

The state of the circuit 1301 is saved, refreshed,
The recovery procedure is the same as that of the circuit 1101 in FIG.

The difference between the circuit 1301 and the circuit 1101 is that 1321 (D
The potential accumulated in 2) is to be applied to 1320 (D1) via NMOSs 1307 and 1308.

The refresh operation timing of the state of the circuit 1301 is the same as that of the case of the circuit 1101. Therefore, description will be given using the control signal of FIG. 12 for the circuit 1101. The control signal can be read by replacing it with a signal of the same name. 1315 at time 1206 (S
T-RC) becomes the potential H. If the state value stored in the capacitor 1306 is the potential H, the NMOS 130
Both 7 and 1308 are turned on. NMOS 130
9 is also turned on. However, due to the relationship with the gate width of the NMOS described above, the NMOS 1307, 13
Since the current driving capability of the 08 path is about 10 times the current driving capability of the NMOS 1309, the potential H of 1320 (D1) is almost close to the power supply voltage Vcc.

If the state value stored in the capacitor 1306 is the potential L, at time 1206, the NMOS 13
Since the 08 is in the OFF state, the NMOSs 1307 and 13
The path driving 1320 (D1) to potential H via 08 does not work. The NMOS 1309 is turned on and 13
20 (D1) becomes the potential L.

Through the above description, 1315 (ST-RC)
Is kept at the potential L during the main power-off with state maintenance.

FIG. 14 shows an example of still another state holding circuit using the present invention. 1401 is the entire state holding circuit. The circuit 1401 has two CIVs 1412, 1413,
One inverter 1410 and one capacitor 1
411.

CIV1412 has two PMOSs 140
2, 1403 and two NMOSs 1406 and 1407. The CIV1413 has two PMOSs 1404,
1405 is composed of two NMOSs 1408 and 1409. Among them, PMOS 1403, 1405, NMOS1
The threshold voltages of 406 and 1408 are higher than those of other MOS transistors.

The circuit 1401 has six external terminals. The external terminals are 1421 (IN), 1422 (OU
T), 1423 (CK1N), 1424 (CK1), 1
425 (CK2N) and 1426 (CK2), the meaning of the signal is 11 of the external terminals in FIG.
The signals have the same names as those of the six signals except 15 (ST-RC), and thus the description thereof will be omitted.

The electric charge of the capacitor 1411 is the node 143.
1 (D1).

The state of the circuit 1401 is saved, refreshed,
The recovery method is similar to that of circuit 1101, but there are some differences.

The first difference is that the circuit 1401 is equivalent to the circuit 11
01 does not have a control signal for state saving and recovery, ie, 1115 (ST-RC).

The second difference is that the circuit 1401 uses the same node 1431 as the node holding the state value in the normal operation of the state holding circuit as the node holding the state value.

The third difference is that in the circuit 1401, 1423 is maintained while the main power supply is cut off while maintaining the state.
(CK1N), 1425 (CK2N) is at the potential H, 14
24 (CK1) and 1426 (CK2) are set to the potential L.

With this setting, the PMOS is turned off while the main power is off.
All of 1403 and 1405 and the NMOSs 1406 and 1408 are turned off, and the potential of the node 1431 is held. Otherwise, circuit 1401 is equivalent to circuit 11 of FIG.
This is the same as 01, and the other description is omitted.

According to the present invention, a control signal (abbreviated as a special control signal here) and a cut M that are kept at the potential H or the potential L even when the main power source of the capacitor and the integrated circuit is cut off.
Includes OS set. Correspondences between the examples described above will be shown.

In the circuit 101 shown in FIG. 1, the capacitor is 108, the special control signal is 115, and the cut MOS set is 107.

In the circuit 1101 shown in FIG. 11, the capacitor is 1106, the special control signal is 1115, and the cut MO.
The S set is 1105.

In the circuit 1301 shown in FIG. 13, the capacitor is 1306, the special control signal is 1315, and the cut MO.
The S set is 1305.

In the circuit 1401 shown in FIG. 14, the capacitor is 1411 and the special control signals are 1423 and 1424.
1425, 1426, 1403, 1 for cut MOS set
405, 1406, and 1408.

FIG. 15 shows a diagram of a logic system using the circuit 101. This system is a four-phase clock 1521 (T
1), 1522 (T2), 1523 (T3), 1524
Use (T4). Explaining the contents of the four-phase clock, a rectangular wave clock with a duty ratio of 50% is given to 1521 (T1), 1522 (T2), 1523 (T3), 1
At 524 (T4), 1521 (T1) is used as a reference, and in the direction of the time axis, 1/4 cycle, 2/4 cycle, and 4 cycle, respectively.
The clock is delayed by three cycles. 150
1, 1504 is a combinational logic such as a random logic. 1502, 1503, and 1505 are
It includes a plurality of static latches shown in FIG. 1506
Is a set of state holding circuits 101. The input signals of this system are 1511, 1512 and the output signals of this system are 1513, 1514. The control signal 1525 for the latch in 1502 is generated from 1521 (T1).
Similarly, the control signal 1526 of the latch in 1503 is 152
2 (T2). The control signal 1527 for the latch in 1504 is generated from 1523 (T3). 15
07, 1508, and 1509 are signals that are logically inverted with respect to the input clock, that is, 423 (CKN) in FIG.
It has a function of creating 424 (CK).

The control signal set 1528 of the state holding circuit 101 in 1506 includes the signals 113, 114, 115 and 11.
Equal to the set of 6, 117, 118, 119. 1510
1524 (T4), which is a standby signal 1529
(STBY), a state save control signal 1530 (ST
ORE) to create a control signal set 1524.

In this system, the power sources 1501-1509 are supplied from the main power source. The power of 1510 is supplied from the sub power supply.

The state is 15 while the main power is turned off with the state maintained.
It is held at 06. In the logic system of the form shown in FIG. 15, if the information is held at the timing of one place in one cycle of the clock, it can be restarted after the main power is turned on again.

[0110]

When the state holding circuit according to the present invention is used in an information processing apparatus such as a notebook type personal computer, the main power source of the integrated circuit is cut off for most of the time, and a backup auxiliary battery holds the state value. Wear standby operation can be performed.

As seen in the conventional logic integrated circuit, the threshold voltage V _{th of the} MOS transistor is increased in order to improve the operation speed.
By using the present invention, it is possible to effectively reduce the problem that the effect of reducing the power consumption in the hardware / standby mode becomes small when the value is lowered.

In addition, when the threshold voltage V _th of the MOS transistors is increased only in the cut MOS set, the refresh cycle in the hardware standby mode can be lengthened.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of a state holding circuit of the present invention.

FIG. 2 is a circuit diagram and gate notation of a known CMOS inverter.

FIG. 3 is a graph showing the relationship between the potential of the input signal of the CMOS inverter 201 and the consumption current.

FIG. 4 is a static latch which is an example of a conventional CMOS state holding circuit.

5 is a circuit diagram and a gate notation of a MOS transistor of the clocked inverter 411 of FIG.

FIG. 6 is a dynamic latch which is an example of a conventional CMOS state holding circuit.

FIG. 7 is a graph showing the relationship between the potential of the input signal of the CMOS inverter having a low threshold voltage and the consumption current.

8 is a timing chart of a state saving operation of the state holding circuit 101 of FIG.

9 is a timing diagram of a state refresh operation of the state holding circuit 101 of FIG.

10 is a timing chart of a state recovery operation of the state holding circuit 101 of FIG.

FIG. 11 is a circuit diagram of a second embodiment of the state holding circuit of the present invention.

12 is a timing diagram of a state refresh operation of the state holding circuit 1101 of FIG.

FIG. 13 is a circuit diagram of a third embodiment of the state holding circuit of the present invention.

FIG. 14 is a circuit diagram of a state holding circuit according to a fourth embodiment of the present invention.

FIG. 15 is a configuration diagram of a logic system using the state holding circuit of the present invention.

[Explanation of symbols]

101 ... State holding circuit, 102, 103, 104 ... Clocked inverter, 105, 106 ... Inverter, 10
7 ... High-threshold NMOS transistor, 108 ... Capacitor, 111 ... Data input signal, 112 ... Data output signal, 113, 114, 118, 119 ... Clock signal, 115 ... State save control signal, 116, 117 ... State recovery Control signal, 120, 121 ... Node

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Motonobu Tonomura 1-280 Higashi-Kengokubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Koichi Seki 1-280 Higashi-Kengokubo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory

Claims (2)

[Claims] 1. A state holding circuit comprising a capacitor and a switch element is provided, and an electric charge is held in the capacitor by shutting off the switch element by a control signal which is kept at a predetermined potential when the main power supply is cut off. A semiconductor integrated circuit configured to have a CMOS circuit connected between the input or output of the state holding circuit and the switch element or the capacitor and the capacitor, and the switch element is configured. The semiconductor integrated circuit is characterized in that the threshold voltage of the MOS transistor is set higher than the threshold voltage of the MOS transistor of the CMOS circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the CMOS circuit executes a refresh operation for amplifying a value stored in the capacitor and writing the value in the capacitor again.