JPH0738417A - Cmos semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the operating speed from being decreased when a low power supply voltage is adopted for the integrated circuit as its power supply voltage and to reduce the current consumption in the standby state. CONSTITUTION:Switches SW1, SW2 are turned on in the operating state and turned off in the standby state. An inverter capable of a high operation speed is arranged between power supply terminals VDD2 and VSS2 reaching the floating state in the standby state, and the inverter for latching a signal is arranged between power supply terminals VDD1 and VSS1 in the active state at all times. A p-channel MOS p11 and an nchannel MOS n11 are transistors(TRs) capable of a large current supply at a low threshold voltage and a p-channel MOS p12 and an n-channel MOS n12 are transistors capable of a small current supply at a high threshold voltage. Since the MOS p11, n11 are operated in the operating state, high circuit operation is attained. The MOS p11, n11 are disconnected from the power supply in the standby state and a sub threshold current of the MOS p12, n12 is small, then the current consumption in the standby state is decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS type semiconductor integrated circuit, and particularly suitable for operating under a low power supply voltage,
The present invention relates to a high speed and low power consumption CMOS type semiconductor integrated circuit.

[0002]

2. Description of the Related Art When a MOS transistor is miniaturized under a constant power supply voltage, an internal electric field is strengthened and hot electrons are rapidly generated, resulting in deterioration of transistor characteristics. In order to avoid this, a method of reducing the power supply voltage at the same time as miniaturization is generally adopted. However, when the power supply voltage is reduced, it is desirable to reduce the threshold voltage of the MOS transistor at the same rate. The switching time of the MOS transistor depends on (C _L × V _DD ) / {β × (V _DD − | V _T |) ² } [V _DD ... Power supply voltage, C _L ... Load capacitance, β ... Transistor structure and size. This is because, since it is proportional to the constant, V _T ... Threshold voltage], the smaller | V _T | is, the shorter the switching time is, and particularly when V _DD is lowered, this effect remarkably increases. However, lowering the threshold voltage increases power consumption when the semiconductor device is in the standby mode. This will be described below.

FIG. 6A is a circuit diagram of a CMOS inverter as a constituent element of a conventional semiconductor integrated circuit. This inverter has a source connected to a power supply terminal V _DD , a gate connected to an input terminal I, and a drain. A p-channel MOS transistor (hereinafter referred to as pMOS) p41 connected to the output terminal O, and an n-channel whose source is connected to the ground terminal V _SS , gate is connected to the input terminal I, and drain is connected to the output terminal O MOS transistor (hereinafter nMOS
Note) n41.

In this CMOS inverter, when the signal at the input terminal changes from the low level (the potential of the ground terminal V _SS ) to the high level (the potential of the power supply terminal V _DD ), pM
OSp41 becomes non-conductive, nMOSn41 becomes conductive, the charge of the load capacitance C _L is discharged, and the potential of the output terminal changes from high level to low level. When the signal at the input terminal changes from high level to low level, pMOSp4
1 conducts to charge the load capacitance C _L and the nMOS n41 becomes non-conductive, so that the potential of the output terminal O changes from low level to high level.

Here, the speed at which the output terminal O changes from the high level to the low level is faster as the threshold voltage of the nMOSn41 is smaller, and the speed at which the output terminal O changes from the low level to the high level is the absolute threshold voltage of the pMOSp41. As mentioned earlier, the smaller the value, the faster it is.
In the OS transistor, a subthreshold current flows even when a gate voltage lower than the threshold voltage, for example, the ground level (V _SS ) is applied. Then, as shown in FIG. 6B, when the threshold voltage is lowered from V1 to V2,
The subthreshold current during non-conduction increases from I1 to I2.

Since the subthreshold current increases about 10 times each time the threshold voltage is lowered by 80 to 90 mV, the power consumption in the mode in which the device is not operating (standby mode) rapidly increases as the threshold voltage decreases. Increase to. Therefore, especially in a device using a battery as a power source, in order to prevent the battery life from being shortened, the threshold voltages of both pMOS and nMOS forming the CMOS are set to 0.
It cannot be reduced to less than about 5 volts, which is an obstacle to realizing high-speed operation under a low power supply voltage due to miniaturization.

FIG. 7A shows the conventional CMO of FIG. 6A.
A conventional example in which the above-mentioned drawbacks in the S circuit are improved will be shown. In this circuit, an nMOSn52 having a large threshold voltage is inserted between a CMOS inverter composed of a pMOSp51 and an nMOSn51 having a small absolute threshold voltage and the ground terminal V _SS, and the gate of the nMOSn52 is at a high level in an operation mode and in a standby mode. The control signal SB which is low level is supplied. When SB is at a high level, that is, in the operation mode, the nMOSn52 having a large threshold voltage is in a completely conductive state, and the source of the nMOSn51 and the nMOSn52 are connected to each other.
Since the potential of the connection point of the drain of 52 is almost at the ground potential, when the signal applied to the input terminal I changes from high level to low level as shown in FIG. 7B, the output terminal O
Potential changes from low level to high level, and when the signal at the input terminal I changes from low level to high level, the output terminal changes from high level to low level. In this circuit, the threshold voltage of the pMOSp51 and the nMOSn51 is as low as about 0.1 to 0.2 V in absolute value. Therefore, even if the voltage applied to the power supply terminal V _DD is a low voltage of 1.5 to 2 V, it can be performed at high speed. Can work.

When SB is at the low level, that is, in the standby mode, the nMOS n52 becomes non-conductive,
Since the threshold voltage of Sn52 is as high as about 0.6V, nMO
Current flowing to the V _SS through Sn52 is slight. Therefore, there is almost no power consumption in the standby mode, and this circuit can improve the drawbacks of the conventional CMOS circuit shown in FIG. 6A.

[0009]

However, in the above-described CMOS circuit of FIG. 7A, the absolute values of the threshold voltages of pMOSp51 and nMOSn51 are nMOSn52.
Since it is smaller than that of nMOSn5 when SB is at a low level, the subthreshold current flowing when the gate of pMOSp51 is at a high level is supplied.
It is several orders of magnitude higher than the subthreshold current flowing through 2. Therefore, when SB goes low and enters the standby mode, the current flowing into the output terminal O through the pMOS p51 becomes larger than the current flowing out through the nMOS n52, and as a result, as shown in FIG. The potential gradually starts to rise, and finally reaches a high level completely equal to the potential of the power supply terminal V _DD . As a result, there is a problem in that the output state before entering the standby mode is not maintained and it becomes difficult to restore the original output state when returning from the standby mode to the operation mode again.

Therefore, an object of the present invention is to make it possible to maintain high-speed operation even when the drive voltage is lowered and to suppress the power consumption during standby to a low level. That is. Thus, in an application device using a battery as a power source, it is intended to prolong the battery life without sacrificing the operating speed.

[0011]

In order to achieve the above-mentioned object, according to the present invention, the first and second power supply terminals (V _DD 1,
V _SS 1), third and fourth power supply terminals (V _DD 2, V _SS 2) which are activated in the first operation mode and are in a floating state in the second operation mode, and an input terminal (I). Provided between the output terminal (O) and the third and fourth power supply terminals,
Between the first and second power supply terminals, a first partial circuit (p11, n11; p21, n21) composed of a CMOS logic circuit having an input terminal connected to the input terminal and an output terminal connected to the output terminal And an output terminal connected to the output terminal, which is capable of holding the output state of the first partial circuit immediately before the start of the second operation mode in the second operation mode.
The second partial circuit (p1
2, n12; p22, p23, n22, n23), and the threshold voltage of the MOS transistor forming the first partial circuit is the MOS forming the second partial circuit.
Provided is a CMOS semiconductor integrated circuit characterized by being smaller in absolute value than a threshold voltage of a transistor.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 (a) is a circuit diagram showing a first embodiment of the present invention, FIG. 1 (b) is a timing chart thereof, and FIG. 2 realizes the circuit of FIG. 1 as an integrated circuit on a semiconductor substrate. It is a top view at the time of doing. In FIG. 1A, −
The pMOSp11 having a threshold voltage of about 0.2 V and the nMOSn11 having a threshold voltage of about 0.2 V are connected to their drains as output ends, and are also connected to their gates as input ends to form an CMOS inverter. As the first
Is provided between the third power supply terminal V _DD 2 and the fourth power supply terminal V _SS 2, and its input end is the input terminal I.
The output terminal is connected to the output terminal O.

Similarly, a pM having a threshold voltage of about -0.6 V
OSp12 and nMOSn1 having a threshold voltage of about 0.6V
The drains 2 are connected to each other to serve as output terminals, and the gates are also connected to serve as input terminals to form a second partial circuit as an inverter having a CMOS structure, and the first power supply terminal V _DD 1 and the second It is provided between the power supply terminal V _SS 1 and its input end is connected to the input terminal I and its output end is connected to the output terminal O. Here, pMOSp11 and nMOSn11
Has a wider channel width than pMOSp12 and nMOSn12 and is configured to have a larger current supply capability. A first switching device SW1 is provided between V _DD 1 and V _DD 2, and a second switching device SW1 is provided between V _SS 1 and V _SS 2.
Switching elements SW2 are provided respectively, and all the switching elements are turned on in the operation mode and turned off in the standby mode.

Next, the operation of the CMOS circuit shown in FIG. 1A will be described with reference to the timing chart of FIG. In the operation mode, since both SW1 and SW2 are conducting, V _DD 1 and V _DD 2 give substantially the same voltage, and V _SS 1 and V _SS 2 also give the substantially same ground potential. In the standby mode, since both SW1 and SW2 are cut off, V _DD 1 and V _SS 1 are the same as the potential in the operation mode, but V _DD 2 and V _SS 2 are separated from the power supply and are in a floating state. .

In the operation mode in which the switching element is conducting, when the signal at the input terminal I changes from the low level to the high level at time t1, the pMOSp11 and pMOSp12 are turned off and the nMOSn is turned on.
11 and the nMOS n12 are switched from non-conductive to conductive, the potential of the output terminal O drops from high level to low level. At this time, most of the discharge from the output terminal O is as shown in FIG. Since the threshold voltage is low, it is possible to conduct electricity first and to flow a large amount of current nMO.
Since it is performed by Sn11, the switching speed is sufficiently high.

Next, at this time t2, when the switching elements SW1 and SW2 are cut off to enter the standby mode, the pMOSp11 and the nMOSn11 are disconnected from the power source, so that the currents are low even though their threshold voltages are low in absolute value. but does not flow, since the nMOSn12 to drain the V _SS 1 is connected maintains the conductive state, the output terminal O is maintained at a low level which is the potential before the standby mode. Further, at this time, since the pMOS p12 is a MOS transistor having a large threshold voltage in absolute value, the subthreshold current is small, and therefore the power consumption in the standby mode is small.

Next, at time t3, when SW1 and SW2 are turned on again to enter the operation mode, pMOSp11
The power supply voltage is supplied to the inverter formed by the nMOSn11 and the nMOSn11.
Since the standby mode period was maintained by the inverter 2 and the nMOSn12 inverter, the low level remains unchanged. Next, at time t4 in the operation mode, the input terminal I
When the signal of changes from high level to low level, nM
Since the OSn11 and the nMOSn12 change from conducting to non-conducting and the pMOSp11 and pMOSp12 change from non-conducting to conducting, the potential of the output terminal O rises from low level to high level. As shown in FIG. 1B, the part is performed by the pMOSp11 which has a low absolute value of the threshold voltage and can flow a large current, and therefore can operate at high speed.

Next, at time t5, when the switching elements SW1 and SW2 are cut off and the mode shifts to the standby mode, the power supply voltage is not supplied to the inverter composed of pMOSp11 and nMOSn11, so that no current flows,
The pMOSp12 of the inverter composed of the pMOSp12 and the nMOSn12 maintains the conductive state and maintains the potential of the output terminal during the standby mode period. At this time, the non-conductive nMOS
Since n12 has a high threshold voltage, only a small subthreshold current flows, so that the power consumption during the standby mode is extremely low.

Next, the arrangement on the integrated circuit of the first embodiment will be described with reference to FIG. As shown in the figure, pMOSp11 and pMOSp are provided in the n-well 1.
12 is formed, and nMOSn11 and nMOSn12 are formed on the p-type substrate. pMOSp12 and n
Since the MOSn 12 does not need to contribute to the switching operation and the transistor width of the minimum dimension necessary for stable operation as a MOS transistor is sufficient, the addition of these elements makes little increase in the occupied area.

In FIG. 2, 2 is pMOSp11, p
P-type diffusion layers forming 12 source / drain regions, 3
Is an n-type diffusion layer forming the source / drain regions of the nMOSs n11 and n12, 4 is a polysilicon film forming the gate electrode of each transistor, 5 is a p-type diffusion layer 2, n
A contact between the type diffusion layer 3 or the polysilicon film 4 and the Al wiring 6 is shown.

Although the embodiments shown in FIGS. 1 and 2 relate to the inverter, they can be extended to circuits other than the inverter circuit. For example, the inverter of the first partial circuit pMOSp11 and nMOSn11 is replaced with a CMOS 2-input NAND circuit, and at the same time, the second partial circuit pMOSp12 and nMOSn11 is replaced.
By replacing the twelve inverters with a two-input NAND circuit having a CMOS structure, the circuit according to the present invention having a two-input NAND logic function can be realized and can be expanded to realize various logic functions.

FIG. 3A is a circuit diagram showing a second embodiment of the present invention. As shown in FIG. 3A, -0.2V
A pMOSp21 having a threshold voltage of about 0.2V and an nMOSn21 having a threshold voltage of about 0.2V are connected to each other to serve as output terminals, and are also connected to their gates to serve as input terminals. It constitutes a circuit and is provided between the third power supply terminal V _DD 2 and the fourth power supply terminal V _SS 2, and its input end is connected to the input terminal I and its output end is connected to the output terminal O.

Further, pMO having a threshold voltage of about -0.6 V
The Sp22 and the nMOSn22 having a threshold voltage of about 0.6 V form a first inverter having a CMOS structure in which their drains are connected to form an output terminal and their gates are connected to form an input terminal. PMOS p23 having a threshold voltage of about 6 V and nMOS having a threshold voltage of about 0.6 V
n23 forms a second inverter having a CMOS structure in which the drains of the n23 are connected to each other to serve as the output end, and the gates of the n23 are connected to serve as the input end. Input terminals of the two inverters are connected, and these two inverters are both connected to the first power supply terminal V
_It is provided between _DD 1 and the second power supply terminal V _SS 1 to form a second partial circuit. The input terminal of the first inverter that is also the input terminal of the second partial circuit is connected to the output terminal O, and the output terminal of the second inverter that is also the output terminal of the second partial circuit is also connected to the output terminal O. It is connected. Also in this embodiment, the pMOSp forming the first partial circuit is formed.
21 and the nMOS n21 form a second partial circuit p
The gate width is formed wider than that of the MOSp22, p23, and the nMOSn22, n23, and the MOSp22, p23, and nMOSn22, n23 are configured to have a larger current supply capability.

Next, the operation of the CMOS circuit shown in FIG. 3A will be described with reference to the timing chart of FIG. 3B. In operating mode, SW1 and S
Since W2 is conducting, as in the case of FIG. 1 (a),
V _DD 1 and V _DD 2 give substantially the same voltage, and V _SS 1 and V _DD
SS 2 also gives approximately the same ground potential.

At time t1 in the operation mode, when the potential of the input terminal I changes from low level to high level, p
When the MOSp21 changes from conducting to non-conducting, the nMOSn21
Becomes non-conductive, the potential of the output terminal O changes from high level to low level. At this time, nMOSn
Since 21 is a MOS transistor having a low threshold voltage and a large current supply capability, switching is performed at high speed. In response to the change of the output terminal O, the pMOSp22 becomes conductive and the nMOSn22 becomes nonconductive, so that the potential of the output terminal A of the first inverter in the second partial circuit rises to the high level and the pMOSp23 becomes non-conductive. Conduct, nMO
Although the operation is completed by making Sn23 conductive, it does not change because the potential of the output terminal O is already set to the low level. In this way, a pMOSp having a high threshold voltage in absolute value
22, nMOSn22, pMOSp23 and nMOS
Since n23 does not affect the switching speed of the signal from the input terminal I to the output terminal O, the n23 has a small driving capability.
An S transistor can be used.

Next, at time t2, SW1 and SW
When 2 is cut off and enters the standby mode, pMOSp21
Since the nMOS n21 is disconnected from the power supply, no current flows though these threshold voltages are low in absolute value. At this time, the pMOSp22 is in the conductive state in the first inverter and the nMOSn23 is in the conductive state in the second inverter, and the state immediately before the standby mode is maintained is maintained. Therefore, the point A is at the high level and the output terminal O Keeps low level. Further, at this time, the nM which is in the non-conduction state
Since both the OSn22 and the pMOSp23 have a high threshold voltage in absolute value, the subthreshold current is small, and therefore the power consumption in the standby mode is extremely small.

Next, at time t3, SW1 and SW
When 2 becomes conductive again and returns to the operation mode, pMOSp21
The power supply voltage is supplied to the inverter of the first partial circuit composed of the pMOSp22, the nMOSn22, and the nMOSn21.
In the second partial circuit composed of Sp23 and nMOSn23, the standby mode period is also maintained at the low level, and therefore does not change.

Next, at t4 in the operation mode, when the signal at the input terminal I changes from the high level to the low level, the nMOS n21 changes from conductive to non-conductive, and the pMOS n21 changes.
The potential of the output terminal O rises from a low level to a high level because the p21 changes from non-conducting to conducting, but at this time, the pMOS p21 is a MOS transistor having a large absolute threshold voltage and a large current driving capability. , Switching is performed at high speed. NMO in response to changes in output terminals
Sn22 becomes conductive, point A drops to low level, and pMOSp23 becomes conductive, completing the operation.

Next, when SW1 and SW2 are cut off again to enter the standby mode, the pMO forming the first partial circuit is formed.
The Sp21 and the nMOSn21 are separated from the power source, and the second
In the partial circuit, the nMOS n22 and the pMOS p23 maintain the conductive state and maintain the output terminal at the high level during the standby mode period. Also in this case, the non-conductive pMOSp2
Since 2 and nMOSn23 are both MOS transistors whose threshold voltage is high in absolute value, the subthreshold current is small and the power consumption in the standby mode is small.

FIG. 4 is a plan view of a semiconductor device obtained by integrating the CMOS circuit shown in FIG. 3 into an integrated circuit. As shown in FIG. 4, pMOSp21 and pMOSp2 are provided in the n-well 1.
2, pMOSp23 is formed, and nMO is formed on the p-type substrate.
Sn21, nMOSn22, and nMOSn23 are formed. As described above, pMOSp22, nMOSn
Since 22, 22, pMOSp23, and nMOSn23 do not contribute to the switching operation, it is desirable to set the transistor width to the minimum dimension necessary for stable operation as a MOS transistor. In FIG. 4, portions corresponding to those of the first embodiment shown in FIG. 2 are designated by the same reference numerals, and a duplicate description will be omitted.

The embodiment shown in FIGS. 3 and 4 is equivalent in function, power consumption, and operating speed to the first embodiment shown in FIGS. 1 and 2, but the embodiment shown in FIGS. In the second embodiment shown, since the second partial circuit requires only two CMOS inverters regardless of the logical function, the logical function of the first partial circuit is more complicated, and if the CMOS is configured in CMOS, more MOs are provided.
When the S transistor is required, there is an advantage that the number of transistors in the second partial circuit can be small. For example, when implementing a 5-input NAND circuit,
In the embodiment described above, a total of 20 MOS transistors are required, 10 in the first partial circuit and 10 in the second partial circuit.
In the embodiment shown in FIGS. 3 and 4, the first partial circuit includes 10 pieces and the second piece.
Since it is possible to realize the total of 14 MOS transistors in the partial circuit of 4 in total, it is possible to keep the increase in the occupied area when integrated into a small amount.

FIGS. 5 (a) and 5 (b) are circuit diagrams showing specific configurations of the power supply terminal and the switching element in the embodiment of the present invention. FIG. 5A shows an example in which the first switching element and the second switching element in the present invention are constituted by MOS transistors having a threshold voltage of about 0.6 V in absolute value. In FIG. 5A, the low voltage CM
The OS circuit portion 31 is a portion formed by the MOS transistors in FIG. 1A or FIG. 3A and includes both the first partial circuit and the second partial circuit. The first switching element, that is, FIG. 1 (a) or FIG.
In the pMOS 32 having an absolute value and a high threshold voltage corresponding to SW1 in (a), the source is connected to the first power supply terminal V _DD 1, the drain is connected to the third power supply terminal V _DD 2, and the gate is in the operation mode. A signal ST that becomes high level in the low level and the standby mode is added to the second switching element,
That is, the nMOS 33 having a high threshold voltage corresponding to SW2 in FIG. 1A or FIG. 3A is the second power supply terminal V _SS.
The source is connected to 1, the drain is connected to the fourth power supply terminal V _SS 2, and the signal SB that is high level in the operation mode and low level in the standby mode is applied to the gate.

In the operation mode, since ST is at a low level and the pMOS 32 is in a conductive state, a voltage substantially the same as the voltage at the terminal V _DD 1 can be supplied to the terminal V _DD 2 and SB is at a high level. Since the nMOS 33 becomes conductive, the terminal V _SS 2 can be supplied with the same potential as the ground potential of the terminal V _SS 1. In the standby mode, since ST is at a high level and the pMOS 32 is in a non-conducting state, the terminal V _DD 2 can be disconnected from the terminal V _DD 1, and at this time, the threshold voltage of the pMOS 32 is high, so that a subthreshold current hardly flows. . Since SB is at a low level and the nMOS 33 is in a non-conducting state, the terminal V
_SS 2 can be disconnected from the terminal V _SS 1, and at this time almost no subthreshold current flows due to the high threshold voltage of the nMOS 33.

FIG. 5B shows the pMO in FIG. 5A.
S32 to pnp bipolar transistor 34, nMO
The Spn is replaced with an npn bipolar transistor 35, the emitter of the pnp bipolar transistor 34 is connected to the terminal V _DD 1, the collector is connected to the terminal V _DD 2, and the signal ST is supplied to the base. The emitter is connected to the terminal V _SS 1, the collector is connected to the terminal V _SS 2, and the signal SB is supplied to the base. The same operation as in the case of FIG. 5A is performed, and the same effect is obtained.

In the embodiments of FIGS. 1A and 3A, the threshold voltage of the MOS transistor of the first partial circuit is 0.1 to 0.4 V for nMOS and −0.
1 to -0.4V is desirable, the lower limit of the absolute value is determined by the value for maintaining the enhancement type, and the upper limit is determined by the absolute value being lower than that of the MOS transistor forming the second partial circuit. Similarly, the threshold voltage of the MOS transistor of the second partial circuit is 0.
5 to 1.0 V, pMOS is preferably -0.5 to -1.0 V, and the lower limit of the absolute value is determined by the allowable upper limit of the subthreshold current in consideration of the current supply in the battery, and the upper limit is about 1.5 to 2 V. Is determined in consideration of the low voltage operation.

[0036]

As described above, according to the present invention, the first partial circuit composed of the MOS transistor having a low threshold voltage and the second partial circuit composed of the MOS transistor having a high threshold voltage are provided, and in the operation mode, According to the present invention, the high speed switching operation is performed by the former and the former is disconnected from the power supply so that the output level is maintained only by the latter in the standby mode. The power consumption in the standby mode can be suppressed to an extremely low level. Therefore, according to the present invention, it is possible to prolong the life of the battery in the device using the battery as the power source without lowering the operating speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention and a timing chart thereof.

FIG. 2 is a plan view showing the arrangement on the integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a second embodiment of the present invention and a timing chart thereof.

FIG. 4 is a plan view showing the arrangement on the integrated circuit according to the second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a specific example of a switching element according to an embodiment of the invention.

FIG. 6 is a circuit diagram of a first conventional example and a characteristic curve diagram thereof.

FIG. 7 is a circuit diagram of a second conventional example and its timing chart.

[Explanation of symbols]

p11, p21, p41, p51 low threshold voltage p-channel MOS transistors p12, p22, p23, 32 high threshold voltage p-channel MOS transistors n11, n21, n41, n51 low threshold voltage n-channel MOS transistors n12, n22, n23 , N52, 33 High threshold voltage n-channel MOS transistor 1 n-well 2 p-type diffusion layer 3 n-type diffusion layer 4 polysilicon film 5 contact 6 Al wiring

Front page continuation (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H03K 17/687 19/0175 9473-5J H03K 17/687 F 8321-5J 19/00 101 F

Claims (5)

[Claims] 1. A first power supply terminal, a second power supply terminal, third and fourth power supply terminals which are activated in the first operation mode and are in a floating state in the second operation mode, an input terminal, and an output terminal. A first partial circuit which is provided between the third and fourth power supply terminals and has an input end connected to the input terminal and an output end connected to the output terminal, the first partial circuit including a CMOS logic circuit; A CMOS configuration in which an output terminal provided between two power supply terminals is connected to the output terminal and can hold the output state of the first partial circuit immediately before the start of the second operation mode in the second operation mode. And a threshold voltage of a MOS transistor forming the first partial circuit is smaller in absolute value than a threshold voltage of a MOS transistor forming the second partial circuit. Characterized by CMOS type semiconductor integrated circuit. 2. The CMOS according to claim 1, wherein the second partial circuit is composed of a CMOS circuit having the same structure as the first partial circuit, and an input end is connected to the input terminal. Type semiconductor integrated circuit. 3. The CMOS type semiconductor integrated device according to claim 1, wherein the second partial circuit is composed of cascaded CMOS inverters of two stages and an input terminal thereof is connected to the output terminal. circuit. 4. A disconnection state between the first power supply terminal and the third power supply terminal and between the second power supply terminal and the fourth power supply terminal in a second operation mode. The CMOS type semiconductor integrated circuit according to claim 1, wherein a switching element is connected. 5. A disconnection state between the first power supply terminal and the third power supply terminal and between the second power supply terminal and the fourth power supply terminal in a second operation mode, respectively. The first and second switching elements are connected,
2. The CMOS according to claim 1, wherein the second switching elements have a complementary relationship with each other and control signals having a complementary relationship with each other are input to their respective input ends.
Type semiconductor integrated circuit.