JPH09205360A - Logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a logic circuit which is capable of suppressing the increase of layout area, increasing the speed up of a circuit and reducing power consumption. SOLUTION: Between the supply line 1 of power source voltage VCC and a node ND1 , a switching transistor PTS and pMOS transistors PT1 ,..., PTN are serially connected, the gate of the switching transistor PTS is connected with the input terminal ENB of an enable signal, the gates of the pMOS transistors PT1 ,..., PTN in which threshold voltage Vth is set lower than the normal voltage are connected with input terminals IP1 ,..., IPN, respectively, nMOS transistors NTR1 ,..., NTRsN are connected in parallel between the node ND1 and a ground line 2, and the gates are connected with the input terminals IP1 ,..., IPN. Thus, the area of circuit layout can be reduced, the operating speed up can be contrived and power consumption can be reduced, in addition to the reduction of the channel widths of the transistors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit such as a CMOS circuit formed by using a metal insulating film semiconductor (MIS) transistor.

[0002]

2. Description of the Related Art In a multi-input NOR or multi-input NAND type logic circuit composed of a CMOS circuit, in a circuit including a part in which MOS transistors are connected in series in multiple stages, in order to make current values match, the parts connected in series are It is necessary to set the channel width of the transistor large according to the number of stages.

For example, in the normal inverter circuit shown in FIG. 4, a p-channel MOS (hereinafter referred to as pMOS) transistor PT and an n-channel MOS (hereinafter referred to as nM).
In order to match the channel current value of the transistor NT (referred to as OS), it is necessary to set the ratio of the channel widths of the p-channel and the n-channel to 2: 1.

Further, FIG. 5 shows a pMOS transistor PT.
₁ , ..., PT ₄ and nMOS transistor NTR ₁ ,.
₄ shows a circuit diagram of a 4-input NOR type logic circuit configured by NTR ₄ . In the case of the 4-input NOR circuit shown in FIG. 5, in order to match the current values of the p-channel and the n-channel, the ratio of the channel widths of the p-channel and the n-channel is 8:
Must be set to 1.

[0005]

In the above-described conventional logic circuit, when the number of inputs increases, the number of MOS transistors connected in series also increases, and the channel width must be set accordingly. , The layout area becomes very large. Furthermore, as the channel width of the transistor increases, so does the input capacitance.
There is a problem that the operation speed of the circuit is reduced and the power consumption is increased.

[0006] For example, nMOS transistor NTR ₁ shown in FIG. 5, ..., if the input capacitance of NTR ₄ is respectively one unit, pMOS transistors PT _1, ..., PT ₄
The input capacity of each becomes 8 units. Then, as shown in FIG. 6, these four pMOS transistors PT ₁ ,
..., PT ₄ and four nMOS transistors NTR ₁ ,
The total input capacity of NTR ₄ is 36 units. Further, as the number of inputs increases, the input capacity also increases, resulting in a large input capacity of the multi-input logic circuit, resulting in a decrease in the operating speed of the circuit and an increase in power consumption.

The present invention has been made in view of the above circumstances, and an object thereof is to increase the channel current value without increasing the channel width of a transistor and to suppress an increase in layout area. The purpose of the present invention is to provide a logic circuit capable of speeding up the circuit and further reducing power consumption.

[0008]

In order to achieve the above object, the present invention is a logic circuit which outputs a signal of a first power supply level or a second power supply level according to an input signal level, and a threshold circuit. The value voltage is set lower than usual, the gate electrodes are respectively connected to different input terminals, and the plurality of first power supplies are connected in series between the first power supply and the output node.
A conductive type metal insulating film semiconductor transistor, and a plurality of second conductive type metal insulating film semiconductor transistors connected in parallel between the output node and the second power source and having gate electrodes connected to the different input terminals, respectively. Have and.

The logic circuit of the present invention is connected in series between the first conductive type metal insulating film semiconductor transistor connected in series and the first power source, and the gate electrode is connected to the control signal input terminal. And a switching metal insulating film semiconductor transistor.

According to the logic circuit of the present invention, for example, in a multi-input logic circuit formed of a plurality of metal insulating film semiconductor transistors, a plurality of first power sources and a plurality of series-connected first power supply nodes are connected in series. The threshold voltage of the one-conductivity-type metal insulating film semiconductor transistor is set lower than usual. As a result, the current value can be set large without increasing the channel width of the first conductivity type metal insulating film transistor, the increase of the circuit layout area can be suppressed, the input capacitance can be reduced, and the operation speed of the circuit can be reduced. Improvement and low power consumption can be achieved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a logic circuit according to the present invention, which is a circuit diagram of a NOR type logic circuit composed of MOS transistors and its equivalent. The circuit is shown. 1A is a circuit diagram of a NOR circuit including MOS transistors, and FIG. 1B is a circuit diagram of FIG.
It is an equivalent circuit of the NOR circuit shown in (a). In FIG. 1, 1 is a supply line for the power supply voltage V _CC , 2 is a ground line, PTS is a switching transistor, and PT ₁ , ..., PT _N are pM.
OS transistors, NTR ₁ , ..., NTR _N are nMOS
Transistor and ENB are enable signal input terminals EN
B, IP ₁ , ..., IP _N are input terminals, ND ₁ is a node,
OP indicates each output terminal.

As shown in FIG. 1A, the switching transistor PTS and the pMOS transistors PT ₁ , ...,
PT _N is connected in series between the supply line 1 of the power source voltage V _CC and the node ND _1, and the gates of these pMOS transistors are connected to the input terminals IP ₁ , ..., IP _N , respectively.
The gate of the switching transistor PTS is connected to the enable signal input terminal ENB. The nMOS transistor NTR _1, ..., NTR _N are connected in parallel between node ND ₁ and the ground line 2, these nMOS transistors NTR _1, ..., input terminals IP ₁ gate of NTR _N, ..., IP Connected to _N. further,
The node ND ₁ is connected to the output terminal OP.

A NOR type logic circuit is constructed by the above configuration. In this NOR circuit, pMOS
The gate of the switching transistor formed by the transistor PTS is connected to the enable signal input terminal ENB, and the operating state of the circuit is controlled by the control signal input to the enable signal input terminal ENB. For example, when a high level control signal is input to the enable signal input terminal ENB, the switching transistor PTS
Becomes non-conductive, and the NOR circuit does not operate. When a low-level control signal is input to the enable signal input terminal ENB, the switching transistor PTS becomes conductive and the NOR circuit operates. As mentioned above, this N
The OR circuit is set to the active state by the low level control signal.

[0014] Then, the present first embodiment, pMOS transistors PT ₁ constituting a NOR circuit shown in FIG. 1 (a), ..., PT N threshold voltage V _th is a normal p of
It is set lower than the MO transistor, and the supply line 1 of the power supply voltage V _CC and these pMOS transistors PT ₁ , ..., P
Switching transistor PT connected between T _N and
The threshold voltage V _{th of} S is set similarly to a normal pMOS transistor.

When a high level control signal is input to the enable signal input terminal ENB, the switching transistor PTS is rendered non-conductive, and the generation of leak current can be suppressed. Hereinafter, the operation of the circuit will be described in the case where the low level control signal is input to the enable signal input terminal ENB and the NOR circuit is in the active state.

First, when low level signals are input to the input terminals IP ₁ , ..., IP _N , all the pMOS transistors PT ₁ , ..., PT _N become conductive, and the nMOS transistors NTR ₁ ,. since NTR _N are all non-conducting state, switching transistors PTS and the pMOS transistor PT ₁ node ND ₁ is conductive, ..., are connected via a PT _N to the supply line 1 of the power supply voltage V _CC, i.e., the node ND ₁ is held at high level, and the output terminal OP is held at high level.

Meanwhile, the input terminal IP _1, ..., when a high level signal to one of IP _N is entered, pMOS transistors PT _1, ..., one of PT _N becomes nonconductive, also, nMOS transistor NTR ₁ , ..., NTR
_Since any one of _N becomes conductive, the node ND ₁ is insulated from the supply line 1 of the power supply voltage V _CC , and the node ND ₁ becomes conductive nMOS transistors NTR ₁ , ..., N.
It is connected to the setting line 2 via any one of TR _N , the node ND ₁ is held at a low level, that is, the set potential, and the output terminal OP is also held at the ground potential.

As described above, the circuit shown in FIG. 1A constitutes a NOR type circuit, and the operation of the NOR logic circuit is realized.

In the present embodiment, pMOS transistors PT _1, ..., by the threshold voltage V _th of PT _N is set lower than usual, also the size of the transistor is a like normal more current Can be drained,
The area of the logic circuit can be reduced. Particularly, in a multi-input logic circuit, it is an effective means when transistors are connected in series in multiple stages.

For example, taking a 4-input NOR circuit as an example, the channel width ratio between the p-channel and the n-channel in an ordinary inverter must be 2: 1, but when a low threshold voltage V _th transistor is adopted. , The channel width ratio may be set to 1: 1. In the case of the same 4-input NOR circuit, the input capacitance becomes as small as 16 units as shown in FIG. It can be seen that the input is reduced to less than half as compared with the input 36 units of the conventional 4-input NOR circuit shown in FIG.

As described above, according to this embodiment,
If the power supply voltage V_CCSupply line 1 and node ND₁Between
Switching transistor PTS and pMOS transistor
Star PT₁,,, PT_NAre connected in series and switching
The gate of the transistor PTS is connected to the enable signal input terminal E.
Connect to NB, pMOS transistor PT₁,,, PT
_NThe gate of the input terminal IP₁,,, IP_NContact each
Continue, and node ND ₁NMOS between ground line 2 and
Transistor NTR₁, ..., NTR_NConnected in parallel,
pMOS transistor PT₁,,, PT_NThreshold voltage
Pressure V_thIs set lower than a normal PMOS transistor
Therefore, increasing the channel width of these pMOS transistors
Can be suppressed, the area of the circuit layout can be reduced,
The input capacitance can be reduced and the operation speed of the circuit can be increased.
Power consumption can be reduced.

Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of the logic circuit according to the present invention, showing a circuit diagram of a NAND type logic circuit constituted by MOS transistors and its equivalent circuit. There is. 3A is a circuit diagram of a NAND circuit including MOS transistors, and FIG. 3B is a circuit diagram of FIG.
It is an equivalent circuit of the NAND circuit shown in (a). In FIG. 3, 1 is a supply line for the power supply voltage V _CC , 2 is a ground line, and NTS
Is a switching transistor, NT ₁ , ..., NT _N are n
The MOS transistors, PTR ₁ , ..., PTR _N are pMO
S transistor and ENB are enable signal input terminals EN
B, IP ₁ , ..., IP _N are input terminals, ND ₂ is a node,
OP indicates each output terminal.

As shown in FIG. 3A, the nMOS transistors NT ₁ , ..., NT _N and the switching transistor NTS are connected in series between the node ND ₂ and the ground line 2, and the gates of these nMOS transistors are respectively connected. input terminal IP _1, ..., are connected to the IP _N, the gate of the switching transistor NTS is connected to the enable signal input terminal ENB. Further, pMOS transistor PTR _1, ..., are connected in parallel between the PTR _N is the supply line 1 and the node ND ₂ in the power supply voltage V _CC, pMOS transistor PTR _1, ..., each gate input terminal of the PTR _N IP ₁ , ..., connected to IP _N. Further, the node ND ₂ is connected to the output terminal OP.

A NAND type logic circuit is constructed by the above configuration. In this NAND circuit, nM
The gate of the switching transistor formed by the OS transistor NTS has the enable signal input terminal EN.
The circuit is controlled by the control signal connected to B and input to the enable signal input terminal ENB. For example, when a high level control signal is input to the enable signal input terminal ENB, the switching transistor N
The TS becomes conductive and the NAND circuit operates. When a low level control signal is input to the enable signal input terminal ENB, the switching transistor NTS becomes non-conductive and the NAND circuit does not operate. As described above, this NAND circuit is set to the active state by the high level control signal.

In the second embodiment, the threshold voltage V _{th of} the nMOS transistors NT ₁ , ..., NT _N forming the NAND circuit shown in FIG. 3A is set lower than that of a normal nMOS transistor. And these nM
The threshold voltage V _th of the switching transistor NTS connected between the OS transistors NT ₁ , ..., NT _N and the ground line 2 is set similarly to a normal nMOS transistor.

When a low level control signal is input to the enable signal input terminal ENB, the switching transistor NTS is rendered non-conductive, and the generation of leak current can be suppressed. The operation of the circuit will be described below in the case where a high-level control signal is input to the enable signal input terminal ENB and the NAND circuit is in the active state.

First, when high level signals are input to the input terminals IP ₁ , ..., IP _N , all the nMOS transistors NT ₁ , ..., NT _N become conductive, and the pMOS transistors PTR ₁ ,. Since PTR _N is all non-conducting, the node ND ₂ is connected to the power supply voltage V
_CC insulated supply line 1 and the switching transistors NTS and nMOS transistors NT ₁ further node ND ₂ is conducting, ..., via the NT _N connected to the ground line 2, the node ND ₂ is the low level of the ground potential The output terminal OP is held at a low level.

On the other hand, when a low level signal is input to any of the input terminals IP ₁ , ..., IP _N , any of the nMOS transistors NT ₁ , ..., NT _N becomes non-conductive, and the pMOS transistor is turned on. PTR ₁ , ..., PTR
_Since any one of _N is in a conductive state, the node ND ₂ is in a conductive state in the pMOS transistors PTR ₁ , ..., PTR.
_The node ND ₂ is connected to the supply line 1 of the power supply voltage V _CC via any one of _N and the node ND ₂ is at a high level, that is, the power supply voltage V _CC.
, And the output terminal OP is also held at a high level.

As described above, the circuit shown in FIG. 3A constitutes a NAND type circuit, and the operation of the NAND logic circuit is realized.

In the second embodiment, by setting the threshold voltage V _th of the nMOS transistors NT ₁ , ..., NT _N lower than that of a normal nMOS transistor, the size of the transistor is the same as that of a normal transistor. Can flow a larger current and can reduce the area of the logic circuit. Particularly, in a multi-input logic circuit, it is an effective means when transistors are connected in series in multiple stages.

[0031]

As described above, according to the logic circuit of the present invention, by setting the threshold voltage of the transistor connected in series to be low, a larger current can flow without increasing the channel width. Therefore, the area of the circuit layout can be prevented from increasing, and the input capacitance of the circuit can be suppressed, so that there is an advantage that the operation speed of the circuit can be increased and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a logic circuit according to the present invention.

FIG. 2 is a diagram showing an input capacitance of a logic circuit according to the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the logic circuit according to the present invention.

FIG. 4 is a circuit diagram showing a conventional inverter.

FIG. 5 is a circuit diagram of a conventional 4-input NOR circuit.

FIG. 6 is a diagram showing an input capacitance of a conventional 4-input NOR circuit.

[Explanation of symbols]

1: Power supply voltage V _CC supply line 2 ... ground line ENB ... enable signal input terminal PTS of, NTS ... switching transistors _{PT 1, ..., PT N,} PTR 1, ..., PTR N ... pMO
S transistor _{PT 1, ..., PT N,} NTR 1, ..., NTR N ... nMO
S transistor IP ₁ , ..., IP _N ... input terminal ND ₁ , ND ₂ ... node OP ... output terminal V _CC ... power supply voltage GND ... ground potential

Claims (2)

[Claims] 1. A logic circuit which outputs a signal of a first power supply level or a second power supply level according to an input signal level, wherein a threshold voltage is set lower than usual and gate electrodes are different from each other. A plurality of first conductivity type metal insulating film semiconductor transistors connected to the terminal in series between the first power supply and the output node, and in parallel between the output node and the second power supply. A logic circuit having a plurality of second conductivity type metal insulating film semiconductor transistors which are connected to each other and whose gate electrodes are respectively connected to the different input terminals. 2. A metal insulating film semiconductor for switching, which is connected in series between the first conductive type metal insulating film semiconductor transistor connected in series and the first power supply and has a gate electrode connected to a control signal input terminal. A logic circuit having a transistor.