JPH1117521A - Path transistor logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a path transistor logic circuit with small power consumption, small parasitic capacitance and capable of a high speed operation whose chip size is made small. SOLUTION: The path transistor logic circuit is provided with a switch circuit 1 configured only with NMOS transistors(TRs) and with a voltage conversion circuit 2 that converts an output voltage of the switch circuit 1 into a full swing voltage. The voltage conversion circuit 2 is provided with a cross latch load circuit 3 consisting of PMOS TRs P1, P2 and a drive circuit 4 consisting of NMOS TRs N1, N2. An output voltage of the switch circuit 1 is fed to gate terminals of the NMOS TRs N1, N2, and a gate voltage of the PMOS TRs P1, P2 is controlled by the drain voltage. Since the gate terminal of the NMOS TRs N1, N2 keeps a high resistance, no DC current is supplied to the switch circuit 1 and an output voltage of the current conversion circuit 4 is not affected by an ON-resistance of the switch circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pass transistor logic circuit in which a logic circuit is formed by connecting either type of an NMOS transistor or a PMOS transistor in series.

[0002]

2. Description of the Related Art MOS of the same type (N-type or P-type)
A logic circuit configured by combining transistors and performing a logical operation on the basis of a complementary input signal of a positive / inverting type and complementary outputting the result with a polarity of the positive / inverting type is generally a complementary pass transistor logic circuit (CPL circuit: Complementary Pass-). T
ransistor Logic).

FIG. 13 is a diagram showing an example of a CPL circuit composed of four NMOS transistors. FIG. 13 (a)
13 (d) have the same circuit configuration, and the type of signal input to the input terminal is different from the type of signal output from the output terminal. The circuit of FIG.
Different logical operations are performed depending on the types of signals at the input / output terminals.

[0004] For example, the circuit of FIG.
It becomes equivalent to the AND / NAND gate of FIG.
1 has an OR / NOR gate as shown in FIG.
The circuit of FIG. 3C is an EXOR / EXNOR gate as shown in FIG. 14C, and the circuit of FIG.
It is equivalent to a pair of AND / NAND gates.

As described above, the CPL logic circuit shown in FIG. 13 is characterized in that various logic circuits can be configured with a small number of gates, high-speed operation is possible, and power consumption is small.
When formed on a semiconductor substrate, the element formation area can be reduced.

By the way, the CPL circuit is the same type of MOS.
Since the transistors are connected in series, the output voltage is lower than the power supply voltage VDD due to the influence of the threshold voltage of the MOS transistor. For example,
Assuming that three NMOS transistors M1 to M3 are connected in series as shown in FIG. 15 and the power supply voltage VDD is applied to the drain terminal of the first stage NMOS transistor M1 and the gate terminal of each transistor M1 to M3, The source voltage of the NMOS transistor M3 becomes lower than the power supply voltage VDD by the threshold voltage Vth.

For this reason, usually, a voltage conversion circuit for converting the output voltage of the pass transistor logic into a full amplitude voltage (the power supply voltage VDD and the ground voltage) is often provided after the pass transistor logic (IEEE JOURNAL OF SOLID).
-STATE CIRCUITS VOL.25 NO.2 APRIL 1990 p.389-395)
.

FIG. 16 shows a conventional CP having a voltage conversion circuit.
FIG. 3 is a circuit diagram illustrating an example of an L circuit. The circuit of FIG.
Switch circuit 11 composed of only MOS transistors
And inverters I1, I2 and PMOS transistors P1,
A voltage conversion circuit 12 composed of P2. The switch circuit 11 has the above-described pass transistor logic configuration, and has three types of complementary input signals A, A, B, B,.
The result of calculating the exclusive OR (A EXOR B EXOR C) of C and C bars is output as complementary output signals F and F bars.

The PMOS transistors P1 and P2 in the voltage conversion circuit 12 constitute a cross latch load circuit, and are provided for the purpose of preventing a leak current flowing through the inverters I1 and I2. Assuming that the PMOS transistors P1 and P2 are not provided, the output voltage of the switch circuit 11 becomes lower than the voltage obtained by subtracting the threshold voltage Vth of the NMOS transistor inside the switch circuit 11 from the power supply voltage VDD, and the inverter I1 The PMOS transistor (not shown) inside I2 is not completely turned off. Therefore, a leak current flows through the NMOS transistor and the PMOS transistor inside the inverters I1 and I2. On the other hand, if the PMOS transistors P1 and P2 as shown in FIG. 16 are provided, when the output of the switch circuit 11 is logic "1", the power supply voltage V
The input voltage of the inverters I1 and I2 can be raised to near DD, and no leak current flows.

[0010]

However, FIG.
PMOS transistors P1, P2 in the cross latch load circuit of
In order to normally turn on and off, the switch circuit 11
Is required to be sufficiently smaller than the ON resistances of the PMOS transistors P1 and P2. In order to reduce the on-resistance of the switch circuit 11, the size (formation area) of each NMOS transistor constituting the switch circuit 11 must be increased. If the logic inside the switch circuit 11 is complicated, the switch circuit 11, the size of the whole becomes considerably large.

When a CPL circuit having a cross latch load circuit as shown in FIG. 16 is formed on a semiconductor substrate, the size of each MOS transistor constituting the switch circuit 11 increases as the logic of the switch circuit 11 becomes more complicated. When the size of each NMOS transistor increases, the parasitic capacitance increases accordingly, the operating speed decreases, and power consumption increases.

Incidentally, a single output type pass transistor logic circuit has also been proposed (for example, IEEE 1994 CUSTOM IN).
TEGRATED CIRCUITS CONFERENCE p.603-606).

FIG. 17 is a circuit diagram showing an example of a single-output type pass transistor logic circuit described in the above-mentioned document. The circuit of FIG. 17 includes a switch circuit 11a formed of a single-output type pass transistor logic circuit, and an inverter I3 for voltage conversion. Three types of complementary input signals A, A, B, B, C, and C are input to the switch circuit 11a, and as shown in FIG.
(B EXOR C)} is output from the switch circuit 11a. The inverter I3 in FIG. 17 includes PMOS transistors P1 to P3 and N
It is composed of MOS transistors N1 and N2.

In the circuit shown in FIG.
The circuit operation when the output F of a changes from logic “0” to logic “1” will be described. When the output F of the switch circuit 11a is logic "0", the output voltage of the inverter I3 is substantially equal to the power supply voltage VDD, and the load PMOS transistor P3 in the inverter I3 is off. Output F voltage is inverter
When the voltage exceeds the logical threshold voltage of I3, the inverter I3 is inverted and the PMOS transistor P3 is also turned on.
Is the ground voltage.

Next, a circuit operation when the output F of the switch circuit 11a changes from logic "1" to logic "0" will be described. Before the logic changes, the PMOS transistor P3 in the inverter I3 is on, and the voltage of the output OUT is the ground voltage. When the logic of the output F changes to "0", the load current (leakage current) from the power supply voltage VDD is PM
It flows to the ground terminal in the switch circuit 11a via the OS transistor P3 and the output terminal F. Thereafter, when the voltage of the output F becomes lower than the logical threshold voltage of the inverter I3, the inverter I3 is inverted, the PMOS transistor P3 is turned off, and the load current stops flowing.

As described above, the circuit of FIG. 17 has a problem that a leak current flows when the logic of the switch circuit 11a is switched.

In the circuit shown in FIG.
The voltage level of the logic “0” of the output F of 1a is changed to the inverter I3
, It is necessary to lower the on-resistance of the switch circuit 1 to the value of P in the inverter I3.
It must be sufficiently smaller than the on-resistance of the MOS transistors P1 and P2. As described above, in order to reduce the ON resistance in the switch circuit 1, the formation area (size) of each MOS transistor in the switch circuit 1 must be increased, which hinders miniaturization of the chip size, Problems such as an increase in capacity, a decrease in operation speed, and an increase in power consumption occur.

The present invention has been made in view of the above points, and has as its object to reduce the power consumption, reduce the chip size, reduce the parasitic capacitance, and operate at high speed. Is to provide.

[0019]

In order to solve the above-mentioned problem, the invention of claim 1 is constituted by combining a plurality of either N-type or P-type MOS transistors, and comprises a plurality of types of complementary MOS transistors. A switch circuit that complementarily outputs a result of performing a predetermined logical operation based on the logic of the input signal,
A voltage conversion circuit for amplifying a complementary output voltage output from the switch circuit, and a first and a second corresponding to the complementary output voltage from two output terminals of the voltage conversion circuit.
In a pass transistor logic circuit that complementarily outputs the power supply voltage of the power supply voltage, the voltage conversion circuit has a control gate of a high input resistance to which a complementary output voltage output from the switch circuit is applied, and one of the output terminals And a drive circuit that controls a current flowing inside the circuit in accordance with the complementary output voltage, so that the first power supply voltage becomes the first power supply voltage, and the other voltage of the output terminal becomes the second power supply voltage. And a load circuit for controlling a current flowing inside the circuit in accordance with the output terminal voltage.

According to a second aspect of the present invention, in the pass transistor logic circuit according to the first aspect, the switch circuit and the drive circuit are configured by first conductivity type MOS transistors, and the load circuit is configured by a second conductivity type MOS transistor. It is composed of a type MOS transistor.

According to a third aspect of the present invention, in the pass transistor logic circuit according to the second aspect, the driving circuit comprises:
The first and second MOS transistors are of a conductivity type, and the gate terminals of the first and second MOS transistors are used as the control gates. The load circuit is of a third and a fourth conductivity type. And the source terminals of the first and second MOS transistors are set to the first power supply voltage, and the source terminals of the third and fourth MOS transistors are set to the second power supply voltage. The first and third MOs
The drain terminal of the S transistor and the gate terminal of the fourth MOS transistor are commonly connected to one of the output terminals, and the drain terminals of the second and fourth MOS transistors and the gate terminal of the third MOS transistor Are commonly connected to the other of the output terminals.

According to a fourth aspect of the present invention, in the pass transistor logic circuit according to any one of the first to third aspects, the complementary output voltage corresponding to logic "1" is higher than a logic threshold voltage of the voltage conversion circuit. The switch circuit and the drive circuit are configured to be higher.

According to a fifth aspect of the present invention, a result of performing a predetermined logical operation based on the logic of a plurality of types of complementary input signals is constituted by combining a plurality of either N-type or P-type MOS transistors. In a pass transistor logic circuit including a switch circuit that complementarily outputs the first and second RS flip-flops, the RS flip-flop being set or reset in accordance with the complementary output voltage output from the switch circuit. And a control gate having a high input resistance to which a complementary output voltage output from the switch circuit is applied, and one of the output terminals has a voltage of one of the output terminals. A driving circuit for controlling a current flowing inside the circuit according to the complementary output voltage so as to be the first power supply voltage; A latch circuit for controlling a current flowing through a circuit based on the output terminal voltage so that one of the terminals is maintained at the first power supply voltage and the other of the output terminals is maintained at the second power supply voltage And the output terminals are each connected to a connection path between the drive circuit and the latch circuit.

According to a sixth aspect of the present invention, in the pass transistor logic circuit according to the fifth aspect, the MOS transistor forming the switch circuit and the MOS transistor forming the drive circuit are of the same conductivity type.

According to a seventh aspect of the present invention, in the pass transistor logic circuit according to the sixth aspect, the driving circuit comprises:
The latch circuit includes first and second MOS transistors of the first conductivity type and fifth and sixth M transistors of the second conductivity type.
An OS transistor, wherein the source terminals of the third and fourth MOS transistors are set to the first power supply voltage, and the source terminals of the fifth and sixth MOS transistors are set to the second power supply voltage. And the gate terminals of the third and fifth MOS transistors and the drain terminals of the second, fourth and sixth MOS transistors are commonly connected to one of the output terminals. The gate terminal of the sixth MOS transistor and the drain terminals of the first, third and fifth MOS transistors are commonly connected to the other of the output terminals, and the gate terminals of the first and second MOS transistors are connected. A terminal is used as the control gate.

The invention according to claim 8 is configured by combining a plurality of either N-type or P-type MOS transistors and performing a predetermined logical operation based on the logic of a plurality of types of complementary input signals. And a voltage conversion circuit for amplifying the single output voltage output from the switch circuit. One of the first and second power supply voltages is simply output from the output terminal of the voltage conversion circuit. In the output pass transistor logic circuit, the voltage conversion circuit has a control gate of a high input resistance to which a single output voltage output from the switch circuit is applied, and the output terminal voltage is equal to the first power supply voltage. A drive circuit for controlling a current flowing inside the circuit in accordance with the single output voltage, and the output terminal so that the output terminal voltage becomes the second power supply voltage. And a load circuit for controlling a current flowing through the internal circuit in response to pressure.

According to a ninth aspect of the present invention, in the pass transistor logic circuit according to the eighth aspect, the drive circuit has a source terminal set to the first power supply voltage and a drain terminal connected to the output terminal. First MOS of first conductivity type
A second transistor of a second conductivity type having a drain terminal connected to the output terminal.
A third MOS transistor of a second conductivity type whose source terminal is set to the second power supply voltage and whose drain terminal is connected to the source terminal of the second MOS transistor; A power storage circuit for storing charge in a connection path of the third MOS transistor, wherein gate terminals of the first and second MOS transistors are connected to each other and used as the control gate; The gate terminal
An inverted voltage of the output terminal voltage is applied.

According to a tenth aspect of the present invention, in the pass transistor logic circuit according to the eighth aspect, the drive circuit has a source terminal set to the first power supply voltage and a drain terminal connected to the output terminal. First MO of first conductivity type
The load circuit includes an S transistor, the load circuit includes a second conductive type second MOS transistor having a drain terminal connected to the output terminal, and a source terminal connected to the second M transistor.
A third MOS transistor of a first conductivity type and a depletion type having a drain terminal connected to the source terminal of the OS transistor and having a drain terminal set to the second power supply voltage;
And a power storage circuit for storing a charge in a connection path between the third MOS transistor and the first MOS transistor.
The control terminals of the transistors are connected to each other and used as the control gate, and the inverted terminal of the output terminal voltage is applied to the gate terminal of the third MOS transistor.

According to an eleventh aspect of the present invention, in the power storage circuit, a capacitor element having one end connected to a source terminal of the second MOS transistor and the other end set to the first power supply voltage; A fourth MOS transistor set to the second power supply voltage and having a drain terminal connected to a source terminal of the second MOS transistor; and a gate terminal of the fourth MOS transistor,
A clock for periodically charging the capacitor element is input.

The invention of claim 1 will be described with reference to FIG. 1, for example. A "switch circuit" is a switch circuit 1 in FIG. 1, a "voltage conversion circuit" is a voltage conversion circuit 2, and a "drive circuit" is a The “load circuit” corresponds to the drive circuit 4, and the “load circuit” corresponds to the load circuit 3.

The invention according to claim 3 will be described with reference to FIG. 1, for example. The "first MOS transistor" corresponds to the NMOS transistor N1 in FIG. 1, the "second MOS transistor" corresponds to the NMOS transistor N2, and the " The “third MOS transistor” is connected to the PMOS transistor P1 by a “fourth M transistor”.
The “OS transistor” corresponds to the PMOS transistor P2.

The invention of claim 5 will be described with reference to FIG. 2, for example. A "switch circuit" corresponds to the switch circuit of FIG. 2, an "RS flip-flop" corresponds to the RS flip-flop 5, and a "drive circuit" corresponds to the drive circuit. The “latch circuit” corresponds to the circuit 4 and the “latch circuit” corresponds to the latch circuit 51, respectively.

The invention according to claim 7 will be described with reference to FIG. 2, for example. The "first MOS transistor" corresponds to the NMOS transistor N1 in FIG. 2, the "second MOS transistor" corresponds to the NMOS transistor N2, and the " The “third MOS transistor” is connected to the NMOS transistor N3 by a “fourth MO transistor”.
The S transistor is connected to the NMOS transistor N4,
MOS transistor "is the PMOS transistor P1,
"Sixth MOS transistor" is a PMOS transistor
Each corresponds to P2.

The invention of claim 8 will be described with reference to FIG. 5, for example. The "switch circuit" is the switch circuit 1a in FIG. 5, the "voltage conversion circuit" is the voltage conversion circuit 8, and the "drive circuit" is the drive circuit. The "load circuit" is P for the NMOS transistor N1.
The MOS transistors P1 and P2 correspond to the power storage circuit 9, respectively.

The invention of claim 9 will be described with reference to, for example, FIG. 5. "The first MOS transistor" corresponds to the NMOS transistor N1 in FIG. 5, the "second MOS transistor" corresponds to the PMOS transistor P1, and " The "third MOS transistor" is connected to the PMOS transistor P2 by a "storage circuit".
Respectively correspond to the power storage circuit 9.

The tenth aspect of the present invention will be described with reference to FIG. 8, for example.
, The “second MOS transistor” corresponds to the PMOS transistor P1, the “third MOS transistor” corresponds to the NMOS transistor N2, and the “power storage circuit” corresponds to the power storage circuit 9, respectively.

The invention of claim 11 will be described with reference to FIGS. 5 and 8, for example. The "capacitor element" is a capacitor C, and the "fourth MOS transistor" is a PMOS
Each corresponds to the transistor P4.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a pass transistor logic circuit to which the present invention is applied will be specifically described with reference to the drawings. In the following, a signal with a bar in the drawing is represented by adding “bar” after the signal name.

[First Embodiment] FIG. 1 is a circuit diagram showing a first embodiment of a pass transistor logic circuit according to the present invention. The circuit in FIG. 1 includes a switch circuit 1 configured by combining a plurality of NMOS transistors, and a switch circuit 1.
And a voltage conversion circuit 2 for converting the output of V.sub.1 into a full amplitude voltage (power supply voltage VDD and ground voltage). The switch circuit 1 is
As in the switch circuit 11 of FIG. 16 described above, a predetermined logical operation is performed in accordance with the logic of a plurality of types of complementary (positive inversion) input signals A1 to An and A1 to An bars, and the operation result is complementarily output. . Complementary input signals A2 to An and A2 to An are input to the respective gate terminals of an NMOS transistor (not shown) in the switch circuit 1, and the input signals A1 and A1 are used as current paths (current paths) in the switch circuit 1. ), And complementary output signals F 1 and F bar are output from the other end of this current path.

The voltage conversion circuit 2 shown in FIG. 1 includes a cross latch load circuit 3 composed of PMOS transistors P1 and P2, and a drive circuit 4. The driving circuit 4 is an NMOS transistor
N1 and N2, the gate terminals of the NMOS transistors N1 and N2 are respectively connected to the complementary output terminals F and Fbar of the switch circuit 1, and the source terminals of the transistors N1 and N2 are grounded.

The drain terminal of the NMOS transistor N1 is connected to the drain terminal of the PMOS transistor P1 and PM
Connected to the gate terminal of OS transistor P2, NMOS
The drain terminal of the transistor N2 is connected to the drain terminal of the PMOS transistor P2 and the gate terminal of the PMOS transistor P1. The source terminals of the PMOS transistors P1 and P2 are both set to the power supply voltage VDD,
A voltage obtained by converting the complementary output of the switch circuit 1 to a full amplitude voltage is output from the drain terminals of the PMOS transistors P1 and P2.

Here, the voltage V (H) corresponding to the logic "1" output from the switch circuit 1 is expressed by equation (1), and the voltage V (L) corresponding to the logic "0" is represented by (2). It is expressed by an equation.

V (H) = VDD−Vthn (1) V (L) = 0 (2) where Vthn in the equation (1) is a threshold voltage of an NMOS transistor (not shown) in the switch circuit 1. is there.

In the circuit shown in FIG. 1, the logic threshold voltage of the voltage conversion circuit 2 is lower than the above-described voltage V (H). This can be realized, for example, by devising the circuit configuration of the voltage conversion circuit 2, or by adjusting the threshold voltages of the NMOS transistors N1, N2 at the stage of the manufacturing process.

In the circuit of FIG. 1, for example, when the output F bar of the switch circuit 1 is logic "1", the NMOS transistor N1 in the voltage conversion circuit 2 is turned on, and the output OUT becomes the ground voltage. When the PMOS transistor P2 turns on, the output OUT goes to the power supply voltage VDD. Conversely, when the output F of the switch circuit 1 is logic “1”, the NMOS
The transistor N2 turns on, the output OUT bar goes to the ground voltage, and the PMOS transistor P1 turns on to output OU.
T becomes the power supply voltage VDD.

Unlike the circuit of FIG. 16, the PMOS transistors P1 and P2 of FIG. 1 are turned on and off in accordance with the drain voltages of the NMOS transistors N1 and N2. Even when the switching is performed, no DC current flows in the switch circuit 1. The complementary outputs F and F bar of the switch circuit 1 are NMOS transistors N
1 and N2 are input to the gate terminals, and the PMOS transistor P
Since P1 and P2 are not directly connected to the switch circuit 1, the gate voltages of the PMOS transistors P1 and P2 are not affected by the ON resistance of the switch circuit 1.

For example, each NM constituting the switch circuit 1
Assuming that all OS transistors have the same size,
As the logic in the switch circuit 1 becomes more complicated and the number of connected NMOS transistors increases, the internal resistance of the switch circuit 1 increases, and the rise time and fall time of the output voltage of the switch circuit 1 also increase. However, since no DC current flows inside the switch circuit 1, the output voltages of the switch circuit 1 eventually become V (H) and V (L),
As long as the logic threshold voltage of the voltage conversion circuit 2 is lower than V (H), the voltage conversion circuit 2 operates normally.

Therefore, it is not necessary to reduce the on-resistance by increasing the size of each NMOS transistor constituting the switch circuit 1. When the pass transistor logic circuit of this embodiment is formed on a semiconductor substrate, the chip size is reduced. it can. Also, by reducing the size of each MOS transistor in the switch circuit 1, the parasitic capacitance can be reduced, high-speed operation can be performed, and power consumption can be reduced.

Further, since the switch circuit 1 of this embodiment is formed by a combination of NMOS transistors, similarly to the conventional pass transistor logic circuit, the switch circuit 1 has a smaller number of elements than the case of a static CMOS logic circuit. A circuit can be configured.

[Second Embodiment] In a second embodiment, an RS flip-flop is connected to the output stage of a switch circuit 1 having a pass transistor configuration.

FIG. 2 is a circuit diagram of a second embodiment of the pass transistor logic circuit. The circuit of FIG.
It includes a switch circuit 1 having a pass transistor configuration in which S transistors are connected in series, and an RS flip-flop 5 that is set or reset according to the logic of a complementary output signal output from the switch circuit 1.

The RS flip-flop 5 shown in FIG.
A driving circuit 4 comprising S transistors N1 and N2, and a PMOS
A latch circuit 51 including transistors P1 and P2 and NMOS transistors N1 and N2 is provided. PMOS transistor
The source terminals of P1 and P2 are connected to the power supply voltage terminal VDD,
The source terminals of the MOS transistors N1 to N4 are grounded.

The RS flip-flop 5 has output terminals Q and Q for outputting a full amplitude voltage. The output terminal Q has a drain terminal of the PMOS transistor P2,
The drain terminals of the S transistors N2 and N4, the gate terminal of the PMOS transistor P1, and the gate terminal of the NMOS transistor N3 are connected. The output terminal Q has a drain terminal of the PMOS transistor P1 and NM.
The drain terminals of the OS transistors N1 and N3, the gate terminal of the PMOS transistor P2, and the NMOS transistor N4
Is connected to the gate terminal.

The switch circuit 1 has a logic "1" at the same time.
And outputs signals S and R that do not result in First, the output R of the switch circuit 1 is logic “0” and the output S is logic “0”.
The operation when the value changes from "1" to "1" will be described. When the output S is logic "0", the PMOS transistor P1 is on, and when the output S becomes logic "1", the gate voltage of the NMOS transistor N1 gradually increases. Eventually, NM
The current between the drain and source of the OS transistor N1 is PM
When the current exceeds the drain-source current of the OS transistor P1, the output Q bar of the RS flip-flop 5 becomes the ground voltage. At this time, the PMOS transistor P2 turns on, and the drain voltage Q of the PMOS transistor P2 changes from the ground voltage to the power supply voltage VDD. Also, the NMOS transistor N3 is turned on accordingly.

Even if the output S of the switch circuit 1 changes from logic "1" to logic "0" in this state, the NMOS transistor N3 is kept on, so that the output Q bar of the RS flip-flop 5 is grounded. The voltage does not change.

Next, the operation when the output R of the switch circuit 1 changes from logic "0" to "1" will be described. When the output R becomes logic "1", the NMOS transistor N2 turns on and the output Q of the RS flip-flop 5 becomes the ground voltage. At this time, the PMOS transistor P1 is turned on, and the output Q bar of the RS flip-flop 5 becomes the power supply voltage V.
DD, and the NMOS transistor N4 is turned on accordingly. In this state, even if the output R of the switch circuit 1 changes to low level, the NMOS transistor N4 keeps the ON state, and the output Q does not change with the ground voltage.

As described above, the RS flip-flop 5 shown in FIG. 2 outputs a result set or reset at full amplitude according to the logic of the complementary outputs S and R of the switch circuit 1.
The complementary output of the switch circuit 1 is a control gate of a high input resistance in the drive circuit 4, that is, an NMOS transistor.
Since the signal is input to each of the gate terminals N1 and N2, no DC current flows inside the switch circuit 1.

In the circuit of FIG. 2, when the logic in the switch circuit 1 is complicated and a large number of transistors are connected in series in the switch circuit 1, the internal resistance of the switch circuit 1 increases and the switch circuit 1 The rise time and fall time of the output voltage of No. 1 become long. However, even in such a case, since no DC current flows through the switch circuit 1, the output voltage of the switch circuit 1 eventually becomes (1),
As long as V (H) and V (L) shown in the equation (2) are satisfied, and the condition that the output V (H) is higher than the logical threshold voltage of the RS flip-flop 5, the circuit of FIG. Work,
The influence of the magnitude of the ON resistance in the switch circuit 1 is eliminated. Therefore, even if the logic in the switch circuit 1 is complicated and a large number of NMOS transistors are connected in series in the switch circuit 1, it is not necessary to increase the size of each transistor to reduce the on-resistance, and to reduce the chip size. it can.

[Third Embodiment] In a third embodiment, a voltage conversion circuit is connected to a single output type pass transistor logic circuit, and a capacitor is provided inside the voltage conversion circuit 2. And

FIG. 3 is a circuit diagram of a third embodiment of the pass transistor logic circuit. The circuit of FIG.
It includes a switch circuit 1a having a single output type pass transistor composed of S transistors, and a buffer 6 for converting the output of the switch circuit 1a to a full amplitude voltage. The switch circuit 1a of FIG. 3 has three types of complementary input signals A, A bar,
B, B, C, and C are input, and a result F obtained by performing a logical operation {A NAND (BEXOR C)} as shown in FIG. 4 equivalently is output.

FIG. 5 is a circuit diagram showing a specific configuration of buffer 6 shown in FIG. The buffer 6 has PMOS transistors P1 to P4, NMOS transistors N1 and N2, and a capacitor C. The output terminal F of the switch circuit 1a is connected to the gate terminals of the PMOS transistor P1 and the NMOS transistor N1.

The PMOS transistor P3 and the NMOS transistor N2 constitute an inverter circuit 7, which inverts an input signal and outputs a full amplitude voltage (power supply voltage VDD or ground voltage). The output of the inverter circuit 7 becomes the output OUT of the buffer 6.

A voltage conversion circuit 8 including PMOS transistors P1, P2, P4, an NMOS transistor N1, and a capacitor C is connected to a stage preceding the inverter circuit 7.
This voltage conversion circuit 8 inverts and outputs the output F of the switch circuit 1a. The PMOS transistor P2 in the voltage conversion circuit 8 is connected to the PMOS transistor P2.
The gate voltage of the PMOS transistor P2 is controlled by the output of the inverter circuit 7.

At the connection point between the drain terminal of the PMOS transistor P2 and the source terminal of the PMOS transistor P1,
A power storage circuit 9 including a capacitor C and a PMOS transistor P4 is connected. When the PMOS transistor P2 is off, the power storage circuit 9 stores the PMOS transistor P1
The source voltage of the PMOS transistor P1 is controlled so that the source voltage of the PMOS transistor P1 does not become unstable.

Here, the path to which the output terminal F of the switch circuit 1a is connected is the node p, the connection point between the drain terminal of the PMOS transistor P1 and the drain terminal of the NMOS transistor N1 is the node q, and the source terminal of the PMOS transistor P1 is the node q. The operation of the circuit of FIG. 5 will be described with the connection point between the drain terminal of the PMOS transistor P2 and the drain terminal being the node r.

First, the operation when the output F of the switch circuit 1a changes from logic "0" to logic "1" will be described. When the output F is logic "0", the PMOS transistors P1, P2 and the NMOS transistor N2 are on,
The drain terminal and the source terminal of the PMOS transistor P1 are almost at the power supply voltage VDD. When the voltage of the node p gradually increases and the NMOS transistor N1 turns on, the drain-source resistance of the PMOS transistor P1 increases,
The voltage of the node q gradually decreases and eventually reaches the ground voltage. In response, the PMOS transistor P3 turns on,
The output OUT of the buffer 6 rises to the power supply voltage VDD. At this time, the node r holds the voltage at the time when the PMOS transistors P1 and P2 are turned off.

A control clock φ bar is input from the outside to the gate terminal of the PMOS transistor P4.
The PMOS transistor P4 periodically turns on and off in accordance with the cycle of this clock. PMOS transistor
When P4 turns on, the node r rises to the power supply voltage VDD, and the capacitor C is charged. As a result, the voltage of the node r always becomes the power supply voltage VDD or a voltage slightly lower than the power supply voltage VDD. The control clock φ applied to the gate terminal of the PMOS transistor P4 is
, The PMOS transistor is periodically turned on once every several milliseconds to charge the capacitor C.

Next, the operation when the output F of the switch circuit 1a changes from logic "1" to logic "0" will be described. Before the output F changes to logic "0", the voltage of the node q is the ground voltage, and the output OUT of the buffer 6 is the power supply voltage VDD.
And the PMOS transistor P2 is off. Further, the voltage of the node r is substantially the power supply voltage VDD because the capacitor C is periodically charged. When the output F changes to logic "0", the PMOS transistor P1 is turned on, and the electric charge stored in the capacitor C charges the node q through the source-drain of the PMOS transistor P1. Therefore, the voltage of the node q rises, the NMOS transistor N2 turns on, and the PMOS transistor P3 turns off. Therefore, the output OUT of the buffer becomes the ground voltage, and the PMOS transistor P2 turns on.

The logic of control clock φ bar is "0"
When the logic of the output F of the switch circuit 1a is "1", the voltage of the node r becomes close to the power supply voltage VDD, so that the PMOS transistor P1 is not completely turned off, so that the PMOS transistors P1 and P4 The period during which the control clock φ bar becomes logic “0” is slight with respect to the period of the control clock φ bar,
The increase in power consumption is hardly a problem.

In the pass transistor circuit of FIG. 3, since the output F of the switch circuit 1a is input to each gate terminal of the PMOS transistor P1 and the NMOS transistor N1 in the buffer 6, a load current flows from the buffer 6 to the switch circuit 1a. It does not flow and power consumption can be reduced as compared with the circuit of FIG.

The voltage V of the output F of the switch circuit 1a
As long as (H) is higher than the threshold voltage of the voltage conversion circuit 8, there is no risk of malfunction, the logic in the switch circuit 1a is complicated, and many NMOS transistors are connected in series in the switch circuit 1a. In addition, it is not necessary to increase the size of each NMOS transistor to lower the on-resistance.

[Fourth Embodiment] The fourth embodiment has the same basic circuit configuration as the third embodiment, except that a depletion type MOS transistor is provided inside the voltage conversion circuit 8. There are features.

FIG. 6 is a circuit diagram of a fourth embodiment of the pass transistor logic circuit. The circuit in FIG. 6 includes a switch circuit 1a and a buffer 6a. The configuration of the switch circuit 1a is the same as that of FIG. 3, and equivalently becomes the same as the logic circuit of FIG. The buffer 6a includes an inverter circuit 7 and a voltage conversion circuit 8, as shown in a detailed configuration in FIG.

The inverter circuit 7 is a PMOS transistor
The voltage conversion circuit 8 includes a PMOS transistor P1 and NMOS transistors N1, N2.
3 and a power storage circuit 9 including a PMOS transistor P4 and a capacitor C.

The buffer 6a shown in FIG. 8 is characterized in that a depletion type NMOS transistor N3 is connected to a PMOS transistor P1. The output terminal of the voltage conversion circuit 8 is connected to the gate terminal of the NMOS transistor N3.

The depletion type NMOS transistor N3 has a capability of supplying current by itself when the output F (node p) of the switch circuit 1a is at a low level. , Nodes r and q can be raised to a predetermined voltage.

Therefore, stable operation is possible even with a small supply of electric charge from the power storage circuit 9, and the capacity of the capacitor C can be reduced, so that the pass transistor logic circuit can be downsized.

Next, the signal delay time, current consumption, P
The result of comparing the D product (Power × Delay) by simulation will be described.

FIGS. 9 and 10 are specific circuit diagrams used for the simulation. FIGS. 9A to 9C show examples including the switch circuit 1 of the complementary output type. FIG. 9A is a circuit diagram (CPL: Complementa) of a conventional pass transistor logic in which inverters I1 and I2 are connected at a subsequent stage of the switch circuit 1a.
ry Pass-Transistor Logic), FIG. 9B is a circuit diagram of a conventional pass transistor logic having a pull-up load corresponding to FIG. 16 (PLCPL: P-Load CPL), and FIG. 9C is a first embodiment. Circuit diagram corresponding to the form (OLPL: Output LatchPass-Tra
nsistor Logic).

On the other hand, FIGS. 10A to 10C show examples including a single output type switch circuit 1a. FIG. 10 (a)
Is a conventional circuit diagram (SCPL: Single-ended C) corresponding to FIG.
PL), FIG. 10B is a circuit diagram corresponding to the third embodiment.
(SOLPL1: Single-ended OLPL1), FIG. 10 (c) is a circuit diagram corresponding to the fourth embodiment (SOLPL2: single-ended OLPL1).
2).

FIG. 11 is a plot diagram showing the result of a simulation based on the circuits of FIGS.
Each horizontal axis indicates the number of connection stages of NMOS transistors in the switch circuit 1a. FIG. 11A shows the relationship between the number of connection stages and the signal delay time, FIG. 11B shows the relationship between the number of connection stages and the current consumption, and FIG. 11C shows the relationship between the number of connection stages and the PD product. Each plot in these figures corresponds to the circuit shown on the right side of each figure.

As shown in FIG. 11A, when the number of connection stages in the switch circuit 1a is small, the signal delay time of each circuit does not change much. When the number of connection stages increases, FIG. 9 having a load transistor (PMOS transistor)
The signal delay time of the PLCPL circuit of FIG. 10B and the SCPL circuit of FIG. First, third, fourth embodiment (FIG. 9
The signal delay times of the circuits (c), 10 (b), and 10 (c)) are almost the same.

As shown in FIG. 11B, when the number of connection stages in the switch circuit 1a is small, the OLPL circuit of the first embodiment (FIG. 9C) consumes the most current, and
As the number of connection stages increases, FIG.
(B) The current consumption of the PLCPL circuit increases. The current consumption of the circuits of the third and fourth embodiments (FIGS. 10B and 10C) is always at the lowest level irrespective of the number of connection stages, and the change in current consumption due to the number of connection stages is the same. The number is small as in the first embodiment (FIG. 9C).

As shown in FIG. 11C, when the number of connection stages in the switch circuit 1a is small, the PD product of the OLPL circuit of the first embodiment (FIG. 9C) is different from that of the other circuit. However, when the number of connection stages increases, the PD product of the conventional circuit sharply increases.
The PD product of the circuit (c) does not become so large. Also,
The PD product of the third embodiment (FIG. 10 (b)) and the fourth embodiment (FIG. 10 (c)) is always at the lowest level irrespective of the number of connection stages, and the change due to the number of connection stages is the first embodiment. Small as in the circuit of the embodiment (FIG. 9C).

In each of the embodiments described above, an example has been described in which the switch circuit is constituted by an NMOS transistor. However, the switch circuit may be constituted by a PMOS transistor.

FIG. 12 is a circuit diagram corresponding to the first embodiment in the case where the switch circuit is constituted by PMOS transistors. When the switch circuit is constituted by PMOS transistors, the MOS transistors in the drive circuit 4 are
And the MOS transistor in the cross latch load circuit 3 becomes N-type.

In the first and second embodiments described above, an example has been described in which one set of complementary output signals F and F bar is output from the switch circuit 1. However, a plurality of sets of complementary output signals are output from the switch circuit 1. And a voltage conversion circuit may be provided for each complementary output signal.

[0088]

As described above in detail, according to the present invention, since the output of the switch circuit is input to the control gate having a high input resistance of the voltage conversion circuit, no DC current flows inside the switch circuit. The operation of the voltage conversion circuit is not affected by the on-resistance inside the switch circuit. Therefore, when the pass transistor logic circuit of the present invention is formed on a semiconductor substrate, the size (formation area) of the MOS transistor inside the switch circuit can be reduced, the parasitic capacitance can be reduced, the operation speed can be improved, and the power consumption can be improved. Electric power can also be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of a pass transistor logic circuit.

FIG. 2 is a circuit diagram of a second embodiment of a pass transistor logic circuit.

FIG. 3 is a circuit diagram of a third embodiment of a pass transistor logic circuit.

FIG. 4 is an equivalent circuit diagram of the switch circuit shown in FIG.

FIG. 5 is a circuit diagram showing a specific configuration of a buffer shown in FIG. 3;

FIG. 6 is a circuit diagram of a fourth embodiment of a pass transistor logic circuit.

7 is an equivalent circuit diagram of the switch circuit shown in FIG.

FIG. 8 is a circuit diagram showing a specific configuration of a buffer shown in FIG. 5;

FIG. 9 is a circuit diagram for simulation of a complementary output type pass transistor logic circuit.

FIG. 10 is a circuit diagram for simulation of a single-output type pass transistor logic circuit.

FIG. 11 is a plot diagram showing a simulation result.

FIG. 12 is a circuit diagram showing an example of a pass transistor logic circuit in a case where a switch circuit is configured by PMOS transistors.

FIG. 13 is a diagram illustrating an example of a switch circuit including four NMOS transistors.

FIG. 14 is an equivalent circuit diagram of FIG.

FIG. 15 is a diagram in which three NMOS transistors are connected in series to form a switch circuit.

FIG. 16 is a circuit diagram showing an example of a conventional pass transistor logic circuit including a voltage conversion circuit.

FIG. 17 is a circuit diagram illustrating an example of a single-output type pass transistor logic circuit.

18 is an equivalent circuit diagram of FIG.

19 is a circuit diagram showing a specific configuration of the inverter shown in FIG.

[Description of Signs] 1, 1a switch circuit 2 voltage conversion circuit 3 cross latch load circuit 4 drive circuit 5 RS flip-flop 6, 6a buffer 51 latch circuit

Claims (11)

[Claims] 1. An N-type or P-type MO
A switch circuit configured by combining a plurality of S-transistors and performing a predetermined logical operation based on the logic of a plurality of types of complementary input signals, for complementary output; and a voltage for amplifying the complementary output voltage output from the switch circuit A conversion circuit, wherein the voltage conversion circuit includes a first output terminal and a second output terminal. The second output terminal of the voltage conversion circuit outputs first and second power supply voltages corresponding to the complementary output voltage. And a control gate having a high input resistance to which a complementary output voltage outputted from the circuit is applied, and the inside of the circuit is controlled in accordance with the complementary output voltage so that one voltage of the output terminal becomes the first power supply voltage. A drive circuit for controlling a flowing current; and a circuit inside according to the output terminal voltage so that the other voltage of the output terminal becomes the second power supply voltage. Pass-transistor logic circuit, comprising a load circuit, the controlling the current. 2. The switch circuit and the drive circuit,
2. The pass transistor logic circuit according to claim 1, wherein the load circuit is formed of a first conductivity type MOS transistor, and the load circuit is formed of a second conductivity type MOS transistor. 3. The driving circuit includes first and second MOS transistors of a first conductivity type, and gate terminals of the first and second MOS transistors are used as the control gates. Are third and fourth MOSs of the second conductivity type.
A source terminal of the first and second MOS transistors is set to the first power supply voltage; and a source terminal of the third and fourth MOS transistors is set to the second power supply voltage. The drain terminals of the first and third MOS transistors and the gate terminal of the fourth MOS transistor are commonly connected to one of the output terminals, and the drain terminal of the second and fourth MOS transistors is connected to the drain terminal of the second and fourth MOS transistors. Third M
3. The pass transistor logic circuit according to claim 2, wherein the gate terminal of the OS transistor is commonly connected to the other of the output terminals. 4. The switch circuit and the drive circuit so that the complementary output voltage corresponding to logic "1" is higher than a logic threshold voltage of the voltage conversion circuit. The pass transistor logic circuit according to any one of claims 1 to 3. 5. An N-type or P-type MO
A pass transistor logic circuit including a plurality of S transistors and including a switch circuit that complementarily outputs a result of performing a predetermined logical operation based on the logic of a plurality of types of complementary input signals, wherein the output signal is output from the switch circuit. An RS flip-flop that is set or reset in accordance with a complementary output voltage, wherein the RS flip-flop has two output terminals respectively holding state voltages substantially equal to first and second power supply voltages; A control gate having a high input resistance to which the outputted complementary output voltage is applied, and flowing through the inside of the circuit according to the complementary output voltage so that one voltage of the output terminal becomes the first power supply voltage A drive circuit for controlling current; one of the output terminals is held at the first power supply voltage;
A latch circuit that controls a current flowing through the inside of the circuit based on the output terminal voltage so that the other of the output terminals is held at the second power supply voltage. A pass transistor logic circuit connected to a connection path with the latch circuit. 6. The pass transistor logic circuit according to claim 5, wherein the MOS transistor forming the switch circuit and the MOS transistor forming the drive circuit have the same conductivity type. 7. The driving circuit comprises first and second MOS transistors of a first conductivity type, and the latch circuit comprises third and fourth MOS transistors of a first conductivity type.
S transistor and fifth and sixth MOSs of second conductivity type
A source terminal of the third and fourth MOS transistors is set to the first power supply voltage; a source terminal of the fifth and sixth MOS transistors is set to the second power supply voltage The gate terminals of the third and fifth MOS transistors and the drain terminals of the second, fourth and sixth MOS transistors are commonly connected to one of the output terminals. A gate terminal of the first and second MOS transistors; and a gate terminal of the first, second and third MOS transistors, and a drain terminal of the first, third, and fifth MOS transistors. 7. The pass transistor logic circuit according to claim 6, wherein said circuit is used as said control gate. 8. An N-type or P-type MO
A switch circuit configured by combining a plurality of S transistors and performing a single logical operation based on the logic of a plurality of types of complementary input signals, and a voltage for amplifying a single output voltage output from the switch circuit And a first conversion circuit and a second conversion circuit from an output terminal of the voltage conversion circuit.
A pass transistor logic circuit that single-outputs any one of the power supply voltages, wherein the voltage conversion circuit has a control gate with a high input resistance to which a single output voltage output from the switch circuit is applied, and the output terminal A drive circuit that controls a current flowing inside the circuit according to the single output voltage so that a voltage becomes the first power supply voltage; and a drive circuit that controls the output terminal voltage to be the second power supply voltage.
A load circuit for controlling a current flowing inside the circuit in accordance with the output terminal voltage. 9. The drive circuit includes a first conductivity type first MOS transistor having a source terminal set to the first power supply voltage and a drain terminal connected to the output terminal. The load circuit includes a second MOS transistor of a second conductivity type having a drain terminal connected to the output terminal, a source terminal set to the second power supply voltage, and a drain terminal connected to a source of the second MOS transistor. A third MOS transistor of a second conductivity type connected to a terminal; and a power storage circuit for storing a charge in a connection path between the second and third MOS transistors. Gate terminals are connected to each other and used as the control gate, and an inverted voltage of the output terminal voltage is applied to a gate terminal of the third MOS transistor. Pass-transistor logic circuit according to claim 8, characterized in that it is. 10. The driving circuit, wherein a source terminal of the driving circuit is the first terminal.
And a first MOS transistor of a first conductivity type having a drain terminal connected to the output terminal. The load circuit includes a second MOS transistor having a drain terminal connected to the output terminal. A conductive second MOS transistor, a source terminal connected to the source terminal of the second MOS transistor, and a drain terminal of a first conductive type depletion type third terminal set to the second power supply voltage. MOS
A transistor, and a power storage circuit that stores electric charge in a connection path between the second and third MOS transistors. Control terminals of the first and second MOS transistors are connected to each other and used as the control gate, 9. The pass transistor logic circuit according to claim 8, wherein an inverted voltage of said output terminal voltage is applied to a gate terminal of said third MOS transistor. 11. A power storage circuit comprising: a capacitor element having one end connected to a source terminal of the second MOS transistor and the other end set to the first power supply voltage; and a source terminal connected to the second power supply voltage. A fourth MOS transistor set to a voltage and having a drain terminal connected to a source terminal of the second MOS transistor; and a gate terminal of the fourth MOS transistor periodically charging the capacitor element. The pass transistor logic circuit according to claim 9, wherein a clock for inputting the data is input.